[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / clocksource / sh_tmu.c

/*
 * SuperH Timer Support - TMU
 *
 *  Copyright (C) 2009 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/sh_timer.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>

struct sh_tmu_priv {
	void __iomem *mapbase;
	struct clk *clk;
	struct irqaction irqaction;
	struct platform_device *pdev;
	unsigned long rate;
	unsigned long periodic;
	struct clock_event_device ced;
	struct clocksource cs;
	bool cs_enabled;
	unsigned int enable_count;
};

static DEFINE_RAW_SPINLOCK(sh_tmu_lock);

#define TSTR -1 /* shared register */
#define TCOR  0 /* channel register */
#define TCNT 1 /* channel register */
#define TCR 2 /* channel register */

static inline unsigned long sh_tmu_read(struct sh_tmu_priv *p, int reg_nr)
{
	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
	void __iomem *base = p->mapbase;
	unsigned long offs;

	if (reg_nr == TSTR)
		return ioread8(base - cfg->channel_offset);

	offs = reg_nr << 2;

	if (reg_nr == TCR)
		return ioread16(base + offs);
	else
		return ioread32(base + offs);
}

static inline void sh_tmu_write(struct sh_tmu_priv *p, int reg_nr,
				unsigned long value)
{
	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
	void __iomem *base = p->mapbase;
	unsigned long offs;

	if (reg_nr == TSTR) {
		iowrite8(value, base - cfg->channel_offset);
		return;
	}

	offs = reg_nr << 2;

	if (reg_nr == TCR)
		iowrite16(value, base + offs);
	else
		iowrite32(value, base + offs);
}

static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
{
	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
	unsigned long flags, value;

	/* start stop register shared by multiple timer channels */
	raw_spin_lock_irqsave(&sh_tmu_lock, flags);
	value = sh_tmu_read(p, TSTR);

	if (start)
		value |= 1 << cfg->timer_bit;
	else
		value &= ~(1 << cfg->timer_bit);

	sh_tmu_write(p, TSTR, value);
	raw_spin_unlock_irqrestore(&sh_tmu_lock, flags);
}

static int __sh_tmu_enable(struct sh_tmu_priv *p)
{
	int ret;

	/* enable clock */
	ret = clk_enable(p->clk);
	if (ret) {
		dev_err(&p->pdev->dev, "cannot enable clock\n");
		return ret;
	}

	/* make sure channel is disabled */
	sh_tmu_start_stop_ch(p, 0);

	/* maximum timeout */
	sh_tmu_write(p, TCOR, 0xffffffff);
	sh_tmu_write(p, TCNT, 0xffffffff);

	/* configure channel to parent clock / 4, irq off */
	p->rate = clk_get_rate(p->clk) / 4;
	sh_tmu_write(p, TCR, 0x0000);

	/* enable channel */
	sh_tmu_start_stop_ch(p, 1);

	return 0;
}

static int sh_tmu_enable(struct sh_tmu_priv *p)
{
	if (p->enable_count++ > 0)
		return 0;

	pm_runtime_get_sync(&p->pdev->dev);
	dev_pm_syscore_device(&p->pdev->dev, true);

	return __sh_tmu_enable(p);
}

static void __sh_tmu_disable(struct sh_tmu_priv *p)
{
	/* disable channel */
	sh_tmu_start_stop_ch(p, 0);

	/* disable interrupts in TMU block */
	sh_tmu_write(p, TCR, 0x0000);

	/* stop clock */
	clk_disable(p->clk);
}

static void sh_tmu_disable(struct sh_tmu_priv *p)
{
	if (WARN_ON(p->enable_count == 0))
		return;

	if (--p->enable_count > 0)
		return;

	__sh_tmu_disable(p);

	dev_pm_syscore_device(&p->pdev->dev, false);
	pm_runtime_put(&p->pdev->dev);
}

static void sh_tmu_set_next(struct sh_tmu_priv *p, unsigned long delta,
			    int periodic)
{
	/* stop timer */
	sh_tmu_start_stop_ch(p, 0);

	/* acknowledge interrupt */
	sh_tmu_read(p, TCR);

	/* enable interrupt */
	sh_tmu_write(p, TCR, 0x0020);

	/* reload delta value in case of periodic timer */
	if (periodic)
		sh_tmu_write(p, TCOR, delta);
	else
		sh_tmu_write(p, TCOR, 0xffffffff);

	sh_tmu_write(p, TCNT, delta);

	/* start timer */
	sh_tmu_start_stop_ch(p, 1);
}

static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
{
	struct sh_tmu_priv *p = dev_id;

	/* disable or acknowledge interrupt */
	if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT)
		sh_tmu_write(p, TCR, 0x0000);
	else
		sh_tmu_write(p, TCR, 0x0020);

	/* notify clockevent layer */
	p->ced.event_handler(&p->ced);
	return IRQ_HANDLED;
}

static struct sh_tmu_priv *cs_to_sh_tmu(struct clocksource *cs)
{
	return container_of(cs, struct sh_tmu_priv, cs);
}

static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
{
	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);

	return sh_tmu_read(p, TCNT) ^ 0xffffffff;
}

static int sh_tmu_clocksource_enable(struct clocksource *cs)
{
	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
	int ret;

	if (WARN_ON(p->cs_enabled))
		return 0;

	ret = sh_tmu_enable(p);
	if (!ret) {
		__clocksource_updatefreq_hz(cs, p->rate);
		p->cs_enabled = true;
	}

	return ret;
}

static void sh_tmu_clocksource_disable(struct clocksource *cs)
{
	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);

	if (WARN_ON(!p->cs_enabled))
		return;

	sh_tmu_disable(p);
	p->cs_enabled = false;
}

static void sh_tmu_clocksource_suspend(struct clocksource *cs)
{
	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);

	if (!p->cs_enabled)
		return;

	if (--p->enable_count == 0) {
		__sh_tmu_disable(p);
		pm_genpd_syscore_poweroff(&p->pdev->dev);
	}
}

static void sh_tmu_clocksource_resume(struct clocksource *cs)
{
	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);

	if (!p->cs_enabled)
		return;

	if (p->enable_count++ == 0) {
		pm_genpd_syscore_poweron(&p->pdev->dev);
		__sh_tmu_enable(p);
	}
}

static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
				       char *name, unsigned long rating)
{
	struct clocksource *cs = &p->cs;

	cs->name = name;
	cs->rating = rating;
	cs->read = sh_tmu_clocksource_read;
	cs->enable = sh_tmu_clocksource_enable;
	cs->disable = sh_tmu_clocksource_disable;
	cs->suspend = sh_tmu_clocksource_suspend;
	cs->resume = sh_tmu_clocksource_resume;
	cs->mask = CLOCKSOURCE_MASK(32);
	cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;

	dev_info(&p->pdev->dev, "used as clock source\n");

	/* Register with dummy 1 Hz value, gets updated in ->enable() */
	clocksource_register_hz(cs, 1);
	return 0;
}

static struct sh_tmu_priv *ced_to_sh_tmu(struct clock_event_device *ced)
{
	return container_of(ced, struct sh_tmu_priv, ced);
}

static void sh_tmu_clock_event_start(struct sh_tmu_priv *p, int periodic)
{
	struct clock_event_device *ced = &p->ced;

	sh_tmu_enable(p);

	clockevents_config(ced, p->rate);

	if (periodic) {
		p->periodic = (p->rate + HZ/2) / HZ;
		sh_tmu_set_next(p, p->periodic, 1);
	}
}

static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
				    struct clock_event_device *ced)
{
	struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
	int disabled = 0;

	/* deal with old setting first */
	switch (ced->mode) {
	case CLOCK_EVT_MODE_PERIODIC:
	case CLOCK_EVT_MODE_ONESHOT:
		sh_tmu_disable(p);
		disabled = 1;
		break;
	default:
		break;
	}

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		dev_info(&p->pdev->dev, "used for periodic clock events\n");
		sh_tmu_clock_event_start(p, 1);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		dev_info(&p->pdev->dev, "used for oneshot clock events\n");
		sh_tmu_clock_event_start(p, 0);
		break;
	case CLOCK_EVT_MODE_UNUSED:
		if (!disabled)
			sh_tmu_disable(p);
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	default:
		break;
	}
}

static int sh_tmu_clock_event_next(unsigned long delta,
				   struct clock_event_device *ced)
{
	struct sh_tmu_priv *p = ced_to_sh_tmu(ced);

	BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);

	/* program new delta value */
	sh_tmu_set_next(p, delta, 0);
	return 0;
}

static void sh_tmu_clock_event_suspend(struct clock_event_device *ced)
{
	pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->pdev->dev);
}

static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
{
	pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->pdev->dev);
}

static void sh_tmu_register_clockevent(struct sh_tmu_priv *p,
				       char *name, unsigned long rating)
{
	struct clock_event_device *ced = &p->ced;
	int ret;

	memset(ced, 0, sizeof(*ced));

	ced->name = name;
	ced->features = CLOCK_EVT_FEAT_PERIODIC;
	ced->features |= CLOCK_EVT_FEAT_ONESHOT;
	ced->rating = rating;
	ced->cpumask = cpumask_of(0);
	ced->set_next_event = sh_tmu_clock_event_next;
	ced->set_mode = sh_tmu_clock_event_mode;
	ced->suspend = sh_tmu_clock_event_suspend;
	ced->resume = sh_tmu_clock_event_resume;

	dev_info(&p->pdev->dev, "used for clock events\n");

	clockevents_config_and_register(ced, 1, 0x300, 0xffffffff);

	ret = setup_irq(p->irqaction.irq, &p->irqaction);
	if (ret) {
		dev_err(&p->pdev->dev, "failed to request irq %d\n",
			p->irqaction.irq);
		return;
	}
}

static int sh_tmu_register(struct sh_tmu_priv *p, char *name,
		    unsigned long clockevent_rating,
		    unsigned long clocksource_rating)
{
	if (clockevent_rating)
		sh_tmu_register_clockevent(p, name, clockevent_rating);
	else if (clocksource_rating)
		sh_tmu_register_clocksource(p, name, clocksource_rating);

	return 0;
}

static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
{
	struct sh_timer_config *cfg = pdev->dev.platform_data;
	struct resource *res;
	int irq, ret;
	ret = -ENXIO;

	memset(p, 0, sizeof(*p));
	p->pdev = pdev;

	if (!cfg) {
		dev_err(&p->pdev->dev, "missing platform data\n");
		goto err0;
	}

	platform_set_drvdata(pdev, p);

	res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&p->pdev->dev, "failed to get I/O memory\n");
		goto err0;
	}

	irq = platform_get_irq(p->pdev, 0);
	if (irq < 0) {
		dev_err(&p->pdev->dev, "failed to get irq\n");
		goto err0;
	}

	/* map memory, let mapbase point to our channel */
	p->mapbase = ioremap_nocache(res->start, resource_size(res));
	if (p->mapbase == NULL) {
		dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
		goto err0;
	}

	/* setup data for setup_irq() (too early for request_irq()) */
	p->irqaction.name = dev_name(&p->pdev->dev);
	p->irqaction.handler = sh_tmu_interrupt;
	p->irqaction.dev_id = p;
	p->irqaction.irq = irq;
	p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
			     IRQF_IRQPOLL  | IRQF_NOBALANCING;

	/* get hold of clock */
	p->clk = clk_get(&p->pdev->dev, "tmu_fck");
	if (IS_ERR(p->clk)) {
		dev_err(&p->pdev->dev, "cannot get clock\n");
		ret = PTR_ERR(p->clk);
		goto err1;
	}
	p->cs_enabled = false;
	p->enable_count = 0;

	return sh_tmu_register(p, (char *)dev_name(&p->pdev->dev),
			       cfg->clockevent_rating,
			       cfg->clocksource_rating);
 err1:
	iounmap(p->mapbase);
 err0:
	return ret;
}

static int sh_tmu_probe(struct platform_device *pdev)
{
	struct sh_tmu_priv *p = platform_get_drvdata(pdev);
	struct sh_timer_config *cfg = pdev->dev.platform_data;
	int ret;

	if (!is_early_platform_device(pdev)) {
		pm_runtime_set_active(&pdev->dev);
		pm_runtime_enable(&pdev->dev);
	}

	if (p) {
		dev_info(&pdev->dev, "kept as earlytimer\n");
		goto out;
	}

	p = kmalloc(sizeof(*p), GFP_KERNEL);
	if (p == NULL) {
		dev_err(&pdev->dev, "failed to allocate driver data\n");
		return -ENOMEM;
	}

	ret = sh_tmu_setup(p, pdev);
	if (ret) {
		kfree(p);
		platform_set_drvdata(pdev, NULL);
		pm_runtime_idle(&pdev->dev);
		return ret;
	}
	if (is_early_platform_device(pdev))
		return 0;

 out:
	if (cfg->clockevent_rating || cfg->clocksource_rating)
		pm_runtime_irq_safe(&pdev->dev);
	else
		pm_runtime_idle(&pdev->dev);

	return 0;
}

static int sh_tmu_remove(struct platform_device *pdev)
{
	return -EBUSY; /* cannot unregister clockevent and clocksource */
}

static struct platform_driver sh_tmu_device_driver = {
	.probe		= sh_tmu_probe,
	.remove		= sh_tmu_remove,
	.driver		= {
		.name	= "sh_tmu",
	}
};

static int __init sh_tmu_init(void)
{
	return platform_driver_register(&sh_tmu_device_driver);
}

static void __exit sh_tmu_exit(void)
{
	platform_driver_unregister(&sh_tmu_device_driver);
}

early_platform_init("earlytimer", &sh_tmu_device_driver);
subsys_initcall(sh_tmu_init);
module_exit(sh_tmu_exit);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("SuperH TMU Timer Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9570ef20 MD	1	/*
	2	* SuperH Timer Support - TMU
	3	*
	4	* Copyright (C) 2009 Magnus Damm
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/ioport.h>
	25	#include <linux/delay.h>
	26	#include <linux/io.h>
	27	#include <linux/clk.h>
	28	#include <linux/irq.h>
	29	#include <linux/err.h>
	30	#include <linux/clocksource.h>
	31	#include <linux/clockchips.h>
46a12f74	32	#include <linux/sh_timer.h>
5a0e3ad6	33	#include <linux/slab.h>
7deeab5d	34	#include <linux/module.h>
2ee619f9	35	#include <linux/pm_domain.h>
eaa49a8c	36	#include <linux/pm_runtime.h>
9570ef20 MD	37
	38	struct sh_tmu_priv {
	39	void __iomem *mapbase;
	40	struct clk *clk;
	41	struct irqaction irqaction;
	42	struct platform_device *pdev;
	43	unsigned long rate;
	44	unsigned long periodic;
	45	struct clock_event_device ced;
	46	struct clocksource cs;
eaa49a8c	47	bool cs_enabled;
61a53bfa	48	unsigned int enable_count;
9570ef20 MD	49	};
9570ef20 MD	50
c2225a57	51	static DEFINE_RAW_SPINLOCK(sh_tmu_lock);
9570ef20 MD	52
	53	#define TSTR -1 /* shared register */
	54	#define TCOR 0 /* channel register */
	55	#define TCNT 1 /* channel register */
	56	#define TCR 2 /* channel register */
	57
	58	static inline unsigned long sh_tmu_read(struct sh_tmu_priv *p, int reg_nr)
	59	{
46a12f74	60	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
9570ef20 MD	61	void __iomem *base = p->mapbase;
	62	unsigned long offs;
	63
	64	if (reg_nr == TSTR)
	65	return ioread8(base - cfg->channel_offset);
	66
	67	offs = reg_nr << 2;
	68
	69	if (reg_nr == TCR)
	70	return ioread16(base + offs);
	71	else
	72	return ioread32(base + offs);
	73	}
	74
	75	static inline void sh_tmu_write(struct sh_tmu_priv *p, int reg_nr,
	76	unsigned long value)
	77	{
46a12f74	78	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
9570ef20 MD	79	void __iomem *base = p->mapbase;
	80	unsigned long offs;
	81
	82	if (reg_nr == TSTR) {
	83	iowrite8(value, base - cfg->channel_offset);
	84	return;
	85	}
	86
	87	offs = reg_nr << 2;
	88
	89	if (reg_nr == TCR)
	90	iowrite16(value, base + offs);
	91	else
	92	iowrite32(value, base + offs);
	93	}
	94
	95	static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
	96	{
46a12f74	97	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
9570ef20 MD	98	unsigned long flags, value;
	99
	100	/* start stop register shared by multiple timer channels */
c2225a57	101	raw_spin_lock_irqsave(&sh_tmu_lock, flags);
9570ef20 MD	102	value = sh_tmu_read(p, TSTR);
	103
	104	if (start)
	105	value \|= 1 << cfg->timer_bit;
	106	else
	107	value &= ~(1 << cfg->timer_bit);
	108
	109	sh_tmu_write(p, TSTR, value);
c2225a57	110	raw_spin_unlock_irqrestore(&sh_tmu_lock, flags);
9570ef20 MD	111	}
9570ef20 MD	112
61a53bfa	113	static int __sh_tmu_enable(struct sh_tmu_priv *p)
9570ef20	114	{
9570ef20 MD	115	int ret;
9570ef20 MD	116
d4905ce3	117	/* enable clock */
9570ef20 MD	118	ret = clk_enable(p->clk);
9570ef20 MD	119	if (ret) {
214a607a	120	dev_err(&p->pdev->dev, "cannot enable clock\n");
9570ef20 MD	121	return ret;
	122	}
	123
	124	/* make sure channel is disabled */
	125	sh_tmu_start_stop_ch(p, 0);
	126
	127	/* maximum timeout */
	128	sh_tmu_write(p, TCOR, 0xffffffff);
	129	sh_tmu_write(p, TCNT, 0xffffffff);
	130
	131	/* configure channel to parent clock / 4, irq off */
	132	p->rate = clk_get_rate(p->clk) / 4;
	133	sh_tmu_write(p, TCR, 0x0000);
	134
	135	/* enable channel */
	136	sh_tmu_start_stop_ch(p, 1);
	137
	138	return 0;
	139	}
	140
61a53bfa RW	141	static int sh_tmu_enable(struct sh_tmu_priv *p)
	142	{
	143	if (p->enable_count++ > 0)
	144	return 0;
	145
	146	pm_runtime_get_sync(&p->pdev->dev);
	147	dev_pm_syscore_device(&p->pdev->dev, true);
	148
	149	return __sh_tmu_enable(p);
	150	}
	151
	152	static void __sh_tmu_disable(struct sh_tmu_priv *p)
9570ef20 MD	153	{
	154	/* disable channel */
	155	sh_tmu_start_stop_ch(p, 0);
	156
be890a1a MD	157	/* disable interrupts in TMU block */
	158	sh_tmu_write(p, TCR, 0x0000);
	159
d4905ce3	160	/* stop clock */
9570ef20 MD	161	clk_disable(p->clk);
	162	}
	163
61a53bfa RW	164	static void sh_tmu_disable(struct sh_tmu_priv *p)
	165	{
	166	if (WARN_ON(p->enable_count == 0))
	167	return;
	168
	169	if (--p->enable_count > 0)
	170	return;
	171
	172	__sh_tmu_disable(p);
	173
	174	dev_pm_syscore_device(&p->pdev->dev, false);
	175	pm_runtime_put(&p->pdev->dev);
	176	}
	177
9570ef20 MD	178	static void sh_tmu_set_next(struct sh_tmu_priv *p, unsigned long delta,
	179	int periodic)
	180	{
	181	/* stop timer */
	182	sh_tmu_start_stop_ch(p, 0);
	183
	184	/* acknowledge interrupt */
	185	sh_tmu_read(p, TCR);
	186
	187	/* enable interrupt */
	188	sh_tmu_write(p, TCR, 0x0020);
	189
	190	/* reload delta value in case of periodic timer */
	191	if (periodic)
	192	sh_tmu_write(p, TCOR, delta);
	193	else
6f4b67b8	194	sh_tmu_write(p, TCOR, 0xffffffff);
9570ef20 MD	195
	196	sh_tmu_write(p, TCNT, delta);
	197
	198	/* start timer */
	199	sh_tmu_start_stop_ch(p, 1);
	200	}
	201
	202	static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
	203	{
	204	struct sh_tmu_priv *p = dev_id;
	205
	206	/* disable or acknowledge interrupt */
	207	if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT)
	208	sh_tmu_write(p, TCR, 0x0000);
	209	else
	210	sh_tmu_write(p, TCR, 0x0020);
	211
	212	/* notify clockevent layer */
	213	p->ced.event_handler(&p->ced);
	214	return IRQ_HANDLED;
	215	}
	216
	217	static struct sh_tmu_priv cs_to_sh_tmu(struct clocksource cs)
	218	{
	219	return container_of(cs, struct sh_tmu_priv, cs);
	220	}
	221
	222	static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
	223	{
	224	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
	225
	226	return sh_tmu_read(p, TCNT) ^ 0xffffffff;
	227	}
	228
	229	static int sh_tmu_clocksource_enable(struct clocksource *cs)
	230	{
	231	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
0aeac458	232	int ret;
9570ef20	233
61a53bfa RW	234	if (WARN_ON(p->cs_enabled))
	235	return 0;
	236
0aeac458	237	ret = sh_tmu_enable(p);
eaa49a8c	238	if (!ret) {
0aeac458	239	__clocksource_updatefreq_hz(cs, p->rate);
eaa49a8c RW	240	p->cs_enabled = true;
eaa49a8c RW	241	}
61a53bfa	242
0aeac458	243	return ret;
9570ef20 MD	244	}
	245
	246	static void sh_tmu_clocksource_disable(struct clocksource *cs)
	247	{
eaa49a8c RW	248	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
eaa49a8c RW	249
61a53bfa RW	250	if (WARN_ON(!p->cs_enabled))
61a53bfa RW	251	return;
eaa49a8c RW	252
	253	sh_tmu_disable(p);
	254	p->cs_enabled = false;
	255	}
	256
	257	static void sh_tmu_clocksource_suspend(struct clocksource *cs)
	258	{
	259	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
	260
61a53bfa RW	261	if (!p->cs_enabled)
61a53bfa RW	262	return;
eaa49a8c	263
61a53bfa RW	264	if (--p->enable_count == 0) {
	265	__sh_tmu_disable(p);
	266	pm_genpd_syscore_poweroff(&p->pdev->dev);
	267	}
eaa49a8c RW	268	}
	269
	270	static void sh_tmu_clocksource_resume(struct clocksource *cs)
	271	{
	272	struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
	273
61a53bfa RW	274	if (!p->cs_enabled)
	275	return;
	276
	277	if (p->enable_count++ == 0) {
	278	pm_genpd_syscore_poweron(&p->pdev->dev);
	279	__sh_tmu_enable(p);
	280	}
9570ef20 MD	281	}
	282
	283	static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
	284	char *name, unsigned long rating)
	285	{
	286	struct clocksource *cs = &p->cs;
	287
	288	cs->name = name;
	289	cs->rating = rating;
	290	cs->read = sh_tmu_clocksource_read;
	291	cs->enable = sh_tmu_clocksource_enable;
	292	cs->disable = sh_tmu_clocksource_disable;
eaa49a8c RW	293	cs->suspend = sh_tmu_clocksource_suspend;
eaa49a8c RW	294	cs->resume = sh_tmu_clocksource_resume;
9570ef20 MD	295	cs->mask = CLOCKSOURCE_MASK(32);
9570ef20 MD	296	cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
66f49121	297
214a607a	298	dev_info(&p->pdev->dev, "used as clock source\n");
0aeac458 MD	299
	300	/* Register with dummy 1 Hz value, gets updated in ->enable() */
	301	clocksource_register_hz(cs, 1);
9570ef20 MD	302	return 0;
	303	}
	304
	305	static struct sh_tmu_priv ced_to_sh_tmu(struct clock_event_device ced)
	306	{
	307	return container_of(ced, struct sh_tmu_priv, ced);
	308	}
	309
	310	static void sh_tmu_clock_event_start(struct sh_tmu_priv *p, int periodic)
	311	{
	312	struct clock_event_device *ced = &p->ced;
	313
	314	sh_tmu_enable(p);
	315
3977407e	316	clockevents_config(ced, p->rate);
9570ef20 MD	317
	318	if (periodic) {
	319	p->periodic = (p->rate + HZ/2) / HZ;
	320	sh_tmu_set_next(p, p->periodic, 1);
	321	}
	322	}
	323
	324	static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
	325	struct clock_event_device *ced)
	326	{
	327	struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
	328	int disabled = 0;
	329
	330	/* deal with old setting first */
	331	switch (ced->mode) {
	332	case CLOCK_EVT_MODE_PERIODIC:
	333	case CLOCK_EVT_MODE_ONESHOT:
	334	sh_tmu_disable(p);
	335	disabled = 1;
	336	break;
	337	default:
	338	break;
	339	}
	340
	341	switch (mode) {
	342	case CLOCK_EVT_MODE_PERIODIC:
214a607a	343	dev_info(&p->pdev->dev, "used for periodic clock events\n");
9570ef20 MD	344	sh_tmu_clock_event_start(p, 1);
	345	break;
	346	case CLOCK_EVT_MODE_ONESHOT:
214a607a	347	dev_info(&p->pdev->dev, "used for oneshot clock events\n");
9570ef20 MD	348	sh_tmu_clock_event_start(p, 0);
	349	break;
	350	case CLOCK_EVT_MODE_UNUSED:
	351	if (!disabled)
	352	sh_tmu_disable(p);
	353	break;
	354	case CLOCK_EVT_MODE_SHUTDOWN:
	355	default:
	356	break;
	357	}
	358	}
	359
	360	static int sh_tmu_clock_event_next(unsigned long delta,
	361	struct clock_event_device *ced)
	362	{
	363	struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
	364
	365	BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
	366
	367	/* program new delta value */
	368	sh_tmu_set_next(p, delta, 0);
	369	return 0;
	370	}
	371
eaa49a8c RW	372	static void sh_tmu_clock_event_suspend(struct clock_event_device *ced)
	373	{
	374	pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->pdev->dev);
	375	}
	376
	377	static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
	378	{
	379	pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->pdev->dev);
	380	}
	381
9570ef20 MD	382	static void sh_tmu_register_clockevent(struct sh_tmu_priv *p,
	383	char *name, unsigned long rating)
	384	{
	385	struct clock_event_device *ced = &p->ced;
	386	int ret;
	387
	388	memset(ced, 0, sizeof(*ced));
	389
	390	ced->name = name;
	391	ced->features = CLOCK_EVT_FEAT_PERIODIC;
	392	ced->features \|= CLOCK_EVT_FEAT_ONESHOT;
	393	ced->rating = rating;
	394	ced->cpumask = cpumask_of(0);
	395	ced->set_next_event = sh_tmu_clock_event_next;
	396	ced->set_mode = sh_tmu_clock_event_mode;
eaa49a8c RW	397	ced->suspend = sh_tmu_clock_event_suspend;
eaa49a8c RW	398	ced->resume = sh_tmu_clock_event_resume;
9570ef20	399
214a607a	400	dev_info(&p->pdev->dev, "used for clock events\n");
3977407e PM	401
3977407e PM	402	clockevents_config_and_register(ced, 1, 0x300, 0xffffffff);
da64c2a8	403
9570ef20 MD	404	ret = setup_irq(p->irqaction.irq, &p->irqaction);
9570ef20 MD	405	if (ret) {
214a607a PM	406	dev_err(&p->pdev->dev, "failed to request irq %d\n",
214a607a PM	407	p->irqaction.irq);
9570ef20 MD	408	return;
9570ef20 MD	409	}
9570ef20 MD	410	}
	411
	412	static int sh_tmu_register(struct sh_tmu_priv p, char name,
	413	unsigned long clockevent_rating,
	414	unsigned long clocksource_rating)
	415	{
	416	if (clockevent_rating)
	417	sh_tmu_register_clockevent(p, name, clockevent_rating);
	418	else if (clocksource_rating)
	419	sh_tmu_register_clocksource(p, name, clocksource_rating);
	420
	421	return 0;
	422	}
	423
	424	static int sh_tmu_setup(struct sh_tmu_priv p, struct platform_device pdev)
	425	{
46a12f74	426	struct sh_timer_config *cfg = pdev->dev.platform_data;
9570ef20 MD	427	struct resource *res;
	428	int irq, ret;
	429	ret = -ENXIO;
	430
	431	memset(p, 0, sizeof(*p));
	432	p->pdev = pdev;
	433
	434	if (!cfg) {
	435	dev_err(&p->pdev->dev, "missing platform data\n");
	436	goto err0;
	437	}
	438
	439	platform_set_drvdata(pdev, p);
	440
	441	res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
	442	if (!res) {
	443	dev_err(&p->pdev->dev, "failed to get I/O memory\n");
	444	goto err0;
	445	}
	446
	447	irq = platform_get_irq(p->pdev, 0);
	448	if (irq < 0) {
	449	dev_err(&p->pdev->dev, "failed to get irq\n");
	450	goto err0;
	451	}
	452
	453	/* map memory, let mapbase point to our channel */
	454	p->mapbase = ioremap_nocache(res->start, resource_size(res));
	455	if (p->mapbase == NULL) {
214a607a	456	dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
9570ef20 MD	457	goto err0;
	458	}
	459
	460	/* setup data for setup_irq() (too early for request_irq()) */
214a607a	461	p->irqaction.name = dev_name(&p->pdev->dev);
9570ef20 MD	462	p->irqaction.handler = sh_tmu_interrupt;
	463	p->irqaction.dev_id = p;
	464	p->irqaction.irq = irq;
fecf066c PM	465	p->irqaction.flags = IRQF_DISABLED \| IRQF_TIMER \| \
fecf066c PM	466	IRQF_IRQPOLL \| IRQF_NOBALANCING;
9570ef20 MD	467
9570ef20 MD	468	/* get hold of clock */
c2a25e81	469	p->clk = clk_get(&p->pdev->dev, "tmu_fck");
9570ef20	470	if (IS_ERR(p->clk)) {
03ff858c MD	471	dev_err(&p->pdev->dev, "cannot get clock\n");
	472	ret = PTR_ERR(p->clk);
	473	goto err1;
9570ef20	474	}
61a53bfa RW	475	p->cs_enabled = false;
61a53bfa RW	476	p->enable_count = 0;
9570ef20	477
214a607a	478	return sh_tmu_register(p, (char *)dev_name(&p->pdev->dev),
9570ef20 MD	479	cfg->clockevent_rating,
	480	cfg->clocksource_rating);
	481	err1:
	482	iounmap(p->mapbase);
	483	err0:
	484	return ret;
	485	}
	486
1850514b	487	static int sh_tmu_probe(struct platform_device *pdev)
9570ef20 MD	488	{
9570ef20 MD	489	struct sh_tmu_priv *p = platform_get_drvdata(pdev);
61a53bfa	490	struct sh_timer_config *cfg = pdev->dev.platform_data;
9570ef20 MD	491	int ret;
9570ef20 MD	492
eaa49a8c	493	if (!is_early_platform_device(pdev)) {
61a53bfa RW	494	pm_runtime_set_active(&pdev->dev);
61a53bfa RW	495	pm_runtime_enable(&pdev->dev);
eaa49a8c	496	}
2ee619f9	497
9570ef20	498	if (p) {
214a607a	499	dev_info(&pdev->dev, "kept as earlytimer\n");
61a53bfa	500	goto out;
9570ef20 MD	501	}
	502
	503	p = kmalloc(sizeof(*p), GFP_KERNEL);
	504	if (p == NULL) {
	505	dev_err(&pdev->dev, "failed to allocate driver data\n");
	506	return -ENOMEM;
	507	}
	508
	509	ret = sh_tmu_setup(p, pdev);
	510	if (ret) {
	511	kfree(p);
	512	platform_set_drvdata(pdev, NULL);
61a53bfa RW	513	pm_runtime_idle(&pdev->dev);
61a53bfa RW	514	return ret;
9570ef20	515	}
61a53bfa RW	516	if (is_early_platform_device(pdev))
	517	return 0;
	518
	519	out:
	520	if (cfg->clockevent_rating \|\| cfg->clocksource_rating)
	521	pm_runtime_irq_safe(&pdev->dev);
	522	else
	523	pm_runtime_idle(&pdev->dev);
	524
	525	return 0;
9570ef20 MD	526	}
9570ef20 MD	527
1850514b	528	static int sh_tmu_remove(struct platform_device *pdev)
9570ef20 MD	529	{
	530	return -EBUSY; /* cannot unregister clockevent and clocksource */
	531	}
	532
	533	static struct platform_driver sh_tmu_device_driver = {
	534	.probe = sh_tmu_probe,
1850514b	535	.remove = sh_tmu_remove,
9570ef20 MD	536	.driver = {
	537	.name = "sh_tmu",
	538	}
	539	};
	540
	541	static int __init sh_tmu_init(void)
	542	{
	543	return platform_driver_register(&sh_tmu_device_driver);
	544	}
	545
	546	static void __exit sh_tmu_exit(void)
	547	{
	548	platform_driver_unregister(&sh_tmu_device_driver);
	549	}
	550
	551	early_platform_init("earlytimer", &sh_tmu_device_driver);
b9773c3f	552	subsys_initcall(sh_tmu_init);
9570ef20 MD	553	module_exit(sh_tmu_exit);
	554
	555	MODULE_AUTHOR("Magnus Damm");
	556	MODULE_DESCRIPTION("SuperH TMU Timer Driver");
	557	MODULE_LICENSE("GPL v2");