[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / clocksource / samsung_pwm_timer.c

/*
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com/
 *
 * samsung - Common hr-timer support (s3c and s5p)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <clocksource/samsung_pwm.h>

#include <asm/sched_clock.h>

/*
 * Clocksource driver
 */

#define REG_TCFG0			0x00
#define REG_TCFG1			0x04
#define REG_TCON			0x08
#define REG_TINT_CSTAT			0x44

#define REG_TCNTB(chan)			(0x0c + 12 * (chan))
#define REG_TCMPB(chan)			(0x10 + 12 * (chan))

#define TCFG0_PRESCALER_MASK		0xff
#define TCFG0_PRESCALER1_SHIFT		8

#define TCFG1_SHIFT(x)	  		((x) * 4)
#define TCFG1_MUX_MASK	  		0xf

#define TCON_START(chan)		(1 << (4 * (chan) + 0))
#define TCON_MANUALUPDATE(chan)		(1 << (4 * (chan) + 1))
#define TCON_INVERT(chan)		(1 << (4 * (chan) + 2))
#define TCON_AUTORELOAD(chan)		(1 << (4 * (chan) + 3))

DEFINE_SPINLOCK(samsung_pwm_lock);
EXPORT_SYMBOL(samsung_pwm_lock);

struct samsung_pwm_clocksource {
	void __iomem *base;
	unsigned int irq[SAMSUNG_PWM_NUM];
	struct samsung_pwm_variant variant;

	struct clk *timerclk;

	unsigned int event_id;
	unsigned int source_id;
	unsigned int tcnt_max;
	unsigned int tscaler_div;
	unsigned int tdiv;

	unsigned long clock_count_per_tick;
};

static struct samsung_pwm_clocksource pwm;

static void samsung_timer_set_prescale(unsigned int channel, u16 prescale)
{
	unsigned long flags;
	u8 shift = 0;
	u32 reg;

	if (channel >= 2)
		shift = TCFG0_PRESCALER1_SHIFT;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	reg = readl(pwm.base + REG_TCFG0);
	reg &= ~(TCFG0_PRESCALER_MASK << shift);
	reg |= (prescale - 1) << shift;
	writel(reg, pwm.base + REG_TCFG0);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_timer_set_divisor(unsigned int channel, u8 divisor)
{
	u8 shift = TCFG1_SHIFT(channel);
	unsigned long flags;
	u32 reg;
	u8 bits;

	bits = (fls(divisor) - 1) - pwm.variant.div_base;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	reg = readl(pwm.base + REG_TCFG1);
	reg &= ~(TCFG1_MUX_MASK << shift);
	reg |= bits << shift;
	writel(reg, pwm.base + REG_TCFG1);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_time_stop(unsigned int channel)
{
	unsigned long tcon;
	unsigned long flags;

	if (channel > 0)
		++channel;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	tcon = __raw_readl(pwm.base + REG_TCON);
	tcon &= ~TCON_START(channel);
	__raw_writel(tcon, pwm.base + REG_TCON);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_time_setup(unsigned int channel, unsigned long tcnt)
{
	unsigned long tcon;
	unsigned long flags;
	unsigned int tcon_chan = channel;

	if (tcon_chan > 0)
		++tcon_chan;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	tcon = __raw_readl(pwm.base + REG_TCON);

	tcon &= ~(TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan));
	tcon |= TCON_MANUALUPDATE(tcon_chan);

	__raw_writel(tcnt, pwm.base + REG_TCNTB(channel));
	__raw_writel(tcnt, pwm.base + REG_TCMPB(channel));
	__raw_writel(tcon, pwm.base + REG_TCON);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_time_start(unsigned int channel, bool periodic)
{
	unsigned long tcon;
	unsigned long flags;

	if (channel > 0)
		++channel;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	tcon = __raw_readl(pwm.base + REG_TCON);

	tcon &= ~TCON_MANUALUPDATE(channel);
	tcon |= TCON_START(channel);

	if (periodic)
		tcon |= TCON_AUTORELOAD(channel);
	else
		tcon &= ~TCON_AUTORELOAD(channel);

	__raw_writel(tcon, pwm.base + REG_TCON);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static int samsung_set_next_event(unsigned long cycles,
				struct clock_event_device *evt)
{
	/*
	 * This check is needed to account for internal rounding
	 * errors inside clockevents core, which might result in
	 * passing cycles = 0, which in turn would not generate any
	 * timer interrupt and hang the system.
	 *
	 * Another solution would be to set up the clockevent device
	 * with min_delta = 2, but this would unnecessarily increase
	 * the minimum sleep period.
	 */
	if (!cycles)
		cycles = 1;

	samsung_time_setup(pwm.event_id, cycles);
	samsung_time_start(pwm.event_id, false);

	return 0;
}

static void samsung_timer_resume(void)
{
	/* event timer restart */
	samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1);
	samsung_time_start(pwm.event_id, true);

	/* source timer restart */
	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
	samsung_time_start(pwm.source_id, true);
}

static void samsung_set_mode(enum clock_event_mode mode,
				struct clock_event_device *evt)
{
	samsung_time_stop(pwm.event_id);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1);
		samsung_time_start(pwm.event_id, true);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
		break;

	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		break;

	case CLOCK_EVT_MODE_RESUME:
		samsung_timer_resume();
		break;
	}
}

static struct clock_event_device time_event_device = {
	.name		= "samsung_event_timer",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.rating		= 200,
	.set_next_event	= samsung_set_next_event,
	.set_mode	= samsung_set_mode,
};

static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	if (pwm.variant.has_tint_cstat) {
		u32 mask = (1 << pwm.event_id);
		writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
	}

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction samsung_clock_event_irq = {
	.name		= "samsung_time_irq",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= samsung_clock_event_isr,
	.dev_id		= &time_event_device,
};

static void __init samsung_clockevent_init(void)
{
	unsigned long pclk;
	unsigned long clock_rate;
	unsigned int irq_number;

	pclk = clk_get_rate(pwm.timerclk);

	samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
	samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);

	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
	pwm.clock_count_per_tick = clock_rate / HZ;

	time_event_device.cpumask = cpumask_of(0);
	clockevents_config_and_register(&time_event_device,
						clock_rate, 1, pwm.tcnt_max);

	irq_number = pwm.irq[pwm.event_id];
	setup_irq(irq_number, &samsung_clock_event_irq);

	if (pwm.variant.has_tint_cstat) {
		u32 mask = (1 << pwm.event_id);
		writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
	}
}

static void __iomem *samsung_timer_reg(void)
{
	switch (pwm.source_id) {
	case 0:
	case 1:
	case 2:
	case 3:
		return pwm.base + pwm.source_id * 0x0c + 0x14;

	case 4:
		return pwm.base + 0x40;

	default:
		BUG();
	}
}

/*
 * Override the global weak sched_clock symbol with this
 * local implementation which uses the clocksource to get some
 * better resolution when scheduling the kernel. We accept that
 * this wraps around for now, since it is just a relative time
 * stamp. (Inspired by U300 implementation.)
 */
static u32 notrace samsung_read_sched_clock(void)
{
	void __iomem *reg = samsung_timer_reg();

	if (!reg)
		return 0;

	return ~__raw_readl(reg);
}

static void __init samsung_clocksource_init(void)
{
	void __iomem *reg = samsung_timer_reg();
	unsigned long pclk;
	unsigned long clock_rate;
	int ret;

	pclk = clk_get_rate(pwm.timerclk);

	samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
	samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);

	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);

	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
	samsung_time_start(pwm.source_id, true);

	setup_sched_clock(samsung_read_sched_clock,
						pwm.variant.bits, clock_rate);

	ret = clocksource_mmio_init(reg, "samsung_clocksource_timer",
					clock_rate, 250, pwm.variant.bits,
					clocksource_mmio_readl_down);
	if (ret)
		panic("samsung_clocksource_timer: can't register clocksource\n");
}

static void __init samsung_timer_resources(void)
{
	pwm.timerclk = clk_get(NULL, "timers");
	if (IS_ERR(pwm.timerclk))
		panic("failed to get timers clock for timer");

	clk_prepare_enable(pwm.timerclk);

	pwm.tcnt_max = (1UL << pwm.variant.bits) - 1;
	if (pwm.variant.bits == 16) {
		pwm.tscaler_div = 25;
		pwm.tdiv = 2;
	} else {
		pwm.tscaler_div = 2;
		pwm.tdiv = 1;
	}
}

/*
 * PWM master driver
 */
static void __init _samsung_pwm_clocksource_init(void)
{
	u8 mask;
	int channel;

	mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1);
	channel = fls(mask) - 1;
	if (channel < 0)
		panic("failed to find PWM channel for clocksource");
	pwm.source_id = channel;

	mask &= ~(1 << channel);
	channel = fls(mask) - 1;
	if (channel < 0)
		panic("failed to find PWM channel for clock event");
	pwm.event_id = channel;

	samsung_timer_resources();
	samsung_clockevent_init();
	samsung_clocksource_init();
}

void __init samsung_pwm_clocksource_init(void __iomem *base,
			unsigned int *irqs, struct samsung_pwm_variant *variant)
{
	pwm.base = base;
	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
	memcpy(pwm.irq, irqs, SAMSUNG_PWM_NUM * sizeof(*irqs));

	_samsung_pwm_clocksource_init();
}

#ifdef CONFIG_CLKSRC_OF
static void __init samsung_pwm_alloc(struct device_node *np,
				     const struct samsung_pwm_variant *variant)
{
	struct resource res;
	struct property *prop;
	const __be32 *cur;
	u32 val;
	int i;

	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
	for (i = 0; i < SAMSUNG_PWM_NUM; ++i)
		pwm.irq[i] = irq_of_parse_and_map(np, i);

	of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
		if (val >= SAMSUNG_PWM_NUM) {
			pr_warning("%s: invalid channel index in samsung,pwm-outputs property\n",
								__func__);
			continue;
		}
		pwm.variant.output_mask |= 1 << val;
	}

	of_address_to_resource(np, 0, &res);
	if (!request_mem_region(res.start,
				resource_size(&res), "samsung-pwm")) {
		pr_err("%s: failed to request IO mem region\n", __func__);
		return;
	}

	pwm.base = ioremap(res.start, resource_size(&res));
	if (!pwm.base) {
		pr_err("%s: failed to map PWM registers\n", __func__);
		release_mem_region(res.start, resource_size(&res));
		return;
	}

	_samsung_pwm_clocksource_init();
}

static const struct samsung_pwm_variant s3c24xx_variant = {
	.bits		= 16,
	.div_base	= 1,
	.has_tint_cstat	= false,
	.tclk_mask	= (1 << 4),
};

static void __init s3c2410_pwm_clocksource_init(struct device_node *np)
{
	samsung_pwm_alloc(np, &s3c24xx_variant);
}
CLOCKSOURCE_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init);

static const struct samsung_pwm_variant s3c64xx_variant = {
	.bits		= 32,
	.div_base	= 0,
	.has_tint_cstat	= true,
	.tclk_mask	= (1 << 7) | (1 << 6) | (1 << 5),
};

static void __init s3c64xx_pwm_clocksource_init(struct device_node *np)
{
	samsung_pwm_alloc(np, &s3c64xx_variant);
}
CLOCKSOURCE_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init);

static const struct samsung_pwm_variant s5p64x0_variant = {
	.bits		= 32,
	.div_base	= 0,
	.has_tint_cstat	= true,
	.tclk_mask	= 0,
};

static void __init s5p64x0_pwm_clocksource_init(struct device_node *np)
{
	samsung_pwm_alloc(np, &s5p64x0_variant);
}
CLOCKSOURCE_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init);

static const struct samsung_pwm_variant s5p_variant = {
	.bits		= 32,
	.div_base	= 0,
	.has_tint_cstat	= true,
	.tclk_mask	= (1 << 5),
};

static void __init s5p_pwm_clocksource_init(struct device_node *np)
{
	samsung_pwm_alloc(np, &s5p_variant);
}
CLOCKSOURCE_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init);
#endif
Commit	Line	Data
f1189989 TF	1	/*
	2	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com/
	4	*
	5	* samsung - Common hr-timer support (s3c and s5p)
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/interrupt.h>
	13	#include <linux/irq.h>
	14	#include <linux/err.h>
	15	#include <linux/clk.h>
	16	#include <linux/clockchips.h>
	17	#include <linux/list.h>
	18	#include <linux/module.h>
	19	#include <linux/of.h>
	20	#include <linux/of_address.h>
	21	#include <linux/of_irq.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/slab.h>
	24
	25	#include <clocksource/samsung_pwm.h>
	26
	27	#include <asm/sched_clock.h>
	28
	29	/*
	30	* Clocksource driver
	31	*/
	32
	33	#define REG_TCFG0 0x00
	34	#define REG_TCFG1 0x04
	35	#define REG_TCON 0x08
	36	#define REG_TINT_CSTAT 0x44
	37
	38	#define REG_TCNTB(chan) (0x0c + 12 * (chan))
	39	#define REG_TCMPB(chan) (0x10 + 12 * (chan))
	40
	41	#define TCFG0_PRESCALER_MASK 0xff
	42	#define TCFG0_PRESCALER1_SHIFT 8
	43
	44	#define TCFG1_SHIFT(x) ((x) * 4)
	45	#define TCFG1_MUX_MASK 0xf
	46
	47	#define TCON_START(chan) (1 << (4 * (chan) + 0))
	48	#define TCON_MANUALUPDATE(chan) (1 << (4 * (chan) + 1))
	49	#define TCON_INVERT(chan) (1 << (4 * (chan) + 2))
	50	#define TCON_AUTORELOAD(chan) (1 << (4 * (chan) + 3))
	51
7aac482e TF	52	DEFINE_SPINLOCK(samsung_pwm_lock);
	53	EXPORT_SYMBOL(samsung_pwm_lock);
	54
030c2a1e TF	55	struct samsung_pwm_clocksource {
	56	void __iomem *base;
	57	unsigned int irq[SAMSUNG_PWM_NUM];
	58	struct samsung_pwm_variant variant;
	59
	60	struct clk *timerclk;
	61
f1189989 TF	62	unsigned int event_id;
	63	unsigned int source_id;
	64	unsigned int tcnt_max;
	65	unsigned int tscaler_div;
	66	unsigned int tdiv;
030c2a1e TF	67
030c2a1e TF	68	unsigned long clock_count_per_tick;
f1189989 TF	69	};
f1189989 TF	70
030c2a1e	71	static struct samsung_pwm_clocksource pwm;
f1189989	72
030c2a1e	73	static void samsung_timer_set_prescale(unsigned int channel, u16 prescale)
f1189989 TF	74	{
	75	unsigned long flags;
	76	u8 shift = 0;
	77	u32 reg;
	78
	79	if (channel >= 2)
	80	shift = TCFG0_PRESCALER1_SHIFT;
	81
7aac482e	82	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	83
030c2a1e	84	reg = readl(pwm.base + REG_TCFG0);
f1189989 TF	85	reg &= ~(TCFG0_PRESCALER_MASK << shift);
f1189989 TF	86	reg \|= (prescale - 1) << shift;
030c2a1e	87	writel(reg, pwm.base + REG_TCFG0);
f1189989	88
7aac482e	89	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	90	}
f1189989 TF	91
030c2a1e	92	static void samsung_timer_set_divisor(unsigned int channel, u8 divisor)
f1189989 TF	93	{
	94	u8 shift = TCFG1_SHIFT(channel);
	95	unsigned long flags;
	96	u32 reg;
	97	u8 bits;
	98
030c2a1e	99	bits = (fls(divisor) - 1) - pwm.variant.div_base;
f1189989	100
7aac482e	101	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	102
030c2a1e	103	reg = readl(pwm.base + REG_TCFG1);
f1189989 TF	104	reg &= ~(TCFG1_MUX_MASK << shift);
f1189989 TF	105	reg \|= bits << shift;
030c2a1e	106	writel(reg, pwm.base + REG_TCFG1);
f1189989	107
7aac482e	108	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	109	}
	110
	111	static void samsung_time_stop(unsigned int channel)
	112	{
	113	unsigned long tcon;
	114	unsigned long flags;
	115
	116	if (channel > 0)
	117	++channel;
	118
7aac482e	119	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	120
030c2a1e	121	tcon = __raw_readl(pwm.base + REG_TCON);
f1189989	122	tcon &= ~TCON_START(channel);
030c2a1e	123	__raw_writel(tcon, pwm.base + REG_TCON);
f1189989	124
7aac482e	125	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	126	}
	127
	128	static void samsung_time_setup(unsigned int channel, unsigned long tcnt)
	129	{
	130	unsigned long tcon;
	131	unsigned long flags;
	132	unsigned int tcon_chan = channel;
	133
	134	if (tcon_chan > 0)
	135	++tcon_chan;
	136
7aac482e	137	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	138
030c2a1e	139	tcon = __raw_readl(pwm.base + REG_TCON);
f1189989	140
f1189989 TF	141	tcon &= ~(TCON_START(tcon_chan) \| TCON_AUTORELOAD(tcon_chan));
	142	tcon \|= TCON_MANUALUPDATE(tcon_chan);
	143
030c2a1e TF	144	__raw_writel(tcnt, pwm.base + REG_TCNTB(channel));
	145	__raw_writel(tcnt, pwm.base + REG_TCMPB(channel));
	146	__raw_writel(tcon, pwm.base + REG_TCON);
f1189989	147
7aac482e	148	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	149	}
	150
	151	static void samsung_time_start(unsigned int channel, bool periodic)
	152	{
	153	unsigned long tcon;
	154	unsigned long flags;
	155
	156	if (channel > 0)
	157	++channel;
	158
7aac482e	159	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	160
030c2a1e	161	tcon = __raw_readl(pwm.base + REG_TCON);
f1189989 TF	162
	163	tcon &= ~TCON_MANUALUPDATE(channel);
	164	tcon \|= TCON_START(channel);
	165
	166	if (periodic)
	167	tcon \|= TCON_AUTORELOAD(channel);
	168	else
	169	tcon &= ~TCON_AUTORELOAD(channel);
	170
030c2a1e	171	__raw_writel(tcon, pwm.base + REG_TCON);
f1189989	172
7aac482e	173	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	174	}
	175
	176	static int samsung_set_next_event(unsigned long cycles,
	177	struct clock_event_device *evt)
	178	{
81d4f7bf TF	179	/*
	180	* This check is needed to account for internal rounding
	181	* errors inside clockevents core, which might result in
	182	* passing cycles = 0, which in turn would not generate any
	183	* timer interrupt and hang the system.
	184	*
	185	* Another solution would be to set up the clockevent device
	186	* with min_delta = 2, but this would unnecessarily increase
	187	* the minimum sleep period.
	188	*/
	189	if (!cycles)
	190	cycles = 1;
	191
030c2a1e TF	192	samsung_time_setup(pwm.event_id, cycles);
030c2a1e TF	193	samsung_time_start(pwm.event_id, false);
f1189989 TF	194
	195	return 0;
	196	}
	197
	198	static void samsung_timer_resume(void)
	199	{
	200	/* event timer restart */
6fe4dfd0	201	samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1);
030c2a1e	202	samsung_time_start(pwm.event_id, true);
f1189989 TF	203
f1189989 TF	204	/* source timer restart */
030c2a1e TF	205	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
030c2a1e TF	206	samsung_time_start(pwm.source_id, true);
f1189989 TF	207	}
	208
	209	static void samsung_set_mode(enum clock_event_mode mode,
	210	struct clock_event_device *evt)
	211	{
030c2a1e	212	samsung_time_stop(pwm.event_id);
f1189989 TF	213
	214	switch (mode) {
	215	case CLOCK_EVT_MODE_PERIODIC:
6fe4dfd0	216	samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1);
030c2a1e	217	samsung_time_start(pwm.event_id, true);
f1189989 TF	218	break;
	219
	220	case CLOCK_EVT_MODE_ONESHOT:
	221	break;
	222
	223	case CLOCK_EVT_MODE_UNUSED:
	224	case CLOCK_EVT_MODE_SHUTDOWN:
	225	break;
	226
	227	case CLOCK_EVT_MODE_RESUME:
	228	samsung_timer_resume();
	229	break;
	230	}
	231	}
	232
	233	static struct clock_event_device time_event_device = {
	234	.name = "samsung_event_timer",
	235	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	236	.rating = 200,
	237	.set_next_event = samsung_set_next_event,
	238	.set_mode = samsung_set_mode,
	239	};
	240
	241	static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
	242	{
	243	struct clock_event_device *evt = dev_id;
	244
030c2a1e TF	245	if (pwm.variant.has_tint_cstat) {
	246	u32 mask = (1 << pwm.event_id);
	247	writel(mask \| (mask << 5), pwm.base + REG_TINT_CSTAT);
f1189989 TF	248	}
	249
	250	evt->event_handler(evt);
	251
	252	return IRQ_HANDLED;
	253	}
	254
	255	static struct irqaction samsung_clock_event_irq = {
	256	.name = "samsung_time_irq",
	257	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
	258	.handler = samsung_clock_event_isr,
	259	.dev_id = &time_event_device,
	260	};
	261
	262	static void __init samsung_clockevent_init(void)
	263	{
	264	unsigned long pclk;
	265	unsigned long clock_rate;
	266	unsigned int irq_number;
	267
030c2a1e	268	pclk = clk_get_rate(pwm.timerclk);
f1189989	269
030c2a1e TF	270	samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
030c2a1e TF	271	samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);
f1189989	272
030c2a1e TF	273	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
030c2a1e TF	274	pwm.clock_count_per_tick = clock_rate / HZ;
f1189989 TF	275
f1189989 TF	276	time_event_device.cpumask = cpumask_of(0);
e9b852b8 TF	277	clockevents_config_and_register(&time_event_device,
e9b852b8 TF	278	clock_rate, 1, pwm.tcnt_max);
f1189989	279
030c2a1e	280	irq_number = pwm.irq[pwm.event_id];
f1189989 TF	281	setup_irq(irq_number, &samsung_clock_event_irq);
f1189989 TF	282
030c2a1e TF	283	if (pwm.variant.has_tint_cstat) {
	284	u32 mask = (1 << pwm.event_id);
	285	writel(mask \| (mask << 5), pwm.base + REG_TINT_CSTAT);
f1189989 TF	286	}
	287	}
	288
	289	static void __iomem *samsung_timer_reg(void)
	290	{
030c2a1e	291	switch (pwm.source_id) {
f1189989 TF	292	case 0:
	293	case 1:
	294	case 2:
	295	case 3:
030c2a1e	296	return pwm.base + pwm.source_id * 0x0c + 0x14;
f1189989 TF	297
f1189989 TF	298	case 4:
030c2a1e	299	return pwm.base + 0x40;
f1189989 TF	300
	301	default:
	302	BUG();
	303	}
	304	}
	305
	306	/*
	307	* Override the global weak sched_clock symbol with this
	308	* local implementation which uses the clocksource to get some
	309	* better resolution when scheduling the kernel. We accept that
	310	* this wraps around for now, since it is just a relative time
	311	* stamp. (Inspired by U300 implementation.)
	312	*/
	313	static u32 notrace samsung_read_sched_clock(void)
	314	{
	315	void __iomem *reg = samsung_timer_reg();
	316
	317	if (!reg)
	318	return 0;
	319
	320	return ~__raw_readl(reg);
	321	}
	322
	323	static void __init samsung_clocksource_init(void)
	324	{
	325	void __iomem *reg = samsung_timer_reg();
	326	unsigned long pclk;
	327	unsigned long clock_rate;
	328	int ret;
	329
030c2a1e	330	pclk = clk_get_rate(pwm.timerclk);
f1189989	331
030c2a1e TF	332	samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
030c2a1e TF	333	samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);
f1189989	334
030c2a1e	335	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
f1189989	336
030c2a1e TF	337	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
030c2a1e TF	338	samsung_time_start(pwm.source_id, true);
f1189989 TF	339
f1189989 TF	340	setup_sched_clock(samsung_read_sched_clock,
030c2a1e	341	pwm.variant.bits, clock_rate);
f1189989 TF	342
f1189989 TF	343	ret = clocksource_mmio_init(reg, "samsung_clocksource_timer",
030c2a1e	344	clock_rate, 250, pwm.variant.bits,
f1189989 TF	345	clocksource_mmio_readl_down);
	346	if (ret)
	347	panic("samsung_clocksource_timer: can't register clocksource\n");
	348	}
	349
	350	static void __init samsung_timer_resources(void)
	351	{
030c2a1e TF	352	pwm.timerclk = clk_get(NULL, "timers");
030c2a1e TF	353	if (IS_ERR(pwm.timerclk))
f1189989 TF	354	panic("failed to get timers clock for timer");
f1189989 TF	355
030c2a1e	356	clk_prepare_enable(pwm.timerclk);
f1189989	357
030c2a1e TF	358	pwm.tcnt_max = (1UL << pwm.variant.bits) - 1;
	359	if (pwm.variant.bits == 16) {
	360	pwm.tscaler_div = 25;
	361	pwm.tdiv = 2;
f1189989	362	} else {
030c2a1e TF	363	pwm.tscaler_div = 2;
030c2a1e TF	364	pwm.tdiv = 1;
f1189989 TF	365	}
	366	}
	367
	368	/*
	369	* PWM master driver
	370	*/
f9bb48a2	371	static void __init _samsung_pwm_clocksource_init(void)
f1189989 TF	372	{
	373	u8 mask;
	374	int channel;
	375
030c2a1e	376	mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1);
f1189989 TF	377	channel = fls(mask) - 1;
	378	if (channel < 0)
	379	panic("failed to find PWM channel for clocksource");
030c2a1e	380	pwm.source_id = channel;
f1189989 TF	381
	382	mask &= ~(1 << channel);
	383	channel = fls(mask) - 1;
	384	if (channel < 0)
	385	panic("failed to find PWM channel for clock event");
030c2a1e	386	pwm.event_id = channel;
f1189989 TF	387
	388	samsung_timer_resources();
	389	samsung_clockevent_init();
	390	samsung_clocksource_init();
	391	}
	392
f9bb48a2 TF	393	void __init samsung_pwm_clocksource_init(void __iomem *base,
	394	unsigned int irqs, struct samsung_pwm_variant variant)
	395	{
	396	pwm.base = base;
	397	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
	398	memcpy(pwm.irq, irqs, SAMSUNG_PWM_NUM * sizeof(*irqs));
	399
	400	_samsung_pwm_clocksource_init();
	401	}
	402
	403	#ifdef CONFIG_CLKSRC_OF
f1189989 TF	404	static void __init samsung_pwm_alloc(struct device_node *np,
	405	const struct samsung_pwm_variant *variant)
	406	{
	407	struct resource res;
	408	struct property *prop;
	409	const __be32 *cur;
	410	u32 val;
	411	int i;
	412
030c2a1e	413	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
f1189989	414	for (i = 0; i < SAMSUNG_PWM_NUM; ++i)
030c2a1e	415	pwm.irq[i] = irq_of_parse_and_map(np, i);
f1189989 TF	416
	417	of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
	418	if (val >= SAMSUNG_PWM_NUM) {
	419	pr_warning("%s: invalid channel index in samsung,pwm-outputs property\n",
	420	__func__);
	421	continue;
	422	}
030c2a1e	423	pwm.variant.output_mask \|= 1 << val;
f1189989 TF	424	}
	425
	426	of_address_to_resource(np, 0, &res);
	427	if (!request_mem_region(res.start,
	428	resource_size(&res), "samsung-pwm")) {
	429	pr_err("%s: failed to request IO mem region\n", __func__);
	430	return;
	431	}
	432
030c2a1e TF	433	pwm.base = ioremap(res.start, resource_size(&res));
030c2a1e TF	434	if (!pwm.base) {
f1189989 TF	435	pr_err("%s: failed to map PWM registers\n", __func__);
	436	release_mem_region(res.start, resource_size(&res));
	437	return;
	438	}
	439
f9bb48a2	440	_samsung_pwm_clocksource_init();
f1189989 TF	441	}
	442
	443	static const struct samsung_pwm_variant s3c24xx_variant = {
	444	.bits = 16,
	445	.div_base = 1,
	446	.has_tint_cstat = false,
	447	.tclk_mask = (1 << 4),
	448	};
	449
	450	static void __init s3c2410_pwm_clocksource_init(struct device_node *np)
	451	{
	452	samsung_pwm_alloc(np, &s3c24xx_variant);
	453	}
	454	CLOCKSOURCE_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init);
	455
	456	static const struct samsung_pwm_variant s3c64xx_variant = {
	457	.bits = 32,
	458	.div_base = 0,
	459	.has_tint_cstat = true,
	460	.tclk_mask = (1 << 7) \| (1 << 6) \| (1 << 5),
	461	};
	462
	463	static void __init s3c64xx_pwm_clocksource_init(struct device_node *np)
	464	{
	465	samsung_pwm_alloc(np, &s3c64xx_variant);
	466	}
	467	CLOCKSOURCE_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init);
	468
	469	static const struct samsung_pwm_variant s5p64x0_variant = {
	470	.bits = 32,
	471	.div_base = 0,
	472	.has_tint_cstat = true,
	473	.tclk_mask = 0,
	474	};
	475
	476	static void __init s5p64x0_pwm_clocksource_init(struct device_node *np)
	477	{
	478	samsung_pwm_alloc(np, &s5p64x0_variant);
	479	}
	480	CLOCKSOURCE_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init);
	481
	482	static const struct samsung_pwm_variant s5p_variant = {
	483	.bits = 32,
	484	.div_base = 0,
	485	.has_tint_cstat = true,
	486	.tclk_mask = (1 << 5),
	487	};
	488
	489	static void __init s5p_pwm_clocksource_init(struct device_node *np)
	490	{
	491	samsung_pwm_alloc(np, &s5p_variant);
	492	}
	493	CLOCKSOURCE_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init);
f9bb48a2	494	#endif