[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / char / tpm / tpm_tis.c

/*
 * Copyright (C) 2005, 2006 IBM Corporation
 *
 * Authors:
 * Leendert van Doorn <leendert@watson.ibm.com>
 * Kylene Hall <kjhall@us.ibm.com>
 *
 * Device driver for TCG/TCPA TPM (trusted platform module).
 * Specifications at www.trustedcomputinggroup.org
 *
 * This device driver implements the TPM interface as defined in
 * the TCG TPM Interface Spec version 1.2, revision 1.0.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation, version 2 of the
 * License.
 */
#include <linux/pnp.h>
#include <linux/interrupt.h>
#include <linux/wait.h>
#include "tpm.h"

#define TPM_HEADER_SIZE 10

enum tis_access {
	TPM_ACCESS_VALID = 0x80,
	TPM_ACCESS_ACTIVE_LOCALITY = 0x20,
	TPM_ACCESS_REQUEST_PENDING = 0x04,
	TPM_ACCESS_REQUEST_USE = 0x02,
};

enum tis_status {
	TPM_STS_VALID = 0x80,
	TPM_STS_COMMAND_READY = 0x40,
	TPM_STS_GO = 0x20,
	TPM_STS_DATA_AVAIL = 0x10,
	TPM_STS_DATA_EXPECT = 0x08,
};

enum tis_int_flags {
	TPM_GLOBAL_INT_ENABLE = 0x80000000,
	TPM_INTF_BURST_COUNT_STATIC = 0x100,
	TPM_INTF_CMD_READY_INT = 0x080,
	TPM_INTF_INT_EDGE_FALLING = 0x040,
	TPM_INTF_INT_EDGE_RISING = 0x020,
	TPM_INTF_INT_LEVEL_LOW = 0x010,
	TPM_INTF_INT_LEVEL_HIGH = 0x008,
	TPM_INTF_LOCALITY_CHANGE_INT = 0x004,
	TPM_INTF_STS_VALID_INT = 0x002,
	TPM_INTF_DATA_AVAIL_INT = 0x001,
};

enum tis_defaults {
	TIS_MEM_BASE = 0xFED4000,
	TIS_MEM_LEN = 0x5000,
	TIS_SHORT_TIMEOUT = 750,	/* ms */
	TIS_LONG_TIMEOUT = 2000,	/* 2 sec */
};

#define	TPM_ACCESS(l)			(0x0000 | ((l) << 12))
#define	TPM_INT_ENABLE(l)		(0x0008 | ((l) << 12))
#define	TPM_INT_VECTOR(l)		(0x000C | ((l) << 12))
#define	TPM_INT_STATUS(l)		(0x0010 | ((l) << 12))
#define	TPM_INTF_CAPS(l)		(0x0014 | ((l) << 12))
#define	TPM_STS(l)			(0x0018 | ((l) << 12))
#define	TPM_DATA_FIFO(l)		(0x0024 | ((l) << 12))

#define	TPM_DID_VID(l)			(0x0F00 | ((l) << 12))
#define	TPM_RID(l)			(0x0F04 | ((l) << 12))

static LIST_HEAD(tis_chips);
static DEFINE_SPINLOCK(tis_lock);

static int check_locality(struct tpm_chip *chip, int l)
{
	if ((ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
	     (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) ==
	    (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID))
		return chip->vendor.locality = l;

	return -1;
}

static void release_locality(struct tpm_chip *chip, int l, int force)
{
	if (force || (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
		      (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID)) ==
	    (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID))
		iowrite8(TPM_ACCESS_ACTIVE_LOCALITY,
			 chip->vendor.iobase + TPM_ACCESS(l));
}

static int request_locality(struct tpm_chip *chip, int l)
{
	unsigned long stop;
	long rc;

	if (check_locality(chip, l) >= 0)
		return l;

	iowrite8(TPM_ACCESS_REQUEST_USE,
		 chip->vendor.iobase + TPM_ACCESS(l));

	if (chip->vendor.irq) {
		rc = wait_event_interruptible_timeout(chip->vendor.int_queue,
						      (check_locality
						       (chip, l) >= 0),
						      chip->vendor.timeout_a);
		if (rc > 0)
			return l;

	} else {
		/* wait for burstcount */
		stop = jiffies + chip->vendor.timeout_a;
		do {
			if (check_locality(chip, l) >= 0)
				return l;
			msleep(TPM_TIMEOUT);
		}
		while (time_before(jiffies, stop));
	}
	return -1;
}

static u8 tpm_tis_status(struct tpm_chip *chip)
{
	return ioread8(chip->vendor.iobase +
		       TPM_STS(chip->vendor.locality));
}

static void tpm_tis_ready(struct tpm_chip *chip)
{
	/* this causes the current command to be aborted */
	iowrite8(TPM_STS_COMMAND_READY,
		 chip->vendor.iobase + TPM_STS(chip->vendor.locality));
}

static int get_burstcount(struct tpm_chip *chip)
{
	unsigned long stop;
	int burstcnt;

	/* wait for burstcount */
	/* which timeout value, spec has 2 answers (c & d) */
	stop = jiffies + chip->vendor.timeout_d;
	do {
		burstcnt = ioread8(chip->vendor.iobase +
				   TPM_STS(chip->vendor.locality) + 1);
		burstcnt += ioread8(chip->vendor.iobase +
				    TPM_STS(chip->vendor.locality) +
				    2) << 8;
		if (burstcnt)
			return burstcnt;
		msleep(TPM_TIMEOUT);
	} while (time_before(jiffies, stop));
	return -EBUSY;
}

static int wait_for_stat(struct tpm_chip *chip, u8 mask, unsigned long timeout,
			 wait_queue_head_t *queue)
{
	unsigned long stop;
	long rc;
	u8 status;

	/* check current status */
	status = tpm_tis_status(chip);
	if ((status & mask) == mask)
		return 0;

	if (chip->vendor.irq) {
		rc = wait_event_interruptible_timeout(*queue,
						      ((tpm_tis_status
							(chip) & mask) ==
						       mask), timeout);
		if (rc > 0)
			return 0;
	} else {
		stop = jiffies + timeout;
		do {
			msleep(TPM_TIMEOUT);
			status = tpm_tis_status(chip);
			if ((status & mask) == mask)
				return 0;
		} while (time_before(jiffies, stop));
	}
	return -ETIME;
}

static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count)
{
	int size = 0, burstcnt;
	while (size < count &&
	       wait_for_stat(chip,
			     TPM_STS_DATA_AVAIL | TPM_STS_VALID,
			     chip->vendor.timeout_c,
			     &chip->vendor.read_queue)
	       == 0) {
		burstcnt = get_burstcount(chip);
		for (; burstcnt > 0 && size < count; burstcnt--)
			buf[size++] = ioread8(chip->vendor.iobase +
					      TPM_DATA_FIFO(chip->vendor.
							    locality));
	}
	return size;
}

static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count)
{
	int size = 0;
	int expected, status;

	if (count < TPM_HEADER_SIZE) {
		size = -EIO;
		goto out;
	}

	/* read first 10 bytes, including tag, paramsize, and result */
	if ((size =
	     recv_data(chip, buf, TPM_HEADER_SIZE)) < TPM_HEADER_SIZE) {
		dev_err(chip->dev, "Unable to read header\n");
		goto out;
	}

	expected = be32_to_cpu(*(__be32 *) (buf + 2));
	if (expected > count) {
		size = -EIO;
		goto out;
	}

	if ((size +=
	     recv_data(chip, &buf[TPM_HEADER_SIZE],
		       expected - TPM_HEADER_SIZE)) < expected) {
		dev_err(chip->dev, "Unable to read remainder of result\n");
		size = -ETIME;
		goto out;
	}

	wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
		      &chip->vendor.int_queue);
	status = tpm_tis_status(chip);
	if (status & TPM_STS_DATA_AVAIL) {	/* retry? */
		dev_err(chip->dev, "Error left over data\n");
		size = -EIO;
		goto out;
	}

out:
	tpm_tis_ready(chip);
	release_locality(chip, chip->vendor.locality, 0);
	return size;
}

/*
 * If interrupts are used (signaled by an irq set in the vendor structure)
 * tpm.c can skip polling for the data to be available as the interrupt is
 * waited for here
 */
static int tpm_tis_send(struct tpm_chip *chip, u8 *buf, size_t len)
{
	int rc, status, burstcnt;
	size_t count = 0;
	u32 ordinal;

	if (request_locality(chip, 0) < 0)
		return -EBUSY;

	status = tpm_tis_status(chip);
	if ((status & TPM_STS_COMMAND_READY) == 0) {
		tpm_tis_ready(chip);
		if (wait_for_stat
		    (chip, TPM_STS_COMMAND_READY, chip->vendor.timeout_b,
		     &chip->vendor.int_queue) < 0) {
			rc = -ETIME;
			goto out_err;
		}
	}

	while (count < len - 1) {
		burstcnt = get_burstcount(chip);
		for (; burstcnt > 0 && count < len - 1; burstcnt--) {
			iowrite8(buf[count], chip->vendor.iobase +
				 TPM_DATA_FIFO(chip->vendor.locality));
			count++;
		}

		wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
			      &chip->vendor.int_queue);
		status = tpm_tis_status(chip);
		if ((status & TPM_STS_DATA_EXPECT) == 0) {
			rc = -EIO;
			goto out_err;
		}
	}

	/* write last byte */
	iowrite8(buf[count],
		 chip->vendor.iobase +
		 TPM_DATA_FIFO(chip->vendor.locality));
	wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
		      &chip->vendor.int_queue);
	status = tpm_tis_status(chip);
	if ((status & TPM_STS_DATA_EXPECT) != 0) {
		rc = -EIO;
		goto out_err;
	}

	/* go and do it */
	iowrite8(TPM_STS_GO,
		 chip->vendor.iobase + TPM_STS(chip->vendor.locality));

	if (chip->vendor.irq) {
		ordinal = be32_to_cpu(*((__be32 *) (buf + 6)));
		if (wait_for_stat
		    (chip, TPM_STS_DATA_AVAIL | TPM_STS_VALID,
		     tpm_calc_ordinal_duration(chip, ordinal),
		     &chip->vendor.read_queue) < 0) {
			rc = -ETIME;
			goto out_err;
		}
	}
	return len;
out_err:
	tpm_tis_ready(chip);
	release_locality(chip, chip->vendor.locality, 0);
	return rc;
}

static struct file_operations tis_ops = {
	.owner = THIS_MODULE,
	.llseek = no_llseek,
	.open = tpm_open,
	.read = tpm_read,
	.write = tpm_write,
	.release = tpm_release,
};

static DEVICE_ATTR(pubek, S_IRUGO, tpm_show_pubek, NULL);
static DEVICE_ATTR(pcrs, S_IRUGO, tpm_show_pcrs, NULL);
static DEVICE_ATTR(enabled, S_IRUGO, tpm_show_enabled, NULL);
static DEVICE_ATTR(active, S_IRUGO, tpm_show_active, NULL);
static DEVICE_ATTR(owned, S_IRUGO, tpm_show_owned, NULL);
static DEVICE_ATTR(temp_deactivated, S_IRUGO, tpm_show_temp_deactivated,
		   NULL);
static DEVICE_ATTR(caps, S_IRUGO, tpm_show_caps_1_2, NULL);
static DEVICE_ATTR(cancel, S_IWUSR | S_IWGRP, NULL, tpm_store_cancel);

static struct attribute *tis_attrs[] = {
	&dev_attr_pubek.attr,
	&dev_attr_pcrs.attr,
	&dev_attr_enabled.attr,
	&dev_attr_active.attr,
	&dev_attr_owned.attr,
	&dev_attr_temp_deactivated.attr,
	&dev_attr_caps.attr,
	&dev_attr_cancel.attr, NULL,
};

static struct attribute_group tis_attr_grp = {
	.attrs = tis_attrs
};

static struct tpm_vendor_specific tpm_tis = {
	.status = tpm_tis_status,
	.recv = tpm_tis_recv,
	.send = tpm_tis_send,
	.cancel = tpm_tis_ready,
	.req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
	.req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
	.req_canceled = TPM_STS_COMMAND_READY,
	.attr_group = &tis_attr_grp,
	.miscdev = {
		    .fops = &tis_ops,},
};

static irqreturn_t tis_int_probe(int irq, void *dev_id, struct pt_regs *regs)
{
	struct tpm_chip *chip = (struct tpm_chip *) dev_id;
	u32 interrupt;

	interrupt = ioread32(chip->vendor.iobase +
			     TPM_INT_STATUS(chip->vendor.locality));

	if (interrupt == 0)
		return IRQ_NONE;

	chip->vendor.irq = irq;

	/* Clear interrupts handled with TPM_EOI */
	iowrite32(interrupt,
		  chip->vendor.iobase +
		  TPM_INT_STATUS(chip->vendor.locality));
	return IRQ_HANDLED;
}

static irqreturn_t tis_int_handler(int irq, void *dev_id, struct pt_regs *regs)
{
	struct tpm_chip *chip = (struct tpm_chip *) dev_id;
	u32 interrupt;
	int i;

	interrupt = ioread32(chip->vendor.iobase +
			     TPM_INT_STATUS(chip->vendor.locality));

	if (interrupt == 0)
		return IRQ_NONE;

	if (interrupt & TPM_INTF_DATA_AVAIL_INT)
		wake_up_interruptible(&chip->vendor.read_queue);
	if (interrupt & TPM_INTF_LOCALITY_CHANGE_INT)
		for (i = 0; i < 5; i++)
			if (check_locality(chip, i) >= 0)
				break;
	if (interrupt &
	    (TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_STS_VALID_INT |
	     TPM_INTF_CMD_READY_INT))
		wake_up_interruptible(&chip->vendor.int_queue);

	/* Clear interrupts handled with TPM_EOI */
	iowrite32(interrupt,
		  chip->vendor.iobase +
		  TPM_INT_STATUS(chip->vendor.locality));
	return IRQ_HANDLED;
}

static int __devinit tpm_tis_pnp_init(struct pnp_dev *pnp_dev,
				      const struct pnp_device_id *pnp_id)
{
	u32 vendor, intfcaps, intmask;
	int rc, i;
	unsigned long start, len;
	struct tpm_chip *chip;

	start = pnp_mem_start(pnp_dev, 0);
	len = pnp_mem_len(pnp_dev, 0);

	if (!start)
		start = TIS_MEM_BASE;
	if (!len)
		len = TIS_MEM_LEN;

	if (!(chip = tpm_register_hardware(&pnp_dev->dev, &tpm_tis)))
		return -ENODEV;

	chip->vendor.iobase = ioremap(start, len);
	if (!chip->vendor.iobase) {
		rc = -EIO;
		goto out_err;
	}

	vendor = ioread32(chip->vendor.iobase + TPM_DID_VID(0));
	if ((vendor & 0xFFFF) == 0xFFFF) {
		rc = -ENODEV;
		goto out_err;
	}

	/* Default timeouts */
	chip->vendor.timeout_a = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
	chip->vendor.timeout_b = msecs_to_jiffies(TIS_LONG_TIMEOUT);
	chip->vendor.timeout_c = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
	chip->vendor.timeout_d = msecs_to_jiffies(TIS_SHORT_TIMEOUT);

	dev_info(&pnp_dev->dev,
		 "1.2 TPM (device-id 0x%X, rev-id %d)\n",
		 vendor >> 16, ioread8(chip->vendor.iobase + TPM_RID(0)));

	/* Figure out the capabilities */
	intfcaps =
	    ioread32(chip->vendor.iobase +
		     TPM_INTF_CAPS(chip->vendor.locality));
	dev_dbg(&pnp_dev->dev, "TPM interface capabilities (0x%x):\n",
		intfcaps);
	if (intfcaps & TPM_INTF_BURST_COUNT_STATIC)
		dev_dbg(&pnp_dev->dev, "\tBurst Count Static\n");
	if (intfcaps & TPM_INTF_CMD_READY_INT)
		dev_dbg(&pnp_dev->dev, "\tCommand Ready Int Support\n");
	if (intfcaps & TPM_INTF_INT_EDGE_FALLING)
		dev_dbg(&pnp_dev->dev, "\tInterrupt Edge Falling\n");
	if (intfcaps & TPM_INTF_INT_EDGE_RISING)
		dev_dbg(&pnp_dev->dev, "\tInterrupt Edge Rising\n");
	if (intfcaps & TPM_INTF_INT_LEVEL_LOW)
		dev_dbg(&pnp_dev->dev, "\tInterrupt Level Low\n");
	if (intfcaps & TPM_INTF_INT_LEVEL_HIGH)
		dev_dbg(&pnp_dev->dev, "\tInterrupt Level High\n");
	if (intfcaps & TPM_INTF_LOCALITY_CHANGE_INT)
		dev_dbg(&pnp_dev->dev, "\tLocality Change Int Support\n");
	if (intfcaps & TPM_INTF_STS_VALID_INT)
		dev_dbg(&pnp_dev->dev, "\tSts Valid Int Support\n");
	if (intfcaps & TPM_INTF_DATA_AVAIL_INT)
		dev_dbg(&pnp_dev->dev, "\tData Avail Int Support\n");

	if (request_locality(chip, 0) != 0) {
		rc = -ENODEV;
		goto out_err;
	}

	/* INTERRUPT Setup */
	init_waitqueue_head(&chip->vendor.read_queue);
	init_waitqueue_head(&chip->vendor.int_queue);

	intmask =
	    ioread32(chip->vendor.iobase +
		     TPM_INT_ENABLE(chip->vendor.locality));

	intmask |= TPM_INTF_CMD_READY_INT
	    | TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT
	    | TPM_INTF_STS_VALID_INT;

	iowrite32(intmask,
		  chip->vendor.iobase +
		  TPM_INT_ENABLE(chip->vendor.locality));

	chip->vendor.irq =
	    ioread8(chip->vendor.iobase +
		    TPM_INT_VECTOR(chip->vendor.locality));

	for (i = 3; i < 16 && chip->vendor.irq == 0; i++) {
		iowrite8(i,
			 chip->vendor.iobase +
			 TPM_INT_VECTOR(chip->vendor.locality));
		if (request_irq
		    (i, tis_int_probe, SA_SHIRQ,
		     chip->vendor.miscdev.name, chip) != 0) {
			dev_info(chip->dev,
				 "Unable to request irq: %d for probe\n",
				 i);
			continue;
		}

		/* Clear all existing */
		iowrite32(ioread32
			  (chip->vendor.iobase +
			   TPM_INT_STATUS(chip->vendor.locality)),
			  chip->vendor.iobase +
			  TPM_INT_STATUS(chip->vendor.locality));

		/* Turn on */
		iowrite32(intmask | TPM_GLOBAL_INT_ENABLE,
			  chip->vendor.iobase +
			  TPM_INT_ENABLE(chip->vendor.locality));

		/* Generate Interrupts */
		tpm_gen_interrupt(chip);

		/* Turn off */
		iowrite32(intmask,
			  chip->vendor.iobase +
			  TPM_INT_ENABLE(chip->vendor.locality));
		free_irq(i, chip);
	}
	if (chip->vendor.irq) {
		iowrite8(chip->vendor.irq,
			 chip->vendor.iobase +
			 TPM_INT_VECTOR(chip->vendor.locality));
		if (request_irq
		    (chip->vendor.irq, tis_int_handler, SA_SHIRQ,
		     chip->vendor.miscdev.name, chip) != 0) {
			dev_info(chip->dev,
				 "Unable to request irq: %d for use\n", i);
			chip->vendor.irq = 0;
		} else {
			/* Clear all existing */
			iowrite32(ioread32
				  (chip->vendor.iobase +
				   TPM_INT_STATUS(chip->vendor.locality)),
				  chip->vendor.iobase +
				  TPM_INT_STATUS(chip->vendor.locality));

			/* Turn on */
			iowrite32(intmask | TPM_GLOBAL_INT_ENABLE,
				  chip->vendor.iobase +
				  TPM_INT_ENABLE(chip->vendor.locality));
		}
	}

	INIT_LIST_HEAD(&chip->vendor.list);
	spin_lock(&tis_lock);
	list_add(&chip->vendor.list, &tis_chips);
	spin_unlock(&tis_lock);

	tpm_get_timeouts(chip);
	tpm_continue_selftest(chip);

	return 0;
out_err:
	if (chip->vendor.iobase)
		iounmap(chip->vendor.iobase);
	tpm_remove_hardware(chip->dev);
	return rc;
}

static int tpm_tis_pnp_suspend(struct pnp_dev *dev, pm_message_t msg)
{
	return tpm_pm_suspend(&dev->dev, msg);
}

static int tpm_tis_pnp_resume(struct pnp_dev *dev)
{
	return tpm_pm_resume(&dev->dev);
}

static struct pnp_device_id tpm_pnp_tbl[] __devinitdata = {
	{"PNP0C31", 0},		/* TPM */
	{"", 0}
};

static struct pnp_driver tis_pnp_driver = {
	.name = "tpm_tis",
	.id_table = tpm_pnp_tbl,
	.probe = tpm_tis_pnp_init,
	.suspend = tpm_tis_pnp_suspend,
	.resume = tpm_tis_pnp_resume,
};

static int __init init_tis(void)
{
	return pnp_register_driver(&tis_pnp_driver);
}

static void __exit cleanup_tis(void)
{
	struct tpm_vendor_specific *i, *j;
	struct tpm_chip *chip;
	spin_lock(&tis_lock);
	list_for_each_entry_safe(i, j, &tis_chips, list) {
		chip = to_tpm_chip(i);
		iowrite32(~TPM_GLOBAL_INT_ENABLE &
			  ioread32(chip->vendor.iobase +
				   TPM_INT_ENABLE(chip->vendor.
						  locality)),
			  chip->vendor.iobase +
			  TPM_INT_ENABLE(chip->vendor.locality));
		release_locality(chip, chip->vendor.locality, 1);
		if (chip->vendor.irq)
			free_irq(chip->vendor.irq, chip);
		iounmap(i->iobase);
		list_del(&i->list);
		tpm_remove_hardware(chip->dev);
	}
	spin_unlock(&tis_lock);
	pnp_unregister_driver(&tis_pnp_driver);
}

module_init(init_tis);
module_exit(cleanup_tis);
MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
MODULE_DESCRIPTION("TPM Driver");
MODULE_VERSION("2.0");
MODULE_LICENSE("GPL");
Commit	Line	Data
27084efe LD	1	/*
	2	* Copyright (C) 2005, 2006 IBM Corporation
	3	*
	4	* Authors:
	5	* Leendert van Doorn <leendert@watson.ibm.com>
	6	* Kylene Hall <kjhall@us.ibm.com>
	7	*
	8	* Device driver for TCG/TCPA TPM (trusted platform module).
	9	* Specifications at www.trustedcomputinggroup.org
	10	*
	11	* This device driver implements the TPM interface as defined in
	12	* the TCG TPM Interface Spec version 1.2, revision 1.0.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation, version 2 of the
	17	* License.
	18	*/
	19	#include <linux/pnp.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/wait.h>
	22	#include "tpm.h"
	23
	24	#define TPM_HEADER_SIZE 10
	25
	26	enum tis_access {
	27	TPM_ACCESS_VALID = 0x80,
	28	TPM_ACCESS_ACTIVE_LOCALITY = 0x20,
	29	TPM_ACCESS_REQUEST_PENDING = 0x04,
	30	TPM_ACCESS_REQUEST_USE = 0x02,
	31	};
	32
	33	enum tis_status {
	34	TPM_STS_VALID = 0x80,
	35	TPM_STS_COMMAND_READY = 0x40,
	36	TPM_STS_GO = 0x20,
	37	TPM_STS_DATA_AVAIL = 0x10,
	38	TPM_STS_DATA_EXPECT = 0x08,
	39	};
	40
	41	enum tis_int_flags {
	42	TPM_GLOBAL_INT_ENABLE = 0x80000000,
	43	TPM_INTF_BURST_COUNT_STATIC = 0x100,
	44	TPM_INTF_CMD_READY_INT = 0x080,
	45	TPM_INTF_INT_EDGE_FALLING = 0x040,
	46	TPM_INTF_INT_EDGE_RISING = 0x020,
	47	TPM_INTF_INT_LEVEL_LOW = 0x010,
	48	TPM_INTF_INT_LEVEL_HIGH = 0x008,
	49	TPM_INTF_LOCALITY_CHANGE_INT = 0x004,
	50	TPM_INTF_STS_VALID_INT = 0x002,
	51	TPM_INTF_DATA_AVAIL_INT = 0x001,
	52	};
	53
36b20020	54	enum tis_defaults {
b09d5300 KJH	55	TIS_MEM_BASE = 0xFED4000,
b09d5300 KJH	56	TIS_MEM_LEN = 0x5000,
cb535425 KJH	57	TIS_SHORT_TIMEOUT = 750, /* ms */
cb535425 KJH	58	TIS_LONG_TIMEOUT = 2000, /* 2 sec */
36b20020 KJH	59	};
36b20020 KJH	60
27084efe LD	61	#define TPM_ACCESS(l) (0x0000 \| ((l) << 12))
	62	#define TPM_INT_ENABLE(l) (0x0008 \| ((l) << 12))
	63	#define TPM_INT_VECTOR(l) (0x000C \| ((l) << 12))
	64	#define TPM_INT_STATUS(l) (0x0010 \| ((l) << 12))
	65	#define TPM_INTF_CAPS(l) (0x0014 \| ((l) << 12))
	66	#define TPM_STS(l) (0x0018 \| ((l) << 12))
	67	#define TPM_DATA_FIFO(l) (0x0024 \| ((l) << 12))
	68
	69	#define TPM_DID_VID(l) (0x0F00 \| ((l) << 12))
	70	#define TPM_RID(l) (0x0F04 \| ((l) << 12))
	71
	72	static LIST_HEAD(tis_chips);
	73	static DEFINE_SPINLOCK(tis_lock);
	74
	75	static int check_locality(struct tpm_chip *chip, int l)
	76	{
	77	if ((ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
	78	(TPM_ACCESS_ACTIVE_LOCALITY \| TPM_ACCESS_VALID)) ==
	79	(TPM_ACCESS_ACTIVE_LOCALITY \| TPM_ACCESS_VALID))
	80	return chip->vendor.locality = l;
	81
	82	return -1;
	83	}
	84
	85	static void release_locality(struct tpm_chip *chip, int l, int force)
	86	{
	87	if (force \|\| (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
	88	(TPM_ACCESS_REQUEST_PENDING \| TPM_ACCESS_VALID)) ==
	89	(TPM_ACCESS_REQUEST_PENDING \| TPM_ACCESS_VALID))
	90	iowrite8(TPM_ACCESS_ACTIVE_LOCALITY,
	91	chip->vendor.iobase + TPM_ACCESS(l));
	92	}
	93
	94	static int request_locality(struct tpm_chip *chip, int l)
	95	{
	96	unsigned long stop;
	97	long rc;
	98
	99	if (check_locality(chip, l) >= 0)
	100	return l;
	101
	102	iowrite8(TPM_ACCESS_REQUEST_USE,
	103	chip->vendor.iobase + TPM_ACCESS(l));
	104
	105	if (chip->vendor.irq) {
36b20020	106	rc = wait_event_interruptible_timeout(chip->vendor.int_queue,
27084efe LD	107	(check_locality
27084efe LD	108	(chip, l) >= 0),
36b20020	109	chip->vendor.timeout_a);
27084efe LD	110	if (rc > 0)
	111	return l;
	112
	113	} else {
	114	/* wait for burstcount */
36b20020	115	stop = jiffies + chip->vendor.timeout_a;
27084efe LD	116	do {
	117	if (check_locality(chip, l) >= 0)
	118	return l;
	119	msleep(TPM_TIMEOUT);
	120	}
	121	while (time_before(jiffies, stop));
	122	}
	123	return -1;
	124	}
	125
	126	static u8 tpm_tis_status(struct tpm_chip *chip)
	127	{
	128	return ioread8(chip->vendor.iobase +
	129	TPM_STS(chip->vendor.locality));
	130	}
	131
	132	static void tpm_tis_ready(struct tpm_chip *chip)
	133	{
	134	/* this causes the current command to be aborted */
	135	iowrite8(TPM_STS_COMMAND_READY,
	136	chip->vendor.iobase + TPM_STS(chip->vendor.locality));
	137	}
	138
	139	static int get_burstcount(struct tpm_chip *chip)
	140	{
	141	unsigned long stop;
	142	int burstcnt;
	143
	144	/* wait for burstcount */
	145	/* which timeout value, spec has 2 answers (c & d) */
36b20020	146	stop = jiffies + chip->vendor.timeout_d;
27084efe LD	147	do {
	148	burstcnt = ioread8(chip->vendor.iobase +
	149	TPM_STS(chip->vendor.locality) + 1);
	150	burstcnt += ioread8(chip->vendor.iobase +
	151	TPM_STS(chip->vendor.locality) +
	152	2) << 8;
	153	if (burstcnt)
	154	return burstcnt;
	155	msleep(TPM_TIMEOUT);
	156	} while (time_before(jiffies, stop));
	157	return -EBUSY;
	158	}
	159
36b20020	160	static int wait_for_stat(struct tpm_chip *chip, u8 mask, unsigned long timeout,
27084efe LD	161	wait_queue_head_t *queue)
	162	{
	163	unsigned long stop;
	164	long rc;
	165	u8 status;
	166
	167	/* check current status */
	168	status = tpm_tis_status(chip);
	169	if ((status & mask) == mask)
	170	return 0;
	171
	172	if (chip->vendor.irq) {
	173	rc = wait_event_interruptible_timeout(*queue,
	174	((tpm_tis_status
	175	(chip) & mask) ==
36b20020	176	mask), timeout);
27084efe LD	177	if (rc > 0)
	178	return 0;
	179	} else {
36b20020	180	stop = jiffies + timeout;
27084efe LD	181	do {
	182	msleep(TPM_TIMEOUT);
	183	status = tpm_tis_status(chip);
	184	if ((status & mask) == mask)
	185	return 0;
	186	} while (time_before(jiffies, stop));
	187	}
	188	return -ETIME;
	189	}
	190
cb535425	191	static int recv_data(struct tpm_chip chip, u8 buf, size_t count)
27084efe LD	192	{
	193	int size = 0, burstcnt;
	194	while (size < count &&
	195	wait_for_stat(chip,
	196	TPM_STS_DATA_AVAIL \| TPM_STS_VALID,
	197	chip->vendor.timeout_c,
	198	&chip->vendor.read_queue)
	199	== 0) {
	200	burstcnt = get_burstcount(chip);
	201	for (; burstcnt > 0 && size < count; burstcnt--)
	202	buf[size++] = ioread8(chip->vendor.iobase +
	203	TPM_DATA_FIFO(chip->vendor.
	204	locality));
	205	}
	206	return size;
	207	}
	208
cb535425	209	static int tpm_tis_recv(struct tpm_chip chip, u8 buf, size_t count)
27084efe LD	210	{
	211	int size = 0;
	212	int expected, status;
	213
	214	if (count < TPM_HEADER_SIZE) {
	215	size = -EIO;
	216	goto out;
	217	}
	218
	219	/* read first 10 bytes, including tag, paramsize, and result */
	220	if ((size =
	221	recv_data(chip, buf, TPM_HEADER_SIZE)) < TPM_HEADER_SIZE) {
	222	dev_err(chip->dev, "Unable to read header\n");
	223	goto out;
	224	}
	225
	226	expected = be32_to_cpu((__be32 ) (buf + 2));
	227	if (expected > count) {
	228	size = -EIO;
	229	goto out;
	230	}
	231
	232	if ((size +=
	233	recv_data(chip, &buf[TPM_HEADER_SIZE],
	234	expected - TPM_HEADER_SIZE)) < expected) {
	235	dev_err(chip->dev, "Unable to read remainder of result\n");
	236	size = -ETIME;
	237	goto out;
	238	}
	239
	240	wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
	241	&chip->vendor.int_queue);
	242	status = tpm_tis_status(chip);
	243	if (status & TPM_STS_DATA_AVAIL) { /* retry? */
	244	dev_err(chip->dev, "Error left over data\n");
	245	size = -EIO;
	246	goto out;
	247	}
	248
	249	out:
	250	tpm_tis_ready(chip);
	251	release_locality(chip, chip->vendor.locality, 0);
	252	return size;
	253	}
	254
	255	/*
	256	* If interrupts are used (signaled by an irq set in the vendor structure)
	257	* tpm.c can skip polling for the data to be available as the interrupt is
	258	* waited for here
	259	*/
cb535425	260	static int tpm_tis_send(struct tpm_chip chip, u8 buf, size_t len)
27084efe LD	261	{
	262	int rc, status, burstcnt;
	263	size_t count = 0;
	264	u32 ordinal;
	265
	266	if (request_locality(chip, 0) < 0)
	267	return -EBUSY;
	268
	269	status = tpm_tis_status(chip);
	270	if ((status & TPM_STS_COMMAND_READY) == 0) {
	271	tpm_tis_ready(chip);
	272	if (wait_for_stat
	273	(chip, TPM_STS_COMMAND_READY, chip->vendor.timeout_b,
	274	&chip->vendor.int_queue) < 0) {
	275	rc = -ETIME;
	276	goto out_err;
	277	}
	278	}
	279
	280	while (count < len - 1) {
	281	burstcnt = get_burstcount(chip);
	282	for (; burstcnt > 0 && count < len - 1; burstcnt--) {
	283	iowrite8(buf[count], chip->vendor.iobase +
	284	TPM_DATA_FIFO(chip->vendor.locality));
	285	count++;
	286	}
	287
	288	wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
	289	&chip->vendor.int_queue);
	290	status = tpm_tis_status(chip);
	291	if ((status & TPM_STS_DATA_EXPECT) == 0) {
	292	rc = -EIO;
	293	goto out_err;
	294	}
	295	}
	296
	297	/* write last byte */
	298	iowrite8(buf[count],
	299	chip->vendor.iobase +
	300	TPM_DATA_FIFO(chip->vendor.locality));
	301	wait_for_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
	302	&chip->vendor.int_queue);
	303	status = tpm_tis_status(chip);
	304	if ((status & TPM_STS_DATA_EXPECT) != 0) {
	305	rc = -EIO;
	306	goto out_err;
	307	}
	308
	309	/* go and do it */
	310	iowrite8(TPM_STS_GO,
	311	chip->vendor.iobase + TPM_STS(chip->vendor.locality));
	312
	313	if (chip->vendor.irq) {
	314	ordinal = be32_to_cpu(((__be32 ) (buf + 6)));
	315	if (wait_for_stat
	316	(chip, TPM_STS_DATA_AVAIL \| TPM_STS_VALID,
	317	tpm_calc_ordinal_duration(chip, ordinal),
	318	&chip->vendor.read_queue) < 0) {
	319	rc = -ETIME;
	320	goto out_err;
	321	}
	322	}
	323	return len;
	324	out_err:
325	tpm_tis_ready(chip);
326	release_locality(chip, chip->vendor.locality, 0);
327	return rc;
328	}
329
330	static struct file_operations tis_ops = {
331	.owner = THIS_MODULE,
332	.llseek = no_llseek,
333	.open = tpm_open,
334	.read = tpm_read,
335	.write = tpm_write,
336	.release = tpm_release,
337	};
338
339	static DEVICE_ATTR(pubek, S_IRUGO, tpm_show_pubek, NULL);
340	static DEVICE_ATTR(pcrs, S_IRUGO, tpm_show_pcrs, NULL);
341	static DEVICE_ATTR(enabled, S_IRUGO, tpm_show_enabled, NULL);
342	static DEVICE_ATTR(active, S_IRUGO, tpm_show_active, NULL);
343	static DEVICE_ATTR(owned, S_IRUGO, tpm_show_owned, NULL);
344	static DEVICE_ATTR(temp_deactivated, S_IRUGO, tpm_show_temp_deactivated,
345	NULL);
346	static DEVICE_ATTR(caps, S_IRUGO, tpm_show_caps_1_2, NULL);
347	static DEVICE_ATTR(cancel, S_IWUSR \| S_IWGRP, NULL, tpm_store_cancel);
348
349	static struct attribute *tis_attrs[] = {
350	&dev_attr_pubek.attr,
351	&dev_attr_pcrs.attr,
352	&dev_attr_enabled.attr,
353	&dev_attr_active.attr,
354	&dev_attr_owned.attr,
355	&dev_attr_temp_deactivated.attr,
356	&dev_attr_caps.attr,
357	&dev_attr_cancel.attr, NULL,
358	};
359
360	static struct attribute_group tis_attr_grp = {
361	.attrs = tis_attrs
362	};
363
364	static struct tpm_vendor_specific tpm_tis = {
365	.status = tpm_tis_status,
366	.recv = tpm_tis_recv,
367	.send = tpm_tis_send,
368	.cancel = tpm_tis_ready,
369	.req_complete_mask = TPM_STS_DATA_AVAIL \| TPM_STS_VALID,
370	.req_complete_val = TPM_STS_DATA_AVAIL \| TPM_STS_VALID,
371	.req_canceled = TPM_STS_COMMAND_READY,
372	.attr_group = &tis_attr_grp,
373	.miscdev = {
374	.fops = &tis_ops,},
375	};
376
cb535425	377	static irqreturn_t tis_int_probe(int irq, void dev_id, struct pt_regs regs)
27084efe LD	378	{
	379	struct tpm_chip chip = (struct tpm_chip ) dev_id;
	380	u32 interrupt;
	381
	382	interrupt = ioread32(chip->vendor.iobase +
	383	TPM_INT_STATUS(chip->vendor.locality));
	384
	385	if (interrupt == 0)
	386	return IRQ_NONE;
	387
	388	chip->vendor.irq = irq;
	389
	390	/* Clear interrupts handled with TPM_EOI */
	391	iowrite32(interrupt,
	392	chip->vendor.iobase +
	393	TPM_INT_STATUS(chip->vendor.locality));
	394	return IRQ_HANDLED;
	395	}
	396
cb535425	397	static irqreturn_t tis_int_handler(int irq, void dev_id, struct pt_regs regs)
27084efe LD	398	{
	399	struct tpm_chip chip = (struct tpm_chip ) dev_id;
	400	u32 interrupt;
	401	int i;
	402
	403	interrupt = ioread32(chip->vendor.iobase +
	404	TPM_INT_STATUS(chip->vendor.locality));
	405
	406	if (interrupt == 0)
	407	return IRQ_NONE;
	408
	409	if (interrupt & TPM_INTF_DATA_AVAIL_INT)
	410	wake_up_interruptible(&chip->vendor.read_queue);
	411	if (interrupt & TPM_INTF_LOCALITY_CHANGE_INT)
	412	for (i = 0; i < 5; i++)
	413	if (check_locality(chip, i) >= 0)
	414	break;
	415	if (interrupt &
	416	(TPM_INTF_LOCALITY_CHANGE_INT \| TPM_INTF_STS_VALID_INT \|
	417	TPM_INTF_CMD_READY_INT))
	418	wake_up_interruptible(&chip->vendor.int_queue);
	419
	420	/* Clear interrupts handled with TPM_EOI */
	421	iowrite32(interrupt,
	422	chip->vendor.iobase +
	423	TPM_INT_STATUS(chip->vendor.locality));
	424	return IRQ_HANDLED;
	425	}
	426
cb535425 KJH	427	static int __devinit tpm_tis_pnp_init(struct pnp_dev *pnp_dev,
cb535425 KJH	428	const struct pnp_device_id *pnp_id)
27084efe LD	429	{
	430	u32 vendor, intfcaps, intmask;
	431	int rc, i;
	432	unsigned long start, len;
	433	struct tpm_chip *chip;
	434
	435	start = pnp_mem_start(pnp_dev, 0);
	436	len = pnp_mem_len(pnp_dev, 0);
	437
b09d5300 KJH	438	if (!start)
	439	start = TIS_MEM_BASE;
	440	if (!len)
	441	len = TIS_MEM_LEN;
	442
27084efe LD	443	if (!(chip = tpm_register_hardware(&pnp_dev->dev, &tpm_tis)))
	444	return -ENODEV;
	445
	446	chip->vendor.iobase = ioremap(start, len);
	447	if (!chip->vendor.iobase) {
	448	rc = -EIO;
	449	goto out_err;
	450	}
	451
	452	vendor = ioread32(chip->vendor.iobase + TPM_DID_VID(0));
	453	if ((vendor & 0xFFFF) == 0xFFFF) {
	454	rc = -ENODEV;
	455	goto out_err;
	456	}
	457
	458	/* Default timeouts */
36b20020 KJH	459	chip->vendor.timeout_a = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
	460	chip->vendor.timeout_b = msecs_to_jiffies(TIS_LONG_TIMEOUT);
	461	chip->vendor.timeout_c = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
	462	chip->vendor.timeout_d = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
27084efe LD	463
	464	dev_info(&pnp_dev->dev,
	465	"1.2 TPM (device-id 0x%X, rev-id %d)\n",
	466	vendor >> 16, ioread8(chip->vendor.iobase + TPM_RID(0)));
	467
	468	/* Figure out the capabilities */
	469	intfcaps =
	470	ioread32(chip->vendor.iobase +
	471	TPM_INTF_CAPS(chip->vendor.locality));
	472	dev_dbg(&pnp_dev->dev, "TPM interface capabilities (0x%x):\n",
	473	intfcaps);
	474	if (intfcaps & TPM_INTF_BURST_COUNT_STATIC)
	475	dev_dbg(&pnp_dev->dev, "\tBurst Count Static\n");
	476	if (intfcaps & TPM_INTF_CMD_READY_INT)
	477	dev_dbg(&pnp_dev->dev, "\tCommand Ready Int Support\n");
	478	if (intfcaps & TPM_INTF_INT_EDGE_FALLING)
	479	dev_dbg(&pnp_dev->dev, "\tInterrupt Edge Falling\n");
	480	if (intfcaps & TPM_INTF_INT_EDGE_RISING)
	481	dev_dbg(&pnp_dev->dev, "\tInterrupt Edge Rising\n");
	482	if (intfcaps & TPM_INTF_INT_LEVEL_LOW)
	483	dev_dbg(&pnp_dev->dev, "\tInterrupt Level Low\n");
	484	if (intfcaps & TPM_INTF_INT_LEVEL_HIGH)
	485	dev_dbg(&pnp_dev->dev, "\tInterrupt Level High\n");
	486	if (intfcaps & TPM_INTF_LOCALITY_CHANGE_INT)
	487	dev_dbg(&pnp_dev->dev, "\tLocality Change Int Support\n");
	488	if (intfcaps & TPM_INTF_STS_VALID_INT)
	489	dev_dbg(&pnp_dev->dev, "\tSts Valid Int Support\n");
	490	if (intfcaps & TPM_INTF_DATA_AVAIL_INT)
	491	dev_dbg(&pnp_dev->dev, "\tData Avail Int Support\n");
	492
	493	if (request_locality(chip, 0) != 0) {
	494	rc = -ENODEV;
	495	goto out_err;
	496	}
	497
	498	/* INTERRUPT Setup */
	499	init_waitqueue_head(&chip->vendor.read_queue);
	500	init_waitqueue_head(&chip->vendor.int_queue);
	501
	502	intmask =
	503	ioread32(chip->vendor.iobase +
	504	TPM_INT_ENABLE(chip->vendor.locality));
	505
	506	intmask \|= TPM_INTF_CMD_READY_INT
	507	\| TPM_INTF_LOCALITY_CHANGE_INT \| TPM_INTF_DATA_AVAIL_INT
	508	\| TPM_INTF_STS_VALID_INT;
	509
	510	iowrite32(intmask,
	511	chip->vendor.iobase +
	512	TPM_INT_ENABLE(chip->vendor.locality));
	513
	514	chip->vendor.irq =
	515	ioread8(chip->vendor.iobase +
	516	TPM_INT_VECTOR(chip->vendor.locality));
	517
	518	for (i = 3; i < 16 && chip->vendor.irq == 0; i++) {
	519	iowrite8(i,
	520	chip->vendor.iobase +
	521	TPM_INT_VECTOR(chip->vendor.locality));
	522	if (request_irq
	523	(i, tis_int_probe, SA_SHIRQ,
	524	chip->vendor.miscdev.name, chip) != 0) {
	525	dev_info(chip->dev,
	526	"Unable to request irq: %d for probe\n",
527	i);
528	continue;
529	}
530
531	/* Clear all existing */
532	iowrite32(ioread32
533	(chip->vendor.iobase +
534	TPM_INT_STATUS(chip->vendor.locality)),
535	chip->vendor.iobase +
536	TPM_INT_STATUS(chip->vendor.locality));
537
538	/* Turn on */
539	iowrite32(intmask \| TPM_GLOBAL_INT_ENABLE,
540	chip->vendor.iobase +
541	TPM_INT_ENABLE(chip->vendor.locality));
542
543	/* Generate Interrupts */
544	tpm_gen_interrupt(chip);
545
546	/* Turn off */
547	iowrite32(intmask,
548	chip->vendor.iobase +
549	TPM_INT_ENABLE(chip->vendor.locality));
550	free_irq(i, chip);
551	}
552	if (chip->vendor.irq) {
553	iowrite8(chip->vendor.irq,
554	chip->vendor.iobase +
555	TPM_INT_VECTOR(chip->vendor.locality));
556	if (request_irq
557	(chip->vendor.irq, tis_int_handler, SA_SHIRQ,
558	chip->vendor.miscdev.name, chip) != 0) {
559	dev_info(chip->dev,
560	"Unable to request irq: %d for use\n", i);
561	chip->vendor.irq = 0;
562	} else {
563	/* Clear all existing */
564	iowrite32(ioread32
565	(chip->vendor.iobase +
566	TPM_INT_STATUS(chip->vendor.locality)),
567	chip->vendor.iobase +
568	TPM_INT_STATUS(chip->vendor.locality));
569
570	/* Turn on */
571	iowrite32(intmask \| TPM_GLOBAL_INT_ENABLE,
572	chip->vendor.iobase +
573	TPM_INT_ENABLE(chip->vendor.locality));
574	}
575	}
576
577	INIT_LIST_HEAD(&chip->vendor.list);
578	spin_lock(&tis_lock);
579	list_add(&chip->vendor.list, &tis_chips);
580	spin_unlock(&tis_lock);
581
582	tpm_get_timeouts(chip);
583	tpm_continue_selftest(chip);
584
585	return 0;
586	out_err:
587	if (chip->vendor.iobase)
588	iounmap(chip->vendor.iobase);
589	tpm_remove_hardware(chip->dev);
590	return rc;
591	}
592
593	static int tpm_tis_pnp_suspend(struct pnp_dev *dev, pm_message_t msg)
594	{
595	return tpm_pm_suspend(&dev->dev, msg);
596	}
597
598	static int tpm_tis_pnp_resume(struct pnp_dev *dev)
599	{
600	return tpm_pm_resume(&dev->dev);
601	}
602
603	static struct pnp_device_id tpm_pnp_tbl[] __devinitdata = {
604	{"PNP0C31", 0}, /* TPM */
605	{"", 0}
606	};
607
608	static struct pnp_driver tis_pnp_driver = {
609	.name = "tpm_tis",
610	.id_table = tpm_pnp_tbl,
611	.probe = tpm_tis_pnp_init,
612	.suspend = tpm_tis_pnp_suspend,
613	.resume = tpm_tis_pnp_resume,
614	};
615
616	static int __init init_tis(void)
617	{
618	return pnp_register_driver(&tis_pnp_driver);
619	}
620
621	static void __exit cleanup_tis(void)
622	{
623	struct tpm_vendor_specific i, j;
624	struct tpm_chip *chip;
625	spin_lock(&tis_lock);
626	list_for_each_entry_safe(i, j, &tis_chips, list) {
627	chip = to_tpm_chip(i);
628	iowrite32(~TPM_GLOBAL_INT_ENABLE &
629	ioread32(chip->vendor.iobase +
630	TPM_INT_ENABLE(chip->vendor.
631	locality)),
632	chip->vendor.iobase +
633	TPM_INT_ENABLE(chip->vendor.locality));
634	release_locality(chip, chip->vendor.locality, 1);
635	if (chip->vendor.irq)
636	free_irq(chip->vendor.irq, chip);
637	iounmap(i->iobase);
638	list_del(&i->list);
639	tpm_remove_hardware(chip->dev);
640	}
641	spin_unlock(&tis_lock);
642	pnp_unregister_driver(&tis_pnp_driver);
643	}
644
645	module_init(init_tis);
646	module_exit(cleanup_tis);
647	MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
648	MODULE_DESCRIPTION("TPM Driver");
649	MODULE_VERSION("2.0");
650	MODULE_LICENSE("GPL");