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tiocmget: kill off the passing of the struct file
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / char / mxser.c
CommitLineData
1da177e4
LT		 1/*
2 * mxser.c -- MOXA Smartio/Industio family multiport serial driver.
3 *
80ff8a80
JS		 4 * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com).
5 * Copyright (C) 2006-2008 Jiri Slaby <jirislaby@gmail.com>
1da177e4 6 *
1c45607a
JS		 7 * This code is loosely based on the 1.8 moxa driver which is based on
8 * Linux serial driver, written by Linus Torvalds, Theodore T'so and
9 * others.
1da177e4
LT		 10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
8ea2c2ec 14 * (at your option) any later version.
1da177e4 15 *
1da177e4 16 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox
8eb04cf3
AC		 17 * <alan@lxorguk.ukuu.org.uk>. The original 1.8 code is available on
18 * www.moxa.com.
1da177e4 19 * - Fixed x86_64 cleanness
1da177e4
LT		 20 */
21
1da177e4 22#include <linux/module.h>
1da177e4
LT		 23#include <linux/errno.h>
24#include <linux/signal.h>
25#include <linux/sched.h>
26#include <linux/timer.h>
27#include <linux/interrupt.h>
28#include <linux/tty.h>
29#include <linux/tty_flip.h>
30#include <linux/serial.h>
31#include <linux/serial_reg.h>
32#include <linux/major.h>
33#include <linux/string.h>
34#include <linux/fcntl.h>
35#include <linux/ptrace.h>
1da177e4
LT		 36#include <linux/ioport.h>
37#include <linux/mm.h>
1da177e4
LT		 38#include <linux/delay.h>
39#include <linux/pci.h>
1977f032 40#include <linux/bitops.h>
5a0e3ad6 41#include <linux/slab.h>
1da177e4
LT		 42
43#include <asm/system.h>
44#include <asm/io.h>
45#include <asm/irq.h>
1da177e4
LT		 46#include <asm/uaccess.h>
47
48#include "mxser.h"
49
502f295f 50#define MXSER_VERSION "2.0.5" /* 1.14 */
1da177e4 51#define MXSERMAJOR 174
1da177e4 52
1da177e4 53#define MXSER_BOARDS 4 /* Max. boards */
1da177e4 54#define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */
1c45607a
JS		 55#define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD)
56#define MXSER_ISR_PASS_LIMIT 100
1da177e4 57
1c45607a
JS		 58/*CheckIsMoxaMust return value*/
59#define MOXA_OTHER_UART 0x00
60#define MOXA_MUST_MU150_HWID 0x01
61#define MOXA_MUST_MU860_HWID 0x02
62
1da177e4
LT		 63#define WAKEUP_CHARS 256
64
65#define UART_MCR_AFE 0x20
66#define UART_LSR_SPECIAL 0x1E
67
e129deff 68#define PCI_DEVICE_ID_POS104UL 0x1044
1c45607a 69#define PCI_DEVICE_ID_CB108 0x1080
e129deff 70#define PCI_DEVICE_ID_CP102UF 0x1023
502f295f 71#define PCI_DEVICE_ID_CP112UL 0x1120
1c45607a 72#define PCI_DEVICE_ID_CB114 0x1142
80ff8a80 73#define PCI_DEVICE_ID_CP114UL 0x1143
1c45607a
JS		 74#define PCI_DEVICE_ID_CB134I 0x1341
75#define PCI_DEVICE_ID_CP138U 0x1380
1da177e4 76
1da177e4
LT		 77
78#define C168_ASIC_ID 1
79#define C104_ASIC_ID 2
80#define C102_ASIC_ID 0xB
81#define CI132_ASIC_ID 4
82#define CI134_ASIC_ID 3
83#define CI104J_ASIC_ID 5
84
1c45607a
JS		 85#define MXSER_HIGHBAUD 1
86#define MXSER_HAS2 2
1da177e4 87
8ea2c2ec 88/* This is only for PCI */
1c45607a 89static const struct {
1da177e4
LT		 90 int type;
91 int tx_fifo;
92 int rx_fifo;
93 int xmit_fifo_size;
94 int rx_high_water;
95 int rx_trigger;
96 int rx_low_water;
97 long max_baud;
1c45607a 98} Gpci_uart_info[] = {
1da177e4
LT		 99 {MOXA_OTHER_UART, 16, 16, 16, 14, 14, 1, 921600L},
100 {MOXA_MUST_MU150_HWID, 64, 64, 64, 48, 48, 16, 230400L},
101 {MOXA_MUST_MU860_HWID, 128, 128, 128, 96, 96, 32, 921600L}
102};
1c45607a 103#define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info)
1da177e4 104
1c45607a
JS		 105struct mxser_cardinfo {
106 char *name;
107 unsigned int nports;
108 unsigned int flags;
109};
1da177e4 110
1c45607a
JS		 111static const struct mxser_cardinfo mxser_cards[] = {
112/* 0*/ { "C168 series", 8, },
113 { "C104 series", 4, },
114 { "CI-104J series", 4, },
115 { "C168H/PCI series", 8, },
116 { "C104H/PCI series", 4, },
117/* 5*/ { "C102 series", 4, MXSER_HAS2 }, /* C102-ISA */
118 { "CI-132 series", 4, MXSER_HAS2 },
119 { "CI-134 series", 4, },
120 { "CP-132 series", 2, },
121 { "CP-114 series", 4, },
122/*10*/ { "CT-114 series", 4, },
123 { "CP-102 series", 2, MXSER_HIGHBAUD },
124 { "CP-104U series", 4, },
125 { "CP-168U series", 8, },
126 { "CP-132U series", 2, },
127/*15*/ { "CP-134U series", 4, },
128 { "CP-104JU series", 4, },
129 { "Moxa UC7000 Serial", 8, }, /* RC7000 */
130 { "CP-118U series", 8, },
131 { "CP-102UL series", 2, },
132/*20*/ { "CP-102U series", 2, },
133 { "CP-118EL series", 8, },
134 { "CP-168EL series", 8, },
135 { "CP-104EL series", 4, },
136 { "CB-108 series", 8, },
137/*25*/ { "CB-114 series", 4, },
138 { "CB-134I series", 4, },
139 { "CP-138U series", 8, },
80ff8a80 140 { "POS-104UL series", 4, },
e129deff 141 { "CP-114UL series", 4, },
502f295f
JS		 142/*30*/ { "CP-102UF series", 2, },
143 { "CP-112UL series", 2, },
1c45607a 144};
1da177e4 145
1c45607a
JS		 146/* driver_data correspond to the lines in the structure above
147 see also ISA probe function before you change something */
1da177e4 148static struct pci_device_id mxser_pcibrds[] = {
1c45607a
JS		 149 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C168), .driver_data = 3 },
150 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C104), .driver_data = 4 },
151 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132), .driver_data = 8 },
152 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114), .driver_data = 9 },
153 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CT114), .driver_data = 10 },
154 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102), .driver_data = 11 },
155 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104U), .driver_data = 12 },
156 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168U), .driver_data = 13 },
157 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132U), .driver_data = 14 },
158 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134U), .driver_data = 15 },
159 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104JU),.driver_data = 16 },
160 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_RC7000), .driver_data = 17 },
161 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118U), .driver_data = 18 },
162 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102UL),.driver_data = 19 },
163 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102U), .driver_data = 20 },
164 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL),.driver_data = 21 },
165 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL),.driver_data = 22 },
166 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL),.driver_data = 23 },
167 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB108), .driver_data = 24 },
168 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB114), .driver_data = 25 },
169 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB134I), .driver_data = 26 },
170 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP138U), .driver_data = 27 },
171 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_POS104UL), .driver_data = 28 },
80ff8a80 172 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP114UL), .driver_data = 29 },
e129deff 173 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP102UF), .driver_data = 30 },
502f295f 174 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP112UL), .driver_data = 31 },
1c45607a 175 { }
1da177e4 176};
1da177e4
LT		 177MODULE_DEVICE_TABLE(pci, mxser_pcibrds);
178
1df00924 179static unsigned long ioaddr[MXSER_BOARDS];
1da177e4 180static int ttymajor = MXSERMAJOR;
1da177e4
LT		 181
182/* Variables for insmod */
183
184MODULE_AUTHOR("Casper Yang");
185MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver");
1df00924
JS		 186module_param_array(ioaddr, ulong, NULL, 0);
187MODULE_PARM_DESC(ioaddr, "ISA io addresses to look for a moxa board");
8d3b33f6 188module_param(ttymajor, int, 0);
1da177e4
LT		 189MODULE_LICENSE("GPL");
190
191struct mxser_log {
192 int tick;
193 unsigned long rxcnt[MXSER_PORTS];
194 unsigned long txcnt[MXSER_PORTS];
195};
196
1da177e4
LT		 197struct mxser_mon {
198 unsigned long rxcnt;
199 unsigned long txcnt;
200 unsigned long up_rxcnt;
201 unsigned long up_txcnt;
202 int modem_status;
203 unsigned char hold_reason;
204};
205
206struct mxser_mon_ext {
207 unsigned long rx_cnt[32];
208 unsigned long tx_cnt[32];
209 unsigned long up_rxcnt[32];
210 unsigned long up_txcnt[32];
211 int modem_status[32];
212
213 long baudrate[32];
214 int databits[32];
215 int stopbits[32];
216 int parity[32];
217 int flowctrl[32];
218 int fifo[32];
219 int iftype[32];
220};
8ea2c2ec 221
1c45607a
JS		 222struct mxser_board;
223
224struct mxser_port {
0ad9e7d1 225 struct tty_port port;
1c45607a 226 struct mxser_board *board;
1c45607a
JS		 227
228 unsigned long ioaddr;
229 unsigned long opmode_ioaddr;
230 int max_baud;
1da177e4 231
1da177e4
LT		 232 int rx_high_water;
233 int rx_trigger; /* Rx fifo trigger level */
234 int rx_low_water;
235 int baud_base; /* max. speed */
1da177e4 236 int type; /* UART type */
1c45607a 237
1da177e4 238 int x_char; /* xon/xoff character */
1da177e4
LT		 239 int IER; /* Interrupt Enable Register */
240 int MCR; /* Modem control register */
1c45607a
JS		 241
242 unsigned char stop_rx;
243 unsigned char ldisc_stop_rx;
244
245 int custom_divisor;
1c45607a 246 unsigned char err_shadow;
1c45607a 247
1c45607a
JS		 248 struct async_icount icount; /* kernel counters for 4 input interrupts */
249 int timeout;
250
251 int read_status_mask;
252 int ignore_status_mask;
253 int xmit_fifo_size;
1da177e4
LT		 254 int xmit_head;
255 int xmit_tail;
256 int xmit_cnt;
1c45607a 257
606d099c 258 struct ktermios normal_termios;
1c45607a 259
1da177e4 260 struct mxser_mon mon_data;
1c45607a 261
1da177e4 262 spinlock_t slock;
1c45607a
JS		 263};
264
265struct mxser_board {
266 unsigned int idx;
267 int irq;
268 const struct mxser_cardinfo *info;
269 unsigned long vector;
270 unsigned long vector_mask;
271
272 int chip_flag;
273 int uart_type;
274
275 struct mxser_port ports[MXSER_PORTS_PER_BOARD];
1da177e4
LT		 276};
277
1da177e4
LT		 278struct mxser_mstatus {
279 tcflag_t cflag;
280 int cts;
281 int dsr;
282 int ri;
283 int dcd;
284};
285
1c45607a 286static struct mxser_board mxser_boards[MXSER_BOARDS];
1da177e4 287static struct tty_driver *mxvar_sdriver;
1da177e4 288static struct mxser_log mxvar_log;
1da177e4 289static int mxser_set_baud_method[MXSER_PORTS + 1];
1da177e4 290
148ff86b
CH		 291static void mxser_enable_must_enchance_mode(unsigned long baseio)
292{
293 u8 oldlcr;
294 u8 efr;
295
296 oldlcr = inb(baseio + UART_LCR);
297 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
298
299 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
300 efr |= MOXA_MUST_EFR_EFRB_ENABLE;
301
302 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
303 outb(oldlcr, baseio + UART_LCR);
304}
305
e89d67cf 306#ifdef CONFIG_PCI
148ff86b
CH		 307static void mxser_disable_must_enchance_mode(unsigned long baseio)
308{
309 u8 oldlcr;
310 u8 efr;
311
312 oldlcr = inb(baseio + UART_LCR);
313 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
314
315 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
316 efr &= ~MOXA_MUST_EFR_EFRB_ENABLE;
317
318 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
319 outb(oldlcr, baseio + UART_LCR);
320}
e89d67cf 321#endif
148ff86b
CH		 322
323static void mxser_set_must_xon1_value(unsigned long baseio, u8 value)
324{
325 u8 oldlcr;
326 u8 efr;
327
328 oldlcr = inb(baseio + UART_LCR);
329 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
330
331 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
332 efr &= ~MOXA_MUST_EFR_BANK_MASK;
333 efr |= MOXA_MUST_EFR_BANK0;
334
335 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
336 outb(value, baseio + MOXA_MUST_XON1_REGISTER);
337 outb(oldlcr, baseio + UART_LCR);
338}
339
340static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value)
341{
342 u8 oldlcr;
343 u8 efr;
344
345 oldlcr = inb(baseio + UART_LCR);
346 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
347
348 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
349 efr &= ~MOXA_MUST_EFR_BANK_MASK;
350 efr |= MOXA_MUST_EFR_BANK0;
351
352 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
353 outb(value, baseio + MOXA_MUST_XOFF1_REGISTER);
354 outb(oldlcr, baseio + UART_LCR);
355}
356
357static void mxser_set_must_fifo_value(struct mxser_port *info)
358{
359 u8 oldlcr;
360 u8 efr;
361
362 oldlcr = inb(info->ioaddr + UART_LCR);
363 outb(MOXA_MUST_ENTER_ENCHANCE, info->ioaddr + UART_LCR);
364
365 efr = inb(info->ioaddr + MOXA_MUST_EFR_REGISTER);
366 efr &= ~MOXA_MUST_EFR_BANK_MASK;
367 efr |= MOXA_MUST_EFR_BANK1;
368
369 outb(efr, info->ioaddr + MOXA_MUST_EFR_REGISTER);
370 outb((u8)info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER);
371 outb((u8)info->rx_trigger, info->ioaddr + MOXA_MUST_RBRTI_REGISTER);
372 outb((u8)info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER);
373 outb(oldlcr, info->ioaddr + UART_LCR);
374}
375
376static void mxser_set_must_enum_value(unsigned long baseio, u8 value)
377{
378 u8 oldlcr;
379 u8 efr;
380
381 oldlcr = inb(baseio + UART_LCR);
382 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
383
384 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
385 efr &= ~MOXA_MUST_EFR_BANK_MASK;
386 efr |= MOXA_MUST_EFR_BANK2;
387
388 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
389 outb(value, baseio + MOXA_MUST_ENUM_REGISTER);
390 outb(oldlcr, baseio + UART_LCR);
391}
392
e89d67cf 393#ifdef CONFIG_PCI
148ff86b
CH		 394static void mxser_get_must_hardware_id(unsigned long baseio, u8 *pId)
395{
396 u8 oldlcr;
397 u8 efr;
398
399 oldlcr = inb(baseio + UART_LCR);
400 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
401
402 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
403 efr &= ~MOXA_MUST_EFR_BANK_MASK;
404 efr |= MOXA_MUST_EFR_BANK2;
405
406 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
407 *pId = inb(baseio + MOXA_MUST_HWID_REGISTER);
408 outb(oldlcr, baseio + UART_LCR);
409}
e89d67cf 410#endif
148ff86b
CH		 411
412static void SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(unsigned long baseio)
413{
414 u8 oldlcr;
415 u8 efr;
416
417 oldlcr = inb(baseio + UART_LCR);
418 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
419
420 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
421 efr &= ~MOXA_MUST_EFR_SF_MASK;
422
423 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
424 outb(oldlcr, baseio + UART_LCR);
425}
426
427static void mxser_enable_must_tx_software_flow_control(unsigned long baseio)
428{
429 u8 oldlcr;
430 u8 efr;
431
432 oldlcr = inb(baseio + UART_LCR);
433 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
434
435 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
436 efr &= ~MOXA_MUST_EFR_SF_TX_MASK;
437 efr |= MOXA_MUST_EFR_SF_TX1;
438
439 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
440 outb(oldlcr, baseio + UART_LCR);
441}
442
443static void mxser_disable_must_tx_software_flow_control(unsigned long baseio)
444{
445 u8 oldlcr;
446 u8 efr;
447
448 oldlcr = inb(baseio + UART_LCR);
449 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
450
451 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
452 efr &= ~MOXA_MUST_EFR_SF_TX_MASK;
453
454 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
455 outb(oldlcr, baseio + UART_LCR);
456}
457
458static void mxser_enable_must_rx_software_flow_control(unsigned long baseio)
459{
460 u8 oldlcr;
461 u8 efr;
462
463 oldlcr = inb(baseio + UART_LCR);
464 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
465
466 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
467 efr &= ~MOXA_MUST_EFR_SF_RX_MASK;
468 efr |= MOXA_MUST_EFR_SF_RX1;
469
470 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
471 outb(oldlcr, baseio + UART_LCR);
472}
473
474static void mxser_disable_must_rx_software_flow_control(unsigned long baseio)
475{
476 u8 oldlcr;
477 u8 efr;
478
479 oldlcr = inb(baseio + UART_LCR);
480 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
481
482 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
483 efr &= ~MOXA_MUST_EFR_SF_RX_MASK;
484
485 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
486 outb(oldlcr, baseio + UART_LCR);
487}
488
b8cc5549 489#ifdef CONFIG_PCI
1c45607a 490static int __devinit CheckIsMoxaMust(unsigned long io)
1da177e4
LT		 491{
492 u8 oldmcr, hwid;
493 int i;
494
495 outb(0, io + UART_LCR);
148ff86b 496 mxser_disable_must_enchance_mode(io);
1da177e4
LT		 497 oldmcr = inb(io + UART_MCR);
498 outb(0, io + UART_MCR);
148ff86b 499 mxser_set_must_xon1_value(io, 0x11);
1da177e4
LT		 500 if ((hwid = inb(io + UART_MCR)) != 0) {
501 outb(oldmcr, io + UART_MCR);
8ea2c2ec 502 return MOXA_OTHER_UART;
1da177e4
LT		 503 }
504
148ff86b 505 mxser_get_must_hardware_id(io, &hwid);
1c45607a
JS		 506 for (i = 1; i < UART_INFO_NUM; i++) { /* 0 = OTHER_UART */
507 if (hwid == Gpci_uart_info[i].type)
8ea2c2ec 508 return (int)hwid;
1da177e4
LT		 509 }
510 return MOXA_OTHER_UART;
511}
b8cc5549 512#endif
1da177e4 513
1c45607a 514static void process_txrx_fifo(struct mxser_port *info)
1da177e4
LT		 515{
516 int i;
517
518 if ((info->type == PORT_16450) || (info->type == PORT_8250)) {
519 info->rx_trigger = 1;
520 info->rx_high_water = 1;
521 info->rx_low_water = 1;
522 info->xmit_fifo_size = 1;
1c45607a
JS		 523 } else
524 for (i = 0; i < UART_INFO_NUM; i++)
525 if (info->board->chip_flag == Gpci_uart_info[i].type) {
1da177e4
LT		 526 info->rx_trigger = Gpci_uart_info[i].rx_trigger;
527 info->rx_low_water = Gpci_uart_info[i].rx_low_water;
528 info->rx_high_water = Gpci_uart_info[i].rx_high_water;
529 info->xmit_fifo_size = Gpci_uart_info[i].xmit_fifo_size;
530 break;
531 }
1da177e4
LT		 532}
533
1c45607a 534static unsigned char mxser_get_msr(int baseaddr, int mode, int port)
1da177e4 535{
72800df9 536 static unsigned char mxser_msr[MXSER_PORTS + 1];
1c45607a 537 unsigned char status = 0;
1da177e4 538
1c45607a 539 status = inb(baseaddr + UART_MSR);
1da177e4 540
1c45607a
JS		 541 mxser_msr[port] &= 0x0F;
542 mxser_msr[port] |= status;
543 status = mxser_msr[port];
544 if (mode)
545 mxser_msr[port] = 0;
1da177e4 546
1c45607a
JS		 547 return status;
548}
1da177e4 549
31f35939
AC		 550static int mxser_carrier_raised(struct tty_port *port)
551{
552 struct mxser_port *mp = container_of(port, struct mxser_port, port);
553 return (inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD)?1:0;
554}
555
fcc8ac18 556static void mxser_dtr_rts(struct tty_port *port, int on)
5d951fb4
AC		 557{
558 struct mxser_port *mp = container_of(port, struct mxser_port, port);
559 unsigned long flags;
560
561 spin_lock_irqsave(&mp->slock, flags);
fcc8ac18
AC		 562 if (on)
563 outb(inb(mp->ioaddr + UART_MCR) |
564 UART_MCR_DTR | UART_MCR_RTS, mp->ioaddr + UART_MCR);
565 else
566 outb(inb(mp->ioaddr + UART_MCR)&~(UART_MCR_DTR | UART_MCR_RTS),
567 mp->ioaddr + UART_MCR);
5d951fb4
AC		 568 spin_unlock_irqrestore(&mp->slock, flags);
569}
570
216ba023 571static int mxser_set_baud(struct tty_struct *tty, long newspd)
1da177e4 572{
216ba023 573 struct mxser_port *info = tty->driver_data;
1c45607a
JS		 574 int quot = 0, baud;
575 unsigned char cval;
1da177e4 576
216ba023 577 if (!info->ioaddr)
1c45607a 578 return -1;
1da177e4 579
1c45607a
JS		 580 if (newspd > info->max_baud)
581 return -1;
1da177e4 582
1c45607a
JS		 583 if (newspd == 134) {
584 quot = 2 * info->baud_base / 269;
216ba023 585 tty_encode_baud_rate(tty, 134, 134);
1c45607a
JS		 586 } else if (newspd) {
587 quot = info->baud_base / newspd;
588 if (quot == 0)
589 quot = 1;
590 baud = info->baud_base/quot;
216ba023 591 tty_encode_baud_rate(tty, baud, baud);
1c45607a
JS		 592 } else {
593 quot = 0;
594 }
1da177e4 595
1c45607a
JS		 596 info->timeout = ((info->xmit_fifo_size * HZ * 10 * quot) / info->baud_base);
597 info->timeout += HZ / 50; /* Add .02 seconds of slop */
1da177e4 598
1c45607a
JS		 599 if (quot) {
600 info->MCR |= UART_MCR_DTR;
601 outb(info->MCR, info->ioaddr + UART_MCR);
602 } else {
603 info->MCR &= ~UART_MCR_DTR;
604 outb(info->MCR, info->ioaddr + UART_MCR);
605 return 0;
606 }
1da177e4 607
1c45607a 608 cval = inb(info->ioaddr + UART_LCR);
1da177e4 609
1c45607a 610 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */
1da177e4 611
1c45607a
JS		 612 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */
613 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */
614 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */
1da177e4 615
1c45607a 616#ifdef BOTHER
216ba023 617 if (C_BAUD(tty) == BOTHER) {
1c45607a
JS		 618 quot = info->baud_base % newspd;
619 quot *= 8;
620 if (quot % newspd > newspd / 2) {
621 quot /= newspd;
622 quot++;
623 } else
624 quot /= newspd;
625
148ff86b 626 mxser_set_must_enum_value(info->ioaddr, quot);
1c45607a
JS		 627 } else
628#endif
148ff86b 629 mxser_set_must_enum_value(info->ioaddr, 0);
1da177e4 630
8ea2c2ec 631 return 0;
1da177e4 632}
1da177e4 633
1c45607a
JS		 634/*
635 * This routine is called to set the UART divisor registers to match
636 * the specified baud rate for a serial port.
637 */
216ba023
AC		 638static int mxser_change_speed(struct tty_struct *tty,
639 struct ktermios *old_termios)
1da177e4 640{
216ba023 641 struct mxser_port *info = tty->driver_data;
1c45607a
JS		 642 unsigned cflag, cval, fcr;
643 int ret = 0;
644 unsigned char status;
1da177e4 645
216ba023
AC		 646 cflag = tty->termios->c_cflag;
647 if (!info->ioaddr)
1c45607a 648 return ret;
1da177e4 649
216ba023
AC		 650 if (mxser_set_baud_method[tty->index] == 0)
651 mxser_set_baud(tty, tty_get_baud_rate(tty));
1da177e4 652
1c45607a
JS		 653 /* byte size and parity */
654 switch (cflag & CSIZE) {
655 case CS5:
656 cval = 0x00;
657 break;
658 case CS6:
659 cval = 0x01;
660 break;
661 case CS7:
662 cval = 0x02;
663 break;
664 case CS8:
665 cval = 0x03;
666 break;
667 default:
668 cval = 0x00;
669 break; /* too keep GCC shut... */
670 }
671 if (cflag & CSTOPB)
672 cval |= 0x04;
673 if (cflag & PARENB)
674 cval |= UART_LCR_PARITY;
675 if (!(cflag & PARODD))
676 cval |= UART_LCR_EPAR;
677 if (cflag & CMSPAR)
678 cval |= UART_LCR_SPAR;
1da177e4 679
1c45607a
JS		 680 if ((info->type == PORT_8250) || (info->type == PORT_16450)) {
681 if (info->board->chip_flag) {
682 fcr = UART_FCR_ENABLE_FIFO;
683 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
148ff86b 684 mxser_set_must_fifo_value(info);
1c45607a
JS		 685 } else
686 fcr = 0;
687 } else {
688 fcr = UART_FCR_ENABLE_FIFO;
689 if (info->board->chip_flag) {
690 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
148ff86b 691 mxser_set_must_fifo_value(info);
1c45607a
JS		 692 } else {
693 switch (info->rx_trigger) {
694 case 1:
695 fcr |= UART_FCR_TRIGGER_1;
696 break;
697 case 4:
698 fcr |= UART_FCR_TRIGGER_4;
699 break;
700 case 8:
701 fcr |= UART_FCR_TRIGGER_8;
702 break;
703 default:
704 fcr |= UART_FCR_TRIGGER_14;
705 break;
706 }
1da177e4 707 }
1da177e4
LT		 708 }
709
1c45607a
JS		 710 /* CTS flow control flag and modem status interrupts */
711 info->IER &= ~UART_IER_MSI;
712 info->MCR &= ~UART_MCR_AFE;
713 if (cflag & CRTSCTS) {
0ad9e7d1 714 info->port.flags |= ASYNC_CTS_FLOW;
1c45607a
JS		 715 info->IER |= UART_IER_MSI;
716 if ((info->type == PORT_16550A) || (info->board->chip_flag)) {
717 info->MCR |= UART_MCR_AFE;
718 } else {
719 status = inb(info->ioaddr + UART_MSR);
216ba023 720 if (tty->hw_stopped) {
1c45607a 721 if (status & UART_MSR_CTS) {
216ba023 722 tty->hw_stopped = 0;
1c45607a
JS		 723 if (info->type != PORT_16550A &&
724 !info->board->chip_flag) {
725 outb(info->IER & ~UART_IER_THRI,
726 info->ioaddr +
727 UART_IER);
728 info->IER |= UART_IER_THRI;
729 outb(info->IER, info->ioaddr +
730 UART_IER);
731 }
216ba023 732 tty_wakeup(tty);
1c45607a
JS		 733 }
734 } else {
735 if (!(status & UART_MSR_CTS)) {
216ba023 736 tty->hw_stopped = 1;
1c45607a
JS		 737 if ((info->type != PORT_16550A) &&
738 (!info->board->chip_flag)) {
739 info->IER &= ~UART_IER_THRI;
740 outb(info->IER, info->ioaddr +
741 UART_IER);
742 }
743 }
744 }
1da177e4 745 }
1c45607a 746 } else {
0ad9e7d1 747 info->port.flags &= ~ASYNC_CTS_FLOW;
1c45607a
JS		 748 }
749 outb(info->MCR, info->ioaddr + UART_MCR);
750 if (cflag & CLOCAL) {
0ad9e7d1 751 info->port.flags &= ~ASYNC_CHECK_CD;
1c45607a 752 } else {
0ad9e7d1 753 info->port.flags |= ASYNC_CHECK_CD;
1c45607a
JS		 754 info->IER |= UART_IER_MSI;
755 }
756 outb(info->IER, info->ioaddr + UART_IER);
757
758 /*
759 * Set up parity check flag
760 */
761 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
216ba023 762 if (I_INPCK(tty))
1c45607a 763 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
216ba023 764 if (I_BRKINT(tty) || I_PARMRK(tty))
1c45607a 765 info->read_status_mask |= UART_LSR_BI;
1da177e4 766
1c45607a 767 info->ignore_status_mask = 0;
1da177e4 768
216ba023 769 if (I_IGNBRK(tty)) {
1c45607a
JS		 770 info->ignore_status_mask |= UART_LSR_BI;
771 info->read_status_mask |= UART_LSR_BI;
8ea2c2ec 772 /*
1c45607a
JS		 773 * If we're ignore parity and break indicators, ignore
774 * overruns too. (For real raw support).
8ea2c2ec 775 */
216ba023 776 if (I_IGNPAR(tty)) {
1c45607a
JS		 777 info->ignore_status_mask |=
778 UART_LSR_OE |
779 UART_LSR_PE |
780 UART_LSR_FE;
781 info->read_status_mask |=
782 UART_LSR_OE |
783 UART_LSR_PE |
784 UART_LSR_FE;
785 }
1da177e4 786 }
1c45607a 787 if (info->board->chip_flag) {
216ba023
AC		 788 mxser_set_must_xon1_value(info->ioaddr, START_CHAR(tty));
789 mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(tty));
790 if (I_IXON(tty)) {
148ff86b
CH		 791 mxser_enable_must_rx_software_flow_control(
792 info->ioaddr);
1c45607a 793 } else {
148ff86b
CH		 794 mxser_disable_must_rx_software_flow_control(
795 info->ioaddr);
1da177e4 796 }
216ba023 797 if (I_IXOFF(tty)) {
148ff86b
CH		 798 mxser_enable_must_tx_software_flow_control(
799 info->ioaddr);
1c45607a 800 } else {
148ff86b
CH		 801 mxser_disable_must_tx_software_flow_control(
802 info->ioaddr);
1da177e4
LT		 803 }
804 }
1da177e4 805
1da177e4 806
1c45607a
JS		 807 outb(fcr, info->ioaddr + UART_FCR); /* set fcr */
808 outb(cval, info->ioaddr + UART_LCR);
1da177e4 809
1c45607a 810 return ret;
1da177e4
LT		 811}
812
216ba023
AC		 813static void mxser_check_modem_status(struct tty_struct *tty,
814 struct mxser_port *port, int status)
1da177e4 815{
1c45607a
JS		 816 /* update input line counters */
817 if (status & UART_MSR_TERI)
818 port->icount.rng++;
819 if (status & UART_MSR_DDSR)
820 port->icount.dsr++;
821 if (status & UART_MSR_DDCD)
822 port->icount.dcd++;
823 if (status & UART_MSR_DCTS)
824 port->icount.cts++;
825 port->mon_data.modem_status = status;
bdc04e31 826 wake_up_interruptible(&port->port.delta_msr_wait);
1da177e4 827
0ad9e7d1 828 if ((port->port.flags & ASYNC_CHECK_CD) && (status & UART_MSR_DDCD)) {
1c45607a 829 if (status & UART_MSR_DCD)
0ad9e7d1 830 wake_up_interruptible(&port->port.open_wait);
1c45607a 831 }
1da177e4 832
0ad9e7d1 833 if (port->port.flags & ASYNC_CTS_FLOW) {
216ba023 834 if (tty->hw_stopped) {
1c45607a 835 if (status & UART_MSR_CTS) {
216ba023 836 tty->hw_stopped = 0;
1c45607a
JS		 837
838 if ((port->type != PORT_16550A) &&
839 (!port->board->chip_flag)) {
840 outb(port->IER & ~UART_IER_THRI,
841 port->ioaddr + UART_IER);
842 port->IER |= UART_IER_THRI;
843 outb(port->IER, port->ioaddr +
844 UART_IER);
845 }
216ba023 846 tty_wakeup(tty);
1c45607a
JS		 847 }
848 } else {
849 if (!(status & UART_MSR_CTS)) {
216ba023 850 tty->hw_stopped = 1;
1c45607a
JS		 851 if (port->type != PORT_16550A &&
852 !port->board->chip_flag) {
853 port->IER &= ~UART_IER_THRI;
854 outb(port->IER, port->ioaddr +
855 UART_IER);
856 }
857 }
858 }
1da177e4
LT		 859 }
860}
861
6769140d 862static int mxser_activate(struct tty_port *port, struct tty_struct *tty)
1da177e4 863{
6769140d 864 struct mxser_port *info = container_of(port, struct mxser_port, port);
1c45607a
JS		 865 unsigned long page;
866 unsigned long flags;
1da177e4 867
1c45607a
JS		 868 page = __get_free_page(GFP_KERNEL);
869 if (!page)
870 return -ENOMEM;
1da177e4 871
1c45607a 872 spin_lock_irqsave(&info->slock, flags);
1da177e4 873
1c45607a 874 if (!info->ioaddr || !info->type) {
216ba023 875 set_bit(TTY_IO_ERROR, &tty->flags);
1c45607a
JS		 876 free_page(page);
877 spin_unlock_irqrestore(&info->slock, flags);
1da177e4 878 return 0;
1c45607a 879 }
6769140d 880 info->port.xmit_buf = (unsigned char *) page;
1da177e4 881
1da177e4 882 /*
1c45607a
JS		 883 * Clear the FIFO buffers and disable them
884 * (they will be reenabled in mxser_change_speed())
1da177e4 885 */
1c45607a
JS		 886 if (info->board->chip_flag)
887 outb((UART_FCR_CLEAR_RCVR |
888 UART_FCR_CLEAR_XMIT |
889 MOXA_MUST_FCR_GDA_MODE_ENABLE), info->ioaddr + UART_FCR);
890 else
891 outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
892 info->ioaddr + UART_FCR);
1da177e4 893
1c45607a
JS		 894 /*
895 * At this point there's no way the LSR could still be 0xFF;
896 * if it is, then bail out, because there's likely no UART
897 * here.
898 */
899 if (inb(info->ioaddr + UART_LSR) == 0xff) {
900 spin_unlock_irqrestore(&info->slock, flags);
901 if (capable(CAP_SYS_ADMIN)) {
f43a510d 902 set_bit(TTY_IO_ERROR, &tty->flags);
1c45607a
JS		 903 return 0;
904 } else
905 return -ENODEV;
906 }
1da177e4 907
1c45607a
JS		 908 /*
909 * Clear the interrupt registers.
910 */
911 (void) inb(info->ioaddr + UART_LSR);
912 (void) inb(info->ioaddr + UART_RX);
913 (void) inb(info->ioaddr + UART_IIR);
914 (void) inb(info->ioaddr + UART_MSR);
915
916 /*
917 * Now, initialize the UART
918 */
919 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */
920 info->MCR = UART_MCR_DTR | UART_MCR_RTS;
921 outb(info->MCR, info->ioaddr + UART_MCR);
922
923 /*
924 * Finally, enable interrupts
925 */
926 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
927
928 if (info->board->chip_flag)
929 info->IER |= MOXA_MUST_IER_EGDAI;
930 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */
931
932 /*
933 * And clear the interrupt registers again for luck.
934 */
935 (void) inb(info->ioaddr + UART_LSR);
936 (void) inb(info->ioaddr + UART_RX);
937 (void) inb(info->ioaddr + UART_IIR);
938 (void) inb(info->ioaddr + UART_MSR);
939
216ba023 940 clear_bit(TTY_IO_ERROR, &tty->flags);
1c45607a
JS		 941 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
942
943 /*
944 * and set the speed of the serial port
945 */
216ba023 946 mxser_change_speed(tty, NULL);
1c45607a
JS		 947 spin_unlock_irqrestore(&info->slock, flags);
948
949 return 0;
950}
951
952/*
6769140d 953 * This routine will shutdown a serial port
1c45607a 954 */
6769140d 955static void mxser_shutdown_port(struct tty_port *port)
1c45607a 956{
6769140d 957 struct mxser_port *info = container_of(port, struct mxser_port, port);
1c45607a
JS		 958 unsigned long flags;
959
1c45607a
JS		 960 spin_lock_irqsave(&info->slock, flags);
961
962 /*
963 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
964 * here so the queue might never be waken up
965 */
bdc04e31 966 wake_up_interruptible(&info->port.delta_msr_wait);
1c45607a
JS		 967
968 /*
6769140d 969 * Free the xmit buffer, if necessary
1c45607a 970 */
0ad9e7d1
AC		 971 if (info->port.xmit_buf) {
972 free_page((unsigned long) info->port.xmit_buf);
973 info->port.xmit_buf = NULL;
1da177e4
LT		 974 }
975
1c45607a
JS		 976 info->IER = 0;
977 outb(0x00, info->ioaddr + UART_IER);
978
1c45607a
JS		 979 /* clear Rx/Tx FIFO's */
980 if (info->board->chip_flag)
981 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT |
982 MOXA_MUST_FCR_GDA_MODE_ENABLE,
983 info->ioaddr + UART_FCR);
984 else
985 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
986 info->ioaddr + UART_FCR);
987
988 /* read data port to reset things */
989 (void) inb(info->ioaddr + UART_RX);
990
1c45607a
JS		 991
992 if (info->board->chip_flag)
993 SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(info->ioaddr);
994
995 spin_unlock_irqrestore(&info->slock, flags);
996}
997
998/*
999 * This routine is called whenever a serial port is opened. It
1000 * enables interrupts for a serial port, linking in its async structure into
1001 * the IRQ chain. It also performs the serial-specific
1002 * initialization for the tty structure.
1003 */
1004static int mxser_open(struct tty_struct *tty, struct file *filp)
1005{
1006 struct mxser_port *info;
6769140d 1007 int line;
1c45607a
JS		 1008
1009 line = tty->index;
1010 if (line == MXSER_PORTS)
1011 return 0;
1012 if (line < 0 || line > MXSER_PORTS)
1013 return -ENODEV;
1014 info = &mxser_boards[line / MXSER_PORTS_PER_BOARD].ports[line % MXSER_PORTS_PER_BOARD];
1015 if (!info->ioaddr)
1016 return -ENODEV;
1017
a2d1e351 1018 tty->driver_data = info;
6769140d 1019 return tty_port_open(&info->port, tty, filp);
1da177e4
LT		 1020}
1021
978e595f
AC		 1022static void mxser_flush_buffer(struct tty_struct *tty)
1023{
1024 struct mxser_port *info = tty->driver_data;
1025 char fcr;
1026 unsigned long flags;
1027
1028
1029 spin_lock_irqsave(&info->slock, flags);
1030 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1031
1032 fcr = inb(info->ioaddr + UART_FCR);
1033 outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
1034 info->ioaddr + UART_FCR);
1035 outb(fcr, info->ioaddr + UART_FCR);
1036
1037 spin_unlock_irqrestore(&info->slock, flags);
1038
1039 tty_wakeup(tty);
1040}
1041
1042
6769140d 1043static void mxser_close_port(struct tty_port *port)
1da177e4 1044{
1e2b0254 1045 struct mxser_port *info = container_of(port, struct mxser_port, port);
1da177e4 1046 unsigned long timeout;
1da177e4
LT		 1047 /*
1048 * At this point we stop accepting input. To do this, we
1049 * disable the receive line status interrupts, and tell the
1050 * interrupt driver to stop checking the data ready bit in the
1051 * line status register.
1052 */
1053 info->IER &= ~UART_IER_RLSI;
1c45607a 1054 if (info->board->chip_flag)
1da177e4 1055 info->IER &= ~MOXA_MUST_RECV_ISR;
1c45607a 1056
6769140d
AC		 1057 outb(info->IER, info->ioaddr + UART_IER);
1058 /*
1059 * Before we drop DTR, make sure the UART transmitter
1060 * has completely drained; this is especially
1061 * important if there is a transmit FIFO!
1062 */
1063 timeout = jiffies + HZ;
1064 while (!(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT)) {
1065 schedule_timeout_interruptible(5);
1066 if (time_after(jiffies, timeout))
1067 break;
1da177e4 1068 }
1e2b0254
AC		 1069}
1070
1071/*
1072 * This routine is called when the serial port gets closed. First, we
1073 * wait for the last remaining data to be sent. Then, we unlink its
1074 * async structure from the interrupt chain if necessary, and we free
1075 * that IRQ if nothing is left in the chain.
1076 */
1077static void mxser_close(struct tty_struct *tty, struct file *filp)
1078{
1079 struct mxser_port *info = tty->driver_data;
1080 struct tty_port *port = &info->port;
1081
a2d1e351 1082 if (tty->index == MXSER_PORTS || info == NULL)
1e2b0254
AC		 1083 return;
1084 if (tty_port_close_start(port, tty, filp) == 0)
1085 return;
6769140d
AC		 1086 mutex_lock(&port->mutex);
1087 mxser_close_port(port);
1e2b0254 1088 mxser_flush_buffer(tty);
6769140d
AC		 1089 mxser_shutdown_port(port);
1090 clear_bit(ASYNCB_INITIALIZED, &port->flags);
1091 mutex_unlock(&port->mutex);
a6614999
AC		 1092 /* Right now the tty_port set is done outside of the close_end helper
1093 as we don't yet have everyone using refcounts */
1094 tty_port_close_end(port, tty);
1095 tty_port_tty_set(port, NULL);
1da177e4
LT		 1096}
1097
1098static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count)
1099{
1100 int c, total = 0;
1c45607a 1101 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1102 unsigned long flags;
1103
0ad9e7d1 1104 if (!info->port.xmit_buf)
8ea2c2ec 1105 return 0;
1da177e4
LT		 1106
1107 while (1) {
8ea2c2ec
JJ		 1108 c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
1109 SERIAL_XMIT_SIZE - info->xmit_head));
1da177e4
LT		 1110 if (c <= 0)
1111 break;
1112
0ad9e7d1 1113 memcpy(info->port.xmit_buf + info->xmit_head, buf, c);
1da177e4 1114 spin_lock_irqsave(&info->slock, flags);
8ea2c2ec
JJ		 1115 info->xmit_head = (info->xmit_head + c) &
1116 (SERIAL_XMIT_SIZE - 1);
1da177e4
LT		 1117 info->xmit_cnt += c;
1118 spin_unlock_irqrestore(&info->slock, flags);
1119
1120 buf += c;
1121 count -= c;
1122 total += c;
1da177e4
LT		 1123 }
1124
1c45607a 1125 if (info->xmit_cnt && !tty->stopped) {
8ea2c2ec
JJ		 1126 if (!tty->hw_stopped ||
1127 (info->type == PORT_16550A) ||
1c45607a 1128 (info->board->chip_flag)) {
1da177e4 1129 spin_lock_irqsave(&info->slock, flags);
1c45607a
JS		 1130 outb(info->IER & ~UART_IER_THRI, info->ioaddr +
1131 UART_IER);
1da177e4 1132 info->IER |= UART_IER_THRI;
1c45607a 1133 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1134 spin_unlock_irqrestore(&info->slock, flags);
1135 }
1136 }
1137 return total;
1138}
1139
0be2eade 1140static int mxser_put_char(struct tty_struct *tty, unsigned char ch)
1da177e4 1141{
1c45607a 1142 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1143 unsigned long flags;
1144
0ad9e7d1 1145 if (!info->port.xmit_buf)
0be2eade 1146 return 0;
1da177e4
LT		 1147
1148 if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1)
0be2eade 1149 return 0;
1da177e4
LT		 1150
1151 spin_lock_irqsave(&info->slock, flags);
0ad9e7d1 1152 info->port.xmit_buf[info->xmit_head++] = ch;
1da177e4
LT		 1153 info->xmit_head &= SERIAL_XMIT_SIZE - 1;
1154 info->xmit_cnt++;
1155 spin_unlock_irqrestore(&info->slock, flags);
1c45607a 1156 if (!tty->stopped) {
8ea2c2ec
JJ		 1157 if (!tty->hw_stopped ||
1158 (info->type == PORT_16550A) ||
1c45607a 1159 info->board->chip_flag) {
1da177e4 1160 spin_lock_irqsave(&info->slock, flags);
1c45607a 1161 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1da177e4 1162 info->IER |= UART_IER_THRI;
1c45607a 1163 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1164 spin_unlock_irqrestore(&info->slock, flags);
1165 }
1166 }
0be2eade 1167 return 1;
1da177e4
LT		 1168}
1169
1170
1171static void mxser_flush_chars(struct tty_struct *tty)
1172{
1c45607a 1173 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1174 unsigned long flags;
1175
ace7dd96
JS		 1176 if (info->xmit_cnt <= 0 || tty->stopped || !info->port.xmit_buf ||
1177 (tty->hw_stopped && info->type != PORT_16550A &&
1178 !info->board->chip_flag))
1da177e4
LT		 1179 return;
1180
1181 spin_lock_irqsave(&info->slock, flags);
1182
1c45607a 1183 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1da177e4 1184 info->IER |= UART_IER_THRI;
1c45607a 1185 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1186
1187 spin_unlock_irqrestore(&info->slock, flags);
1188}
1189
1190static int mxser_write_room(struct tty_struct *tty)
1191{
1c45607a 1192 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1193 int ret;
1194
1195 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
ace7dd96 1196 return ret < 0 ? 0 : ret;
1da177e4
LT		 1197}
1198
1199static int mxser_chars_in_buffer(struct tty_struct *tty)
1200{
1c45607a 1201 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1202 return info->xmit_cnt;
1203}
1204
1c45607a
JS		 1205/*
1206 * ------------------------------------------------------------
1207 * friends of mxser_ioctl()
1208 * ------------------------------------------------------------
1209 */
216ba023 1210static int mxser_get_serial_info(struct tty_struct *tty,
1c45607a
JS		 1211 struct serial_struct __user *retinfo)
1212{
216ba023 1213 struct mxser_port *info = tty->driver_data;
1c45607a
JS		 1214 struct serial_struct tmp = {
1215 .type = info->type,
216ba023 1216 .line = tty->index,
1c45607a
JS		 1217 .port = info->ioaddr,
1218 .irq = info->board->irq,
0ad9e7d1 1219 .flags = info->port.flags,
1c45607a 1220 .baud_base = info->baud_base,
44b7d1b3
AC		 1221 .close_delay = info->port.close_delay,
1222 .closing_wait = info->port.closing_wait,
1c45607a
JS		 1223 .custom_divisor = info->custom_divisor,
1224 .hub6 = 0
1225 };
1226 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
1227 return -EFAULT;
1228 return 0;
1229}
1230
216ba023 1231static int mxser_set_serial_info(struct tty_struct *tty,
1c45607a 1232 struct serial_struct __user *new_info)
1da177e4 1233{
216ba023 1234 struct mxser_port *info = tty->driver_data;
07f86c03 1235 struct tty_port *port = &info->port;
1c45607a 1236 struct serial_struct new_serial;
80ff8a80 1237 speed_t baud;
1c45607a
JS		 1238 unsigned long sl_flags;
1239 unsigned int flags;
1240 int retval = 0;
1da177e4 1241
1c45607a 1242 if (!new_info || !info->ioaddr)
80ff8a80 1243 return -ENODEV;
1c45607a
JS		 1244 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
1245 return -EFAULT;
1da177e4 1246
80ff8a80
JS		 1247 if (new_serial.irq != info->board->irq ||
1248 new_serial.port != info->ioaddr)
1249 return -EINVAL;
1da177e4 1250
07f86c03 1251 flags = port->flags & ASYNC_SPD_MASK;
1da177e4 1252
1c45607a
JS		 1253 if (!capable(CAP_SYS_ADMIN)) {
1254 if ((new_serial.baud_base != info->baud_base) ||
44b7d1b3 1255 (new_serial.close_delay != info->port.close_delay) ||
0ad9e7d1 1256 ((new_serial.flags & ~ASYNC_USR_MASK) != (info->port.flags & ~ASYNC_USR_MASK)))
1c45607a 1257 return -EPERM;
0ad9e7d1 1258 info->port.flags = ((info->port.flags & ~ASYNC_USR_MASK) |
1c45607a
JS		 1259 (new_serial.flags & ASYNC_USR_MASK));
1260 } else {
1da177e4 1261 /*
1c45607a
JS		 1262 * OK, past this point, all the error checking has been done.
1263 * At this point, we start making changes.....
1da177e4 1264 */
07f86c03 1265 port->flags = ((port->flags & ~ASYNC_FLAGS) |
1c45607a 1266 (new_serial.flags & ASYNC_FLAGS));
07f86c03
AC		 1267 port->close_delay = new_serial.close_delay * HZ / 100;
1268 port->closing_wait = new_serial.closing_wait * HZ / 100;
1269 tty->low_latency = (port->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1270 if ((port->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST &&
80ff8a80
JS		 1271 (new_serial.baud_base != info->baud_base ||
1272 new_serial.custom_divisor !=
1273 info->custom_divisor)) {
07f86c03
AC		 1274 if (new_serial.custom_divisor == 0)
1275 return -EINVAL;
80ff8a80 1276 baud = new_serial.baud_base / new_serial.custom_divisor;
216ba023 1277 tty_encode_baud_rate(tty, baud, baud);
80ff8a80 1278 }
1c45607a 1279 }
fc83815c 1280
1c45607a 1281 info->type = new_serial.type;
1da177e4 1282
1c45607a
JS		 1283 process_txrx_fifo(info);
1284
07f86c03
AC		 1285 if (test_bit(ASYNCB_INITIALIZED, &port->flags)) {
1286 if (flags != (port->flags & ASYNC_SPD_MASK)) {
1c45607a 1287 spin_lock_irqsave(&info->slock, sl_flags);
216ba023 1288 mxser_change_speed(tty, NULL);
1c45607a 1289 spin_unlock_irqrestore(&info->slock, sl_flags);
1da177e4 1290 }
6769140d 1291 } else {
07f86c03 1292 retval = mxser_activate(port, tty);
6769140d 1293 if (retval == 0)
07f86c03 1294 set_bit(ASYNCB_INITIALIZED, &port->flags);
6769140d 1295 }
1c45607a
JS		 1296 return retval;
1297}
1da177e4 1298
1c45607a
JS		 1299/*
1300 * mxser_get_lsr_info - get line status register info
1301 *
1302 * Purpose: Let user call ioctl() to get info when the UART physically
1303 * is emptied. On bus types like RS485, the transmitter must
1304 * release the bus after transmitting. This must be done when
1305 * the transmit shift register is empty, not be done when the
1306 * transmit holding register is empty. This functionality
1307 * allows an RS485 driver to be written in user space.
1308 */
1309static int mxser_get_lsr_info(struct mxser_port *info,
1310 unsigned int __user *value)
1311{
1312 unsigned char status;
1313 unsigned int result;
1314 unsigned long flags;
1da177e4 1315
1c45607a
JS		 1316 spin_lock_irqsave(&info->slock, flags);
1317 status = inb(info->ioaddr + UART_LSR);
1318 spin_unlock_irqrestore(&info->slock, flags);
1319 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
1320 return put_user(result, value);
1321}
1da177e4 1322
60b33c13 1323static int mxser_tiocmget(struct tty_struct *tty)
1c45607a
JS		 1324{
1325 struct mxser_port *info = tty->driver_data;
1326 unsigned char control, status;
1327 unsigned long flags;
1da177e4 1328
8ea2c2ec 1329
1c45607a
JS		 1330 if (tty->index == MXSER_PORTS)
1331 return -ENOIOCTLCMD;
1332 if (test_bit(TTY_IO_ERROR, &tty->flags))
1333 return -EIO;
1da177e4 1334
1c45607a 1335 control = info->MCR;
1da177e4 1336
1c45607a
JS		 1337 spin_lock_irqsave(&info->slock, flags);
1338 status = inb(info->ioaddr + UART_MSR);
1339 if (status & UART_MSR_ANY_DELTA)
216ba023 1340 mxser_check_modem_status(tty, info, status);
1c45607a
JS		 1341 spin_unlock_irqrestore(&info->slock, flags);
1342 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
1343 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
1344 ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) |
1345 ((status & UART_MSR_RI) ? TIOCM_RNG : 0) |
1346 ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) |
1347 ((status & UART_MSR_CTS) ? TIOCM_CTS : 0);
1348}
1da177e4 1349
1c45607a
JS		 1350static int mxser_tiocmset(struct tty_struct *tty, struct file *file,
1351 unsigned int set, unsigned int clear)
1352{
1353 struct mxser_port *info = tty->driver_data;
1354 unsigned long flags;
1da177e4 1355
1da177e4 1356
1c45607a
JS		 1357 if (tty->index == MXSER_PORTS)
1358 return -ENOIOCTLCMD;
1359 if (test_bit(TTY_IO_ERROR, &tty->flags))
1360 return -EIO;
1da177e4 1361
1c45607a 1362 spin_lock_irqsave(&info->slock, flags);
1da177e4 1363
1c45607a
JS		 1364 if (set & TIOCM_RTS)
1365 info->MCR |= UART_MCR_RTS;
1366 if (set & TIOCM_DTR)
1367 info->MCR |= UART_MCR_DTR;
1da177e4 1368
1c45607a
JS		 1369 if (clear & TIOCM_RTS)
1370 info->MCR &= ~UART_MCR_RTS;
1371 if (clear & TIOCM_DTR)
1372 info->MCR &= ~UART_MCR_DTR;
8ea2c2ec 1373
1c45607a
JS		 1374 outb(info->MCR, info->ioaddr + UART_MCR);
1375 spin_unlock_irqrestore(&info->slock, flags);
1376 return 0;
1377}
1da177e4 1378
1c45607a
JS		 1379static int __init mxser_program_mode(int port)
1380{
1381 int id, i, j, n;
1382
1383 outb(0, port);
1384 outb(0, port);
1385 outb(0, port);
1386 (void)inb(port);
1387 (void)inb(port);
1388 outb(0, port);
1389 (void)inb(port);
1390
1391 id = inb(port + 1) & 0x1F;
1392 if ((id != C168_ASIC_ID) &&
1393 (id != C104_ASIC_ID) &&
1394 (id != C102_ASIC_ID) &&
1395 (id != CI132_ASIC_ID) &&
1396 (id != CI134_ASIC_ID) &&
1397 (id != CI104J_ASIC_ID))
1398 return -1;
1399 for (i = 0, j = 0; i < 4; i++) {
1400 n = inb(port + 2);
1401 if (n == 'M') {
1402 j = 1;
1403 } else if ((j == 1) && (n == 1)) {
1404 j = 2;
1405 break;
1406 } else
1407 j = 0;
1da177e4 1408 }
1c45607a
JS		 1409 if (j != 2)
1410 id = -2;
1411 return id;
1da177e4
LT		 1412}
1413
1c45607a
JS		 1414static void __init mxser_normal_mode(int port)
1415{
1416 int i, n;
1417
1418 outb(0xA5, port + 1);
1419 outb(0x80, port + 3);
1420 outb(12, port + 0); /* 9600 bps */
1421 outb(0, port + 1);
1422 outb(0x03, port + 3); /* 8 data bits */
1423 outb(0x13, port + 4); /* loop back mode */
1424 for (i = 0; i < 16; i++) {
1425 n = inb(port + 5);
1426 if ((n & 0x61) == 0x60)
1427 break;
1428 if ((n & 1) == 1)
1429 (void)inb(port);
1430 }
1431 outb(0x00, port + 4);
1432}
1433
1434#define CHIP_SK 0x01 /* Serial Data Clock in Eprom */
1435#define CHIP_DO 0x02 /* Serial Data Output in Eprom */
1436#define CHIP_CS 0x04 /* Serial Chip Select in Eprom */
1437#define CHIP_DI 0x08 /* Serial Data Input in Eprom */
1438#define EN_CCMD 0x000 /* Chip's command register */
1439#define EN0_RSARLO 0x008 /* Remote start address reg 0 */
1440#define EN0_RSARHI 0x009 /* Remote start address reg 1 */
1441#define EN0_RCNTLO 0x00A /* Remote byte count reg WR */
1442#define EN0_RCNTHI 0x00B /* Remote byte count reg WR */
1443#define EN0_DCFG 0x00E /* Data configuration reg WR */
1444#define EN0_PORT 0x010 /* Rcv missed frame error counter RD */
1445#define ENC_PAGE0 0x000 /* Select page 0 of chip registers */
1446#define ENC_PAGE3 0x0C0 /* Select page 3 of chip registers */
1447static int __init mxser_read_register(int port, unsigned short *regs)
1448{
1449 int i, k, value, id;
1450 unsigned int j;
1451
1452 id = mxser_program_mode(port);
1453 if (id < 0)
1454 return id;
1455 for (i = 0; i < 14; i++) {
1456 k = (i & 0x3F) | 0x180;
1457 for (j = 0x100; j > 0; j >>= 1) {
1458 outb(CHIP_CS, port);
1459 if (k & j) {
1460 outb(CHIP_CS | CHIP_DO, port);
1461 outb(CHIP_CS | CHIP_DO | CHIP_SK, port); /* A? bit of read */
1462 } else {
1463 outb(CHIP_CS, port);
1464 outb(CHIP_CS | CHIP_SK, port); /* A? bit of read */
1465 }
1466 }
1467 (void)inb(port);
1468 value = 0;
1469 for (k = 0, j = 0x8000; k < 16; k++, j >>= 1) {
1470 outb(CHIP_CS, port);
1471 outb(CHIP_CS | CHIP_SK, port);
1472 if (inb(port) & CHIP_DI)
1473 value |= j;
1474 }
1475 regs[i] = value;
1476 outb(0, port);
1477 }
1478 mxser_normal_mode(port);
1479 return id;
1480}
1da177e4
LT		 1481
1482static int mxser_ioctl_special(unsigned int cmd, void __user *argp)
1483{
07f86c03
AC		 1484 struct mxser_port *ip;
1485 struct tty_port *port;
216ba023 1486 struct tty_struct *tty;
1c45607a
JS		 1487 int result, status;
1488 unsigned int i, j;
9d6d162d 1489 int ret = 0;
1da177e4
LT		 1490
1491 switch (cmd) {
1da177e4 1492 case MOXA_GET_MAJOR:
8f3d137e
JS		 1493 if (printk_ratelimit())
1494 printk(KERN_WARNING "mxser: '%s' uses deprecated ioctl "
1495 "%x (GET_MAJOR), fix your userspace\n",
1496 current->comm, cmd);
1c45607a 1497 return put_user(ttymajor, (int __user *)argp);
1da177e4
LT		 1498
1499 case MOXA_CHKPORTENABLE:
1500 result = 0;
1c45607a
JS		 1501 for (i = 0; i < MXSER_BOARDS; i++)
1502 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++)
1503 if (mxser_boards[i].ports[j].ioaddr)
1504 result |= (1 << i);
8ea2c2ec 1505 return put_user(result, (unsigned long __user *)argp);
1da177e4 1506 case MOXA_GETDATACOUNT:
07f86c03
AC		 1507 /* The receive side is locked by port->slock but it isn't
1508 clear that an exact snapshot is worth copying here */
1da177e4 1509 if (copy_to_user(argp, &mxvar_log, sizeof(mxvar_log)))
9d6d162d 1510 ret = -EFAULT;
9d6d162d 1511 return ret;
72800df9
JS		 1512 case MOXA_GETMSTATUS: {
1513 struct mxser_mstatus ms, __user *msu = argp;
1c45607a
JS		 1514 for (i = 0; i < MXSER_BOARDS; i++)
1515 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) {
07f86c03
AC		 1516 ip = &mxser_boards[i].ports[j];
1517 port = &ip->port;
72800df9 1518 memset(&ms, 0, sizeof(ms));
1c45607a 1519
07f86c03
AC		 1520 mutex_lock(&port->mutex);
1521 if (!ip->ioaddr)
72800df9 1522 goto copy;
216ba023 1523
07f86c03 1524 tty = tty_port_tty_get(port);
1da177e4 1525
216ba023 1526 if (!tty || !tty->termios)
07f86c03 1527 ms.cflag = ip->normal_termios.c_cflag;
1c45607a 1528 else
216ba023
AC		 1529 ms.cflag = tty->termios->c_cflag;
1530 tty_kref_put(tty);
07f86c03
AC		 1531 spin_lock_irq(&ip->slock);
1532 status = inb(ip->ioaddr + UART_MSR);
1533 spin_unlock_irq(&ip->slock);
72800df9
JS		 1534 if (status & UART_MSR_DCD)
1535 ms.dcd = 1;
1536 if (status & UART_MSR_DSR)
1537 ms.dsr = 1;
1538 if (status & UART_MSR_CTS)
1539 ms.cts = 1;
1540 copy:
07f86c03
AC		 1541 mutex_unlock(&port->mutex);
1542 if (copy_to_user(msu, &ms, sizeof(ms)))
72800df9 1543 return -EFAULT;
72800df9 1544 msu++;
1c45607a 1545 }
1da177e4 1546 return 0;
72800df9 1547 }
8ea2c2ec 1548 case MOXA_ASPP_MON_EXT: {
72800df9
JS		 1549 struct mxser_mon_ext *me; /* it's 2k, stack unfriendly */
1550 unsigned int cflag, iflag, p;
1551 u8 opmode;
1552
1553 me = kzalloc(sizeof(*me), GFP_KERNEL);
1554 if (!me)
1555 return -ENOMEM;
1c45607a 1556
72800df9
JS		 1557 for (i = 0, p = 0; i < MXSER_BOARDS; i++) {
1558 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++, p++) {
1559 if (p >= ARRAY_SIZE(me->rx_cnt)) {
1560 i = MXSER_BOARDS;
1561 break;
1562 }
07f86c03
AC		 1563 ip = &mxser_boards[i].ports[j];
1564 port = &ip->port;
1565
1566 mutex_lock(&port->mutex);
1567 if (!ip->ioaddr) {
1568 mutex_unlock(&port->mutex);
1da177e4 1569 continue;
07f86c03 1570 }
1da177e4 1571
07f86c03
AC		 1572 spin_lock_irq(&ip->slock);
1573 status = mxser_get_msr(ip->ioaddr, 0, p);
1c45607a 1574
1da177e4 1575 if (status & UART_MSR_TERI)
07f86c03 1576 ip->icount.rng++;
1da177e4 1577 if (status & UART_MSR_DDSR)
07f86c03 1578 ip->icount.dsr++;
1da177e4 1579 if (status & UART_MSR_DDCD)
07f86c03 1580 ip->icount.dcd++;
1da177e4 1581 if (status & UART_MSR_DCTS)
07f86c03 1582 ip->icount.cts++;
1c45607a 1583
07f86c03
AC		 1584 ip->mon_data.modem_status = status;
1585 me->rx_cnt[p] = ip->mon_data.rxcnt;
1586 me->tx_cnt[p] = ip->mon_data.txcnt;
1587 me->up_rxcnt[p] = ip->mon_data.up_rxcnt;
1588 me->up_txcnt[p] = ip->mon_data.up_txcnt;
72800df9 1589 me->modem_status[p] =
07f86c03
AC		 1590 ip->mon_data.modem_status;
1591 spin_unlock_irq(&ip->slock);
1592
1593 tty = tty_port_tty_get(&ip->port);
1c45607a 1594
216ba023 1595 if (!tty || !tty->termios) {
07f86c03
AC		 1596 cflag = ip->normal_termios.c_cflag;
1597 iflag = ip->normal_termios.c_iflag;
1598 me->baudrate[p] = tty_termios_baud_rate(&ip->normal_termios);
1da177e4 1599 } else {
216ba023
AC		 1600 cflag = tty->termios->c_cflag;
1601 iflag = tty->termios->c_iflag;
1602 me->baudrate[p] = tty_get_baud_rate(tty);
1da177e4 1603 }
216ba023 1604 tty_kref_put(tty);
1da177e4 1605
72800df9
JS		 1606 me->databits[p] = cflag & CSIZE;
1607 me->stopbits[p] = cflag & CSTOPB;
1608 me->parity[p] = cflag & (PARENB | PARODD |
1609 CMSPAR);
1da177e4
LT		 1610
1611 if (cflag & CRTSCTS)
72800df9 1612 me->flowctrl[p] |= 0x03;
1da177e4
LT		 1613
1614 if (iflag & (IXON | IXOFF))
72800df9 1615 me->flowctrl[p] |= 0x0C;
1da177e4 1616
07f86c03 1617 if (ip->type == PORT_16550A)
72800df9 1618 me->fifo[p] = 1;
1da177e4 1619
07f86c03 1620 opmode = inb(ip->opmode_ioaddr)>>((p % 4) * 2);
1da177e4 1621 opmode &= OP_MODE_MASK;
72800df9 1622 me->iftype[p] = opmode;
07f86c03 1623 mutex_unlock(&port->mutex);
1da177e4 1624 }
9d6d162d 1625 }
72800df9
JS		 1626 if (copy_to_user(argp, me, sizeof(*me)))
1627 ret = -EFAULT;
1628 kfree(me);
1629 return ret;
9d6d162d
AC		 1630 }
1631 default:
1da177e4
LT		 1632 return -ENOIOCTLCMD;
1633 }
1634 return 0;
1635}
1636
1c45607a
JS		 1637static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg,
1638 struct async_icount *cprev)
1da177e4 1639{
1c45607a
JS		 1640 struct async_icount cnow;
1641 unsigned long flags;
1642 int ret;
1da177e4 1643
1c45607a
JS		 1644 spin_lock_irqsave(&info->slock, flags);
1645 cnow = info->icount; /* atomic copy */
1646 spin_unlock_irqrestore(&info->slock, flags);
1da177e4 1647
1c45607a
JS		 1648 ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) ||
1649 ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) ||
1650 ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) ||
1651 ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts));
1da177e4 1652
1c45607a
JS		 1653 *cprev = cnow;
1654
1655 return ret;
1656}
1657
1658static int mxser_ioctl(struct tty_struct *tty, struct file *file,
1659 unsigned int cmd, unsigned long arg)
1da177e4 1660{
1c45607a 1661 struct mxser_port *info = tty->driver_data;
07f86c03 1662 struct tty_port *port = &info->port;
1c45607a 1663 struct async_icount cnow;
1c45607a
JS		 1664 unsigned long flags;
1665 void __user *argp = (void __user *)arg;
1666 int retval;
1da177e4 1667
1c45607a
JS		 1668 if (tty->index == MXSER_PORTS)
1669 return mxser_ioctl_special(cmd, argp);
1da177e4 1670
1c45607a
JS		 1671 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) {
1672 int p;
1673 unsigned long opmode;
1674 static unsigned char ModeMask[] = { 0xfc, 0xf3, 0xcf, 0x3f };
1675 int shiftbit;
1676 unsigned char val, mask;
1da177e4 1677
1c45607a
JS		 1678 p = tty->index % 4;
1679 if (cmd == MOXA_SET_OP_MODE) {
1680 if (get_user(opmode, (int __user *) argp))
1681 return -EFAULT;
1682 if (opmode != RS232_MODE &&
1683 opmode != RS485_2WIRE_MODE &&
1684 opmode != RS422_MODE &&
1685 opmode != RS485_4WIRE_MODE)
1686 return -EFAULT;
1687 mask = ModeMask[p];
1688 shiftbit = p * 2;
07f86c03 1689 spin_lock_irq(&info->slock);
1c45607a
JS		 1690 val = inb(info->opmode_ioaddr);
1691 val &= mask;
1692 val |= (opmode << shiftbit);
1693 outb(val, info->opmode_ioaddr);
07f86c03 1694 spin_unlock_irq(&info->slock);
1c45607a
JS		 1695 } else {
1696 shiftbit = p * 2;
07f86c03 1697 spin_lock_irq(&info->slock);
1c45607a 1698 opmode = inb(info->opmode_ioaddr) >> shiftbit;
07f86c03 1699 spin_unlock_irq(&info->slock);
1c45607a
JS		 1700 opmode &= OP_MODE_MASK;
1701 if (put_user(opmode, (int __user *)argp))
1702 return -EFAULT;
1703 }
1704 return 0;
1705 }
1706
0587102c 1707 if (cmd != TIOCGSERIAL && cmd != TIOCMIWAIT &&
1c45607a
JS		 1708 test_bit(TTY_IO_ERROR, &tty->flags))
1709 return -EIO;
1710
1711 switch (cmd) {
1c45607a 1712 case TIOCGSERIAL:
07f86c03 1713 mutex_lock(&port->mutex);
216ba023 1714 retval = mxser_get_serial_info(tty, argp);
07f86c03 1715 mutex_unlock(&port->mutex);
9d6d162d 1716 return retval;
1c45607a 1717 case TIOCSSERIAL:
07f86c03 1718 mutex_lock(&port->mutex);
216ba023 1719 retval = mxser_set_serial_info(tty, argp);
07f86c03 1720 mutex_unlock(&port->mutex);
9d6d162d 1721 return retval;
1c45607a 1722 case TIOCSERGETLSR: /* Get line status register */
9d6d162d 1723 return mxser_get_lsr_info(info, argp);
1c45607a
JS		 1724 /*
1725 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
1726 * - mask passed in arg for lines of interest
1727 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
1728 * Caller should use TIOCGICOUNT to see which one it was
1729 */
1730 case TIOCMIWAIT:
1731 spin_lock_irqsave(&info->slock, flags);
1732 cnow = info->icount; /* note the counters on entry */
1733 spin_unlock_irqrestore(&info->slock, flags);
1734
bdc04e31 1735 return wait_event_interruptible(info->port.delta_msr_wait,
1c45607a 1736 mxser_cflags_changed(info, arg, &cnow));
1c45607a
JS		 1737 case MOXA_HighSpeedOn:
1738 return put_user(info->baud_base != 115200 ? 1 : 0, (int __user *)argp);
1739 case MOXA_SDS_RSTICOUNTER:
07f86c03 1740 spin_lock_irq(&info->slock);
1c45607a
JS		 1741 info->mon_data.rxcnt = 0;
1742 info->mon_data.txcnt = 0;
07f86c03 1743 spin_unlock_irq(&info->slock);
1c45607a
JS		 1744 return 0;
1745
1746 case MOXA_ASPP_OQUEUE:{
1747 int len, lsr;
1748
1749 len = mxser_chars_in_buffer(tty);
c6eb69ac 1750 spin_lock_irq(&info->slock);
a75b7b68 1751 lsr = inb(info->ioaddr + UART_LSR) & UART_LSR_THRE;
07f86c03 1752 spin_unlock_irq(&info->slock);
1c45607a
JS		 1753 len += (lsr ? 0 : 1);
1754
1755 return put_user(len, (int __user *)argp);
1756 }
1757 case MOXA_ASPP_MON: {
1758 int mcr, status;
1759
c6eb69ac 1760 spin_lock_irq(&info->slock);
1c45607a 1761 status = mxser_get_msr(info->ioaddr, 1, tty->index);
216ba023 1762 mxser_check_modem_status(tty, info, status);
1c45607a
JS		 1763
1764 mcr = inb(info->ioaddr + UART_MCR);
c6eb69ac 1765 spin_unlock_irq(&info->slock);
07f86c03 1766
1c45607a
JS		 1767 if (mcr & MOXA_MUST_MCR_XON_FLAG)
1768 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFHOLD;
1769 else
1770 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFHOLD;
1771
1772 if (mcr & MOXA_MUST_MCR_TX_XON)
1773 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFXENT;
1774 else
1775 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFXENT;
1776
216ba023 1777 if (tty->hw_stopped)
1c45607a
JS		 1778 info->mon_data.hold_reason |= NPPI_NOTIFY_CTSHOLD;
1779 else
1780 info->mon_data.hold_reason &= ~NPPI_NOTIFY_CTSHOLD;
07f86c03 1781
1c45607a
JS		 1782 if (copy_to_user(argp, &info->mon_data,
1783 sizeof(struct mxser_mon)))
1784 return -EFAULT;
1785
1786 return 0;
1787 }
1788 case MOXA_ASPP_LSTATUS: {
1789 if (put_user(info->err_shadow, (unsigned char __user *)argp))
1790 return -EFAULT;
1791
1792 info->err_shadow = 0;
1793 return 0;
1794 }
1795 case MOXA_SET_BAUD_METHOD: {
1796 int method;
1797
1798 if (get_user(method, (int __user *)argp))
1799 return -EFAULT;
1800 mxser_set_baud_method[tty->index] = method;
1801 return put_user(method, (int __user *)argp);
1802 }
1803 default:
1804 return -ENOIOCTLCMD;
1805 }
1806 return 0;
1807}
1808
0587102c
AC		 1809 /*
1810 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1811 * Return: write counters to the user passed counter struct
1812 * NB: both 1->0 and 0->1 transitions are counted except for
1813 * RI where only 0->1 is counted.
1814 */
1815
1816static int mxser_get_icount(struct tty_struct *tty,
1817 struct serial_icounter_struct *icount)
1818
1819{
1820 struct mxser_port *info = tty->driver_data;
1821 struct async_icount cnow;
1822 unsigned long flags;
1823
1824 spin_lock_irqsave(&info->slock, flags);
1825 cnow = info->icount;
1826 spin_unlock_irqrestore(&info->slock, flags);
1827
1828 icount->frame = cnow.frame;
1829 icount->brk = cnow.brk;
1830 icount->overrun = cnow.overrun;
1831 icount->buf_overrun = cnow.buf_overrun;
1832 icount->parity = cnow.parity;
1833 icount->rx = cnow.rx;
1834 icount->tx = cnow.tx;
1835 icount->cts = cnow.cts;
1836 icount->dsr = cnow.dsr;
1837 icount->rng = cnow.rng;
1838 icount->dcd = cnow.dcd;
1839 return 0;
1840}
1841
1c45607a
JS		 1842static void mxser_stoprx(struct tty_struct *tty)
1843{
1844 struct mxser_port *info = tty->driver_data;
1845
1846 info->ldisc_stop_rx = 1;
1847 if (I_IXOFF(tty)) {
1848 if (info->board->chip_flag) {
1849 info->IER &= ~MOXA_MUST_RECV_ISR;
1850 outb(info->IER, info->ioaddr + UART_IER);
1851 } else {
1852 info->x_char = STOP_CHAR(tty);
1853 outb(0, info->ioaddr + UART_IER);
1854 info->IER |= UART_IER_THRI;
1855 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1856 }
1857 }
1858
216ba023 1859 if (tty->termios->c_cflag & CRTSCTS) {
1c45607a
JS		 1860 info->MCR &= ~UART_MCR_RTS;
1861 outb(info->MCR, info->ioaddr + UART_MCR);
1da177e4
LT		 1862 }
1863}
1864
1865/*
1866 * This routine is called by the upper-layer tty layer to signal that
1867 * incoming characters should be throttled.
1868 */
1869static void mxser_throttle(struct tty_struct *tty)
1870{
1da177e4 1871 mxser_stoprx(tty);
1da177e4
LT		 1872}
1873
1874static void mxser_unthrottle(struct tty_struct *tty)
1875{
1c45607a 1876 struct mxser_port *info = tty->driver_data;
1da177e4 1877
1c45607a
JS		 1878 /* startrx */
1879 info->ldisc_stop_rx = 0;
1880 if (I_IXOFF(tty)) {
1881 if (info->x_char)
1882 info->x_char = 0;
1883 else {
1884 if (info->board->chip_flag) {
1885 info->IER |= MOXA_MUST_RECV_ISR;
1886 outb(info->IER, info->ioaddr + UART_IER);
1887 } else {
1888 info->x_char = START_CHAR(tty);
1889 outb(0, info->ioaddr + UART_IER);
1890 info->IER |= UART_IER_THRI;
1891 outb(info->IER, info->ioaddr + UART_IER);
1892 }
1da177e4 1893 }
1c45607a 1894 }
1da177e4 1895
216ba023 1896 if (tty->termios->c_cflag & CRTSCTS) {
1c45607a
JS		 1897 info->MCR |= UART_MCR_RTS;
1898 outb(info->MCR, info->ioaddr + UART_MCR);
1da177e4
LT		 1899 }
1900}
1901
1902/*
1903 * mxser_stop() and mxser_start()
1904 *
1905 * This routines are called before setting or resetting tty->stopped.
1906 * They enable or disable transmitter interrupts, as necessary.
1907 */
1908static void mxser_stop(struct tty_struct *tty)
1909{
1c45607a 1910 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1911 unsigned long flags;
1912
1913 spin_lock_irqsave(&info->slock, flags);
1914 if (info->IER & UART_IER_THRI) {
1915 info->IER &= ~UART_IER_THRI;
1c45607a 1916 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1917 }
1918 spin_unlock_irqrestore(&info->slock, flags);
1919}
1920
1921static void mxser_start(struct tty_struct *tty)
1922{
1c45607a 1923 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1924 unsigned long flags;
1925
1926 spin_lock_irqsave(&info->slock, flags);
0ad9e7d1 1927 if (info->xmit_cnt && info->port.xmit_buf) {
1c45607a 1928 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1da177e4 1929 info->IER |= UART_IER_THRI;
1c45607a 1930 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1931 }
1932 spin_unlock_irqrestore(&info->slock, flags);
1933}
1934
1c45607a
JS		 1935static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1936{
1937 struct mxser_port *info = tty->driver_data;
1938 unsigned long flags;
1939
1940 spin_lock_irqsave(&info->slock, flags);
216ba023 1941 mxser_change_speed(tty, old_termios);
1c45607a
JS		 1942 spin_unlock_irqrestore(&info->slock, flags);
1943
1944 if ((old_termios->c_cflag & CRTSCTS) &&
1945 !(tty->termios->c_cflag & CRTSCTS)) {
1946 tty->hw_stopped = 0;
1947 mxser_start(tty);
1948 }
1949
1950 /* Handle sw stopped */
1951 if ((old_termios->c_iflag & IXON) &&
1952 !(tty->termios->c_iflag & IXON)) {
1953 tty->stopped = 0;
1954
1955 if (info->board->chip_flag) {
1956 spin_lock_irqsave(&info->slock, flags);
148ff86b
CH		 1957 mxser_disable_must_rx_software_flow_control(
1958 info->ioaddr);
1c45607a
JS		 1959 spin_unlock_irqrestore(&info->slock, flags);
1960 }
1961
1962 mxser_start(tty);
1963 }
1964}
1965
1da177e4
LT		 1966/*
1967 * mxser_wait_until_sent() --- wait until the transmitter is empty
1968 */
1969static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
1970{
1c45607a 1971 struct mxser_port *info = tty->driver_data;
1da177e4 1972 unsigned long orig_jiffies, char_time;
07f86c03 1973 unsigned long flags;
1da177e4
LT		 1974 int lsr;
1975
1976 if (info->type == PORT_UNKNOWN)
1977 return;
1978
1979 if (info->xmit_fifo_size == 0)
1980 return; /* Just in case.... */
1981
1982 orig_jiffies = jiffies;
1983 /*
1984 * Set the check interval to be 1/5 of the estimated time to
1985 * send a single character, and make it at least 1. The check
1986 * interval should also be less than the timeout.
1987 *
1988 * Note: we have to use pretty tight timings here to satisfy
1989 * the NIST-PCTS.
1990 */
1991 char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size;
1992 char_time = char_time / 5;
1993 if (char_time == 0)
1994 char_time = 1;
1995 if (timeout && timeout < char_time)
1996 char_time = timeout;
1997 /*
1998 * If the transmitter hasn't cleared in twice the approximate
1999 * amount of time to send the entire FIFO, it probably won't
2000 * ever clear. This assumes the UART isn't doing flow
2001 * control, which is currently the case. Hence, if it ever
2002 * takes longer than info->timeout, this is probably due to a
2003 * UART bug of some kind. So, we clamp the timeout parameter at
2004 * 2*info->timeout.
2005 */
2006 if (!timeout || timeout > 2 * info->timeout)
2007 timeout = 2 * info->timeout;
2008#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
8ea2c2ec
JJ		 2009 printk(KERN_DEBUG "In rs_wait_until_sent(%d) check=%lu...",
2010 timeout, char_time);
1da177e4
LT		 2011 printk("jiff=%lu...", jiffies);
2012#endif
07f86c03 2013 spin_lock_irqsave(&info->slock, flags);
1c45607a 2014 while (!((lsr = inb(info->ioaddr + UART_LSR)) & UART_LSR_TEMT)) {
1da177e4
LT		 2015#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
2016 printk("lsr = %d (jiff=%lu)...", lsr, jiffies);
2017#endif
07f86c03 2018 spin_unlock_irqrestore(&info->slock, flags);
da4cd8df 2019 schedule_timeout_interruptible(char_time);
07f86c03 2020 spin_lock_irqsave(&info->slock, flags);
1da177e4 2021 if (signal_pending(current))
1c45607a
JS		 2022 break;
2023 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2024 break;
1da177e4 2025 }
07f86c03 2026 spin_unlock_irqrestore(&info->slock, flags);
1c45607a 2027 set_current_state(TASK_RUNNING);
1da177e4 2028
1c45607a
JS		 2029#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
2030 printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies);
2031#endif
2032}
1da177e4 2033
1c45607a
JS		 2034/*
2035 * This routine is called by tty_hangup() when a hangup is signaled.
2036 */
2037static void mxser_hangup(struct tty_struct *tty)
2038{
2039 struct mxser_port *info = tty->driver_data;
1da177e4 2040
1c45607a 2041 mxser_flush_buffer(tty);
3b6826b2 2042 tty_port_hangup(&info->port);
1da177e4
LT		 2043}
2044
1c45607a
JS		 2045/*
2046 * mxser_rs_break() --- routine which turns the break handling on or off
2047 */
9e98966c 2048static int mxser_rs_break(struct tty_struct *tty, int break_state)
1da177e4 2049{
1c45607a 2050 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 2051 unsigned long flags;
2052
1c45607a
JS		 2053 spin_lock_irqsave(&info->slock, flags);
2054 if (break_state == -1)
2055 outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC,
2056 info->ioaddr + UART_LCR);
2057 else
2058 outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC,
2059 info->ioaddr + UART_LCR);
2060 spin_unlock_irqrestore(&info->slock, flags);
9e98966c 2061 return 0;
1c45607a 2062}
1da177e4 2063
216ba023
AC		 2064static void mxser_receive_chars(struct tty_struct *tty,
2065 struct mxser_port *port, int *status)
1c45607a 2066{
1c45607a
JS		 2067 unsigned char ch, gdl;
2068 int ignored = 0;
2069 int cnt = 0;
2070 int recv_room;
2071 int max = 256;
1da177e4 2072
1c45607a 2073 recv_room = tty->receive_room;
216ba023 2074 if (recv_room == 0 && !port->ldisc_stop_rx)
1c45607a 2075 mxser_stoprx(tty);
1c45607a 2076 if (port->board->chip_flag != MOXA_OTHER_UART) {
1da177e4 2077
1c45607a
JS		 2078 if (*status & UART_LSR_SPECIAL)
2079 goto intr_old;
2080 if (port->board->chip_flag == MOXA_MUST_MU860_HWID &&
2081 (*status & MOXA_MUST_LSR_RERR))
2082 goto intr_old;
2083 if (*status & MOXA_MUST_LSR_RERR)
2084 goto intr_old;
1da177e4 2085
1c45607a
JS		 2086 gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER);
2087
2088 if (port->board->chip_flag == MOXA_MUST_MU150_HWID)
2089 gdl &= MOXA_MUST_GDL_MASK;
2090 if (gdl >= recv_room) {
2091 if (!port->ldisc_stop_rx)
2092 mxser_stoprx(tty);
2093 }
2094 while (gdl--) {
2095 ch = inb(port->ioaddr + UART_RX);
2096 tty_insert_flip_char(tty, ch, 0);
2097 cnt++;
2098 }
2099 goto end_intr;
1da177e4 2100 }
1c45607a
JS		 2101intr_old:
2102
2103 do {
2104 if (max-- < 0)
2105 break;
1da177e4 2106
1c45607a
JS		 2107 ch = inb(port->ioaddr + UART_RX);
2108 if (port->board->chip_flag && (*status & UART_LSR_OE))
2109 outb(0x23, port->ioaddr + UART_FCR);
2110 *status &= port->read_status_mask;
2111 if (*status & port->ignore_status_mask) {
2112 if (++ignored > 100)
2113 break;
2114 } else {
2115 char flag = 0;
2116 if (*status & UART_LSR_SPECIAL) {
2117 if (*status & UART_LSR_BI) {
2118 flag = TTY_BREAK;
2119 port->icount.brk++;
1da177e4 2120
0ad9e7d1 2121 if (port->port.flags & ASYNC_SAK)
1c45607a
JS		 2122 do_SAK(tty);
2123 } else if (*status & UART_LSR_PE) {
2124 flag = TTY_PARITY;
2125 port->icount.parity++;
2126 } else if (*status & UART_LSR_FE) {
2127 flag = TTY_FRAME;
2128 port->icount.frame++;
2129 } else if (*status & UART_LSR_OE) {
2130 flag = TTY_OVERRUN;
2131 port->icount.overrun++;
2132 } else
2133 flag = TTY_BREAK;
2134 }
2135 tty_insert_flip_char(tty, ch, flag);
2136 cnt++;
2137 if (cnt >= recv_room) {
2138 if (!port->ldisc_stop_rx)
2139 mxser_stoprx(tty);
2140 break;
2141 }
1da177e4 2142
1c45607a 2143 }
1da177e4 2144
1c45607a
JS		 2145 if (port->board->chip_flag)
2146 break;
1da177e4 2147
1c45607a
JS		 2148 *status = inb(port->ioaddr + UART_LSR);
2149 } while (*status & UART_LSR_DR);
1da177e4 2150
1c45607a 2151end_intr:
216ba023 2152 mxvar_log.rxcnt[tty->index] += cnt;
1c45607a
JS		 2153 port->mon_data.rxcnt += cnt;
2154 port->mon_data.up_rxcnt += cnt;
1da177e4 2155
1c45607a
JS		 2156 /*
2157 * We are called from an interrupt context with &port->slock
2158 * being held. Drop it temporarily in order to prevent
2159 * recursive locking.
2160 */
2161 spin_unlock(&port->slock);
2162 tty_flip_buffer_push(tty);
2163 spin_lock(&port->slock);
1da177e4
LT		 2164}
2165
216ba023 2166static void mxser_transmit_chars(struct tty_struct *tty, struct mxser_port *port)
1da177e4 2167{
1c45607a 2168 int count, cnt;
1da177e4 2169
1c45607a
JS		 2170 if (port->x_char) {
2171 outb(port->x_char, port->ioaddr + UART_TX);
2172 port->x_char = 0;
216ba023 2173 mxvar_log.txcnt[tty->index]++;
1c45607a
JS		 2174 port->mon_data.txcnt++;
2175 port->mon_data.up_txcnt++;
2176 port->icount.tx++;
2177 return;
2178 }
1da177e4 2179
0ad9e7d1 2180 if (port->port.xmit_buf == NULL)
1c45607a 2181 return;
1da177e4 2182
216ba023
AC		 2183 if (port->xmit_cnt <= 0 || tty->stopped ||
2184 (tty->hw_stopped &&
1c45607a
JS		 2185 (port->type != PORT_16550A) &&
2186 (!port->board->chip_flag))) {
2187 port->IER &= ~UART_IER_THRI;
2188 outb(port->IER, port->ioaddr + UART_IER);
2189 return;
1da177e4
LT		 2190 }
2191
1c45607a
JS		 2192 cnt = port->xmit_cnt;
2193 count = port->xmit_fifo_size;
2194 do {
0ad9e7d1 2195 outb(port->port.xmit_buf[port->xmit_tail++],
1c45607a
JS		 2196 port->ioaddr + UART_TX);
2197 port->xmit_tail = port->xmit_tail & (SERIAL_XMIT_SIZE - 1);
2198 if (--port->xmit_cnt <= 0)
2199 break;
2200 } while (--count > 0);
216ba023 2201 mxvar_log.txcnt[tty->index] += (cnt - port->xmit_cnt);
1da177e4 2202
1c45607a
JS		 2203 port->mon_data.txcnt += (cnt - port->xmit_cnt);
2204 port->mon_data.up_txcnt += (cnt - port->xmit_cnt);
2205 port->icount.tx += (cnt - port->xmit_cnt);
1da177e4 2206
464eb8f5 2207 if (port->xmit_cnt < WAKEUP_CHARS)
216ba023 2208 tty_wakeup(tty);
1c45607a
JS		 2209
2210 if (port->xmit_cnt <= 0) {
2211 port->IER &= ~UART_IER_THRI;
2212 outb(port->IER, port->ioaddr + UART_IER);
1da177e4 2213 }
1da177e4
LT		 2214}
2215
2216/*
1c45607a 2217 * This is the serial driver's generic interrupt routine
1da177e4 2218 */
1c45607a 2219static irqreturn_t mxser_interrupt(int irq, void *dev_id)
1da177e4 2220{
1c45607a
JS		 2221 int status, iir, i;
2222 struct mxser_board *brd = NULL;
2223 struct mxser_port *port;
2224 int max, irqbits, bits, msr;
2225 unsigned int int_cnt, pass_counter = 0;
2226 int handled = IRQ_NONE;
216ba023 2227 struct tty_struct *tty;
1da177e4 2228
1c45607a
JS		 2229 for (i = 0; i < MXSER_BOARDS; i++)
2230 if (dev_id == &mxser_boards[i]) {
2231 brd = dev_id;
2232 break;
2233 }
1da177e4 2234
1c45607a
JS		 2235 if (i == MXSER_BOARDS)
2236 goto irq_stop;
2237 if (brd == NULL)
2238 goto irq_stop;
2239 max = brd->info->nports;
2240 while (pass_counter++ < MXSER_ISR_PASS_LIMIT) {
2241 irqbits = inb(brd->vector) & brd->vector_mask;
2242 if (irqbits == brd->vector_mask)
2243 break;
1da177e4 2244
1c45607a
JS		 2245 handled = IRQ_HANDLED;
2246 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) {
2247 if (irqbits == brd->vector_mask)
2248 break;
2249 if (bits & irqbits)
2250 continue;
2251 port = &brd->ports[i];
2252
2253 int_cnt = 0;
2254 spin_lock(&port->slock);
2255 do {
2256 iir = inb(port->ioaddr + UART_IIR);
2257 if (iir & UART_IIR_NO_INT)
2258 break;
2259 iir &= MOXA_MUST_IIR_MASK;
216ba023
AC		 2260 tty = tty_port_tty_get(&port->port);
2261 if (!tty ||
0ad9e7d1
AC		 2262 (port->port.flags & ASYNC_CLOSING) ||
2263 !(port->port.flags &
1c45607a
JS		 2264 ASYNC_INITIALIZED)) {
2265 status = inb(port->ioaddr + UART_LSR);
2266 outb(0x27, port->ioaddr + UART_FCR);
2267 inb(port->ioaddr + UART_MSR);
216ba023 2268 tty_kref_put(tty);
1c45607a
JS		 2269 break;
2270 }
1da177e4 2271
1c45607a
JS		 2272 status = inb(port->ioaddr + UART_LSR);
2273
2274 if (status & UART_LSR_PE)
2275 port->err_shadow |= NPPI_NOTIFY_PARITY;
2276 if (status & UART_LSR_FE)
2277 port->err_shadow |= NPPI_NOTIFY_FRAMING;
2278 if (status & UART_LSR_OE)
2279 port->err_shadow |=
2280 NPPI_NOTIFY_HW_OVERRUN;
2281 if (status & UART_LSR_BI)
2282 port->err_shadow |= NPPI_NOTIFY_BREAK;
2283
2284 if (port->board->chip_flag) {
2285 if (iir == MOXA_MUST_IIR_GDA ||
2286 iir == MOXA_MUST_IIR_RDA ||
2287 iir == MOXA_MUST_IIR_RTO ||
2288 iir == MOXA_MUST_IIR_LSR)
216ba023 2289 mxser_receive_chars(tty, port,
1c45607a
JS		 2290 &status);
2291
2292 } else {
2293 status &= port->read_status_mask;
2294 if (status & UART_LSR_DR)
216ba023 2295 mxser_receive_chars(tty, port,
1c45607a
JS		 2296 &status);
2297 }
2298 msr = inb(port->ioaddr + UART_MSR);
2299 if (msr & UART_MSR_ANY_DELTA)
216ba023 2300 mxser_check_modem_status(tty, port, msr);
1c45607a
JS		 2301
2302 if (port->board->chip_flag) {
2303 if (iir == 0x02 && (status &
2304 UART_LSR_THRE))
216ba023 2305 mxser_transmit_chars(tty, port);
1c45607a
JS		 2306 } else {
2307 if (status & UART_LSR_THRE)
216ba023 2308 mxser_transmit_chars(tty, port);
1c45607a 2309 }
216ba023 2310 tty_kref_put(tty);
1c45607a
JS		 2311 } while (int_cnt++ < MXSER_ISR_PASS_LIMIT);
2312 spin_unlock(&port->slock);
2313 }
2314 }
1da177e4 2315
1c45607a
JS		 2316irq_stop:
2317 return handled;
2318}
1da177e4 2319
1c45607a
JS		 2320static const struct tty_operations mxser_ops = {
2321 .open = mxser_open,
2322 .close = mxser_close,
2323 .write = mxser_write,
2324 .put_char = mxser_put_char,
2325 .flush_chars = mxser_flush_chars,
2326 .write_room = mxser_write_room,
2327 .chars_in_buffer = mxser_chars_in_buffer,
2328 .flush_buffer = mxser_flush_buffer,
2329 .ioctl = mxser_ioctl,
2330 .throttle = mxser_throttle,
2331 .unthrottle = mxser_unthrottle,
2332 .set_termios = mxser_set_termios,
2333 .stop = mxser_stop,
2334 .start = mxser_start,
2335 .hangup = mxser_hangup,
2336 .break_ctl = mxser_rs_break,
2337 .wait_until_sent = mxser_wait_until_sent,
2338 .tiocmget = mxser_tiocmget,
2339 .tiocmset = mxser_tiocmset,
0587102c 2340 .get_icount = mxser_get_icount,
1c45607a 2341};
1da177e4 2342
31f35939
AC		 2343struct tty_port_operations mxser_port_ops = {
2344 .carrier_raised = mxser_carrier_raised,
fcc8ac18 2345 .dtr_rts = mxser_dtr_rts,
6769140d
AC		 2346 .activate = mxser_activate,
2347 .shutdown = mxser_shutdown_port,
31f35939
AC		 2348};
2349
1c45607a
JS		 2350/*
2351 * The MOXA Smartio/Industio serial driver boot-time initialization code!
2352 */
1da177e4 2353
df480518 2354static void mxser_release_ISA_res(struct mxser_board *brd)
1c45607a 2355{
df480518
JS		 2356 free_irq(brd->irq, brd);
2357 release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
2358 release_region(brd->vector, 1);
1da177e4
LT		 2359}
2360
1c45607a
JS		 2361static int __devinit mxser_initbrd(struct mxser_board *brd,
2362 struct pci_dev *pdev)
1da177e4 2363{
1c45607a
JS		 2364 struct mxser_port *info;
2365 unsigned int i;
2366 int retval;
1da177e4 2367
83766bc6
JS		 2368 printk(KERN_INFO "mxser: max. baud rate = %d bps\n",
2369 brd->ports[0].max_baud);
1da177e4 2370
1c45607a
JS		 2371 for (i = 0; i < brd->info->nports; i++) {
2372 info = &brd->ports[i];
44b7d1b3 2373 tty_port_init(&info->port);
31f35939 2374 info->port.ops = &mxser_port_ops;
1c45607a
JS		 2375 info->board = brd;
2376 info->stop_rx = 0;
2377 info->ldisc_stop_rx = 0;
1da177e4 2378
1c45607a
JS		 2379 /* Enhance mode enabled here */
2380 if (brd->chip_flag != MOXA_OTHER_UART)
148ff86b 2381 mxser_enable_must_enchance_mode(info->ioaddr);
1da177e4 2382
0ad9e7d1 2383 info->port.flags = ASYNC_SHARE_IRQ;
1c45607a 2384 info->type = brd->uart_type;
1da177e4 2385
1c45607a 2386 process_txrx_fifo(info);
1da177e4 2387
1c45607a 2388 info->custom_divisor = info->baud_base * 16;
44b7d1b3
AC		 2389 info->port.close_delay = 5 * HZ / 10;
2390 info->port.closing_wait = 30 * HZ;
1c45607a 2391 info->normal_termios = mxvar_sdriver->init_termios;
1c45607a
JS		 2392 memset(&info->mon_data, 0, sizeof(struct mxser_mon));
2393 info->err_shadow = 0;
2394 spin_lock_init(&info->slock);
1da177e4 2395
1c45607a
JS		 2396 /* before set INT ISR, disable all int */
2397 outb(inb(info->ioaddr + UART_IER) & 0xf0,
2398 info->ioaddr + UART_IER);
2399 }
1da177e4 2400
1c45607a
JS		 2401 retval = request_irq(brd->irq, mxser_interrupt, IRQF_SHARED, "mxser",
2402 brd);
df480518 2403 if (retval)
1c45607a
JS		 2404 printk(KERN_ERR "Board %s: Request irq failed, IRQ (%d) may "
2405 "conflict with another device.\n",
2406 brd->info->name, brd->irq);
df480518 2407
1c45607a
JS		 2408 return retval;
2409}
1da177e4 2410
1c45607a 2411static int __init mxser_get_ISA_conf(int cap, struct mxser_board *brd)
1da177e4
LT		 2412{
2413 int id, i, bits;
2414 unsigned short regs[16], irq;
2415 unsigned char scratch, scratch2;
2416
1c45607a 2417 brd->chip_flag = MOXA_OTHER_UART;
1da177e4
LT		 2418
2419 id = mxser_read_register(cap, regs);
1c45607a
JS		 2420 switch (id) {
2421 case C168_ASIC_ID:
2422 brd->info = &mxser_cards[0];
2423 break;
2424 case C104_ASIC_ID:
2425 brd->info = &mxser_cards[1];
2426 break;
2427 case CI104J_ASIC_ID:
2428 brd->info = &mxser_cards[2];
2429 break;
2430 case C102_ASIC_ID:
2431 brd->info = &mxser_cards[5];
2432 break;
2433 case CI132_ASIC_ID:
2434 brd->info = &mxser_cards[6];
2435 break;
2436 case CI134_ASIC_ID:
2437 brd->info = &mxser_cards[7];
2438 break;
2439 default:
8ea2c2ec 2440 return 0;
1c45607a 2441 }
1da177e4
LT		 2442
2443 irq = 0;
1c45607a
JS		 2444 /* some ISA cards have 2 ports, but we want to see them as 4-port (why?)
2445 Flag-hack checks if configuration should be read as 2-port here. */
2446 if (brd->info->nports == 2 || (brd->info->flags & MXSER_HAS2)) {
1da177e4
LT		 2447 irq = regs[9] & 0xF000;
2448 irq = irq | (irq >> 4);
2449 if (irq != (regs[9] & 0xFF00))
83766bc6 2450 goto err_irqconflict;
1c45607a 2451 } else if (brd->info->nports == 4) {
1da177e4
LT		 2452 irq = regs[9] & 0xF000;
2453 irq = irq | (irq >> 4);
2454 irq = irq | (irq >> 8);
2455 if (irq != regs[9])
83766bc6 2456 goto err_irqconflict;
1c45607a 2457 } else if (brd->info->nports == 8) {
1da177e4
LT		 2458 irq = regs[9] & 0xF000;
2459 irq = irq | (irq >> 4);
2460 irq = irq | (irq >> 8);
2461 if ((irq != regs[9]) || (irq != regs[10]))
83766bc6 2462 goto err_irqconflict;
1da177e4
LT		 2463 }
2464
83766bc6
JS		 2465 if (!irq) {
2466 printk(KERN_ERR "mxser: interrupt number unset\n");
2467 return -EIO;
2468 }
1c45607a 2469 brd->irq = ((int)(irq & 0xF000) >> 12);
1da177e4 2470 for (i = 0; i < 8; i++)
1c45607a 2471 brd->ports[i].ioaddr = (int) regs[i + 1] & 0xFFF8;
83766bc6
JS		 2472 if ((regs[12] & 0x80) == 0) {
2473 printk(KERN_ERR "mxser: invalid interrupt vector\n");
2474 return -EIO;
2475 }
1c45607a 2476 brd->vector = (int)regs[11]; /* interrupt vector */
1da177e4 2477 if (id == 1)
1c45607a 2478 brd->vector_mask = 0x00FF;
1da177e4 2479 else
1c45607a 2480 brd->vector_mask = 0x000F;
1da177e4
LT		 2481 for (i = 7, bits = 0x0100; i >= 0; i--, bits <<= 1) {
2482 if (regs[12] & bits) {
1c45607a
JS		 2483 brd->ports[i].baud_base = 921600;
2484 brd->ports[i].max_baud = 921600;
1da177e4 2485 } else {
1c45607a
JS		 2486 brd->ports[i].baud_base = 115200;
2487 brd->ports[i].max_baud = 115200;
1da177e4
LT		 2488 }
2489 }
2490 scratch2 = inb(cap + UART_LCR) & (~UART_LCR_DLAB);
2491 outb(scratch2 | UART_LCR_DLAB, cap + UART_LCR);
2492 outb(0, cap + UART_EFR); /* EFR is the same as FCR */
2493 outb(scratch2, cap + UART_LCR);
2494 outb(UART_FCR_ENABLE_FIFO, cap + UART_FCR);
2495 scratch = inb(cap + UART_IIR);
2496
2497 if (scratch & 0xC0)
1c45607a 2498 brd->uart_type = PORT_16550A;
1da177e4 2499 else
1c45607a
JS		 2500 brd->uart_type = PORT_16450;
2501 if (!request_region(brd->ports[0].ioaddr, 8 * brd->info->nports,
83766bc6
JS		 2502 "mxser(IO)")) {
2503 printk(KERN_ERR "mxser: can't request ports I/O region: "
2504 "0x%.8lx-0x%.8lx\n",
2505 brd->ports[0].ioaddr, brd->ports[0].ioaddr +
2506 8 * brd->info->nports - 1);
2507 return -EIO;
2508 }
1c45607a
JS		 2509 if (!request_region(brd->vector, 1, "mxser(vector)")) {
2510 release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
83766bc6
JS		 2511 printk(KERN_ERR "mxser: can't request interrupt vector region: "
2512 "0x%.8lx-0x%.8lx\n",
2513 brd->ports[0].ioaddr, brd->ports[0].ioaddr +
2514 8 * brd->info->nports - 1);
2515 return -EIO;
1c45607a
JS		 2516 }
2517 return brd->info->nports;
83766bc6
JS		 2518
2519err_irqconflict:
2520 printk(KERN_ERR "mxser: invalid interrupt number\n");
2521 return -EIO;
1da177e4
LT		 2522}
2523
1c45607a
JS		 2524static int __devinit mxser_probe(struct pci_dev *pdev,
2525 const struct pci_device_id *ent)
1da177e4 2526{
1c45607a
JS		 2527#ifdef CONFIG_PCI
2528 struct mxser_board *brd;
2529 unsigned int i, j;
2530 unsigned long ioaddress;
2531 int retval = -EINVAL;
1da177e4 2532
1c45607a
JS		 2533 for (i = 0; i < MXSER_BOARDS; i++)
2534 if (mxser_boards[i].info == NULL)
2535 break;
2536
2537 if (i >= MXSER_BOARDS) {
83766bc6
JS		 2538 dev_err(&pdev->dev, "too many boards found (maximum %d), board "
2539 "not configured\n", MXSER_BOARDS);
1c45607a
JS		 2540 goto err;
2541 }
2542
2543 brd = &mxser_boards[i];
2544 brd->idx = i * MXSER_PORTS_PER_BOARD;
83766bc6 2545 dev_info(&pdev->dev, "found MOXA %s board (BusNo=%d, DevNo=%d)\n",
1c45607a
JS		 2546 mxser_cards[ent->driver_data].name,
2547 pdev->bus->number, PCI_SLOT(pdev->devfn));
2548
2549 retval = pci_enable_device(pdev);
2550 if (retval) {
83766bc6 2551 dev_err(&pdev->dev, "PCI enable failed\n");
1c45607a
JS		 2552 goto err;
2553 }
2554
2555 /* io address */
2556 ioaddress = pci_resource_start(pdev, 2);
2557 retval = pci_request_region(pdev, 2, "mxser(IO)");
2558 if (retval)
df480518 2559 goto err_dis;
1c45607a
JS		 2560
2561 brd->info = &mxser_cards[ent->driver_data];
2562 for (i = 0; i < brd->info->nports; i++)
2563 brd->ports[i].ioaddr = ioaddress + 8 * i;
2564
2565 /* vector */
2566 ioaddress = pci_resource_start(pdev, 3);
2567 retval = pci_request_region(pdev, 3, "mxser(vector)");
2568 if (retval)
df480518 2569 goto err_zero;
1c45607a
JS		 2570 brd->vector = ioaddress;
2571
2572 /* irq */
2573 brd->irq = pdev->irq;
2574
2575 brd->chip_flag = CheckIsMoxaMust(brd->ports[0].ioaddr);
2576 brd->uart_type = PORT_16550A;
2577 brd->vector_mask = 0;
2578
2579 for (i = 0; i < brd->info->nports; i++) {
2580 for (j = 0; j < UART_INFO_NUM; j++) {
2581 if (Gpci_uart_info[j].type == brd->chip_flag) {
2582 brd->ports[i].max_baud =
2583 Gpci_uart_info[j].max_baud;
2584
2585 /* exception....CP-102 */
2586 if (brd->info->flags & MXSER_HIGHBAUD)
2587 brd->ports[i].max_baud = 921600;
2588 break;
1da177e4
LT		 2589 }
2590 }
1c45607a
JS		 2591 }
2592
2593 if (brd->chip_flag == MOXA_MUST_MU860_HWID) {
2594 for (i = 0; i < brd->info->nports; i++) {
2595 if (i < 4)
2596 brd->ports[i].opmode_ioaddr = ioaddress + 4;
2597 else
2598 brd->ports[i].opmode_ioaddr = ioaddress + 0x0c;
1da177e4 2599 }
1c45607a
JS		 2600 outb(0, ioaddress + 4); /* default set to RS232 mode */
2601 outb(0, ioaddress + 0x0c); /* default set to RS232 mode */
1da177e4 2602 }
1c45607a
JS		 2603
2604 for (i = 0; i < brd->info->nports; i++) {
2605 brd->vector_mask |= (1 << i);
2606 brd->ports[i].baud_base = 921600;
2607 }
2608
2609 /* mxser_initbrd will hook ISR. */
2610 retval = mxser_initbrd(brd, pdev);
2611 if (retval)
df480518 2612 goto err_rel3;
1c45607a
JS		 2613
2614 for (i = 0; i < brd->info->nports; i++)
2615 tty_register_device(mxvar_sdriver, brd->idx + i, &pdev->dev);
2616
2617 pci_set_drvdata(pdev, brd);
2618
2619 return 0;
df480518
JS		 2620err_rel3:
2621 pci_release_region(pdev, 3);
2622err_zero:
1c45607a 2623 brd->info = NULL;
df480518
JS		 2624 pci_release_region(pdev, 2);
2625err_dis:
2626 pci_disable_device(pdev);
1c45607a
JS		 2627err:
2628 return retval;
2629#else
2630 return -ENODEV;
2631#endif
1da177e4
LT		 2632}
2633
1c45607a 2634static void __devexit mxser_remove(struct pci_dev *pdev)
1da177e4 2635{
df480518 2636#ifdef CONFIG_PCI
1c45607a
JS		 2637 struct mxser_board *brd = pci_get_drvdata(pdev);
2638 unsigned int i;
1da177e4 2639
1c45607a
JS		 2640 for (i = 0; i < brd->info->nports; i++)
2641 tty_unregister_device(mxvar_sdriver, brd->idx + i);
1da177e4 2642
df480518
JS		 2643 free_irq(pdev->irq, brd);
2644 pci_release_region(pdev, 2);
2645 pci_release_region(pdev, 3);
2646 pci_disable_device(pdev);
1c45607a 2647 brd->info = NULL;
df480518 2648#endif
1da177e4
LT		 2649}
2650
1c45607a
JS		 2651static struct pci_driver mxser_driver = {
2652 .name = "mxser",
2653 .id_table = mxser_pcibrds,
2654 .probe = mxser_probe,
2655 .remove = __devexit_p(mxser_remove)
2656};
2657
2658static int __init mxser_module_init(void)
1da177e4 2659{
1c45607a 2660 struct mxser_board *brd;
1df00924
JS		 2661 unsigned int b, i, m;
2662 int retval;
1da177e4 2663
1c45607a
JS		 2664 mxvar_sdriver = alloc_tty_driver(MXSER_PORTS + 1);
2665 if (!mxvar_sdriver)
2666 return -ENOMEM;
2667
2668 printk(KERN_INFO "MOXA Smartio/Industio family driver version %s\n",
2669 MXSER_VERSION);
2670
2671 /* Initialize the tty_driver structure */
2672 mxvar_sdriver->owner = THIS_MODULE;
2673 mxvar_sdriver->magic = TTY_DRIVER_MAGIC;
2674 mxvar_sdriver->name = "ttyMI";
2675 mxvar_sdriver->major = ttymajor;
2676 mxvar_sdriver->minor_start = 0;
2677 mxvar_sdriver->num = MXSER_PORTS + 1;
2678 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL;
2679 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL;
2680 mxvar_sdriver->init_termios = tty_std_termios;
2681 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
2682 mxvar_sdriver->flags = TTY_DRIVER_REAL_RAW|TTY_DRIVER_DYNAMIC_DEV;
2683 tty_set_operations(mxvar_sdriver, &mxser_ops);
2684
2685 retval = tty_register_driver(mxvar_sdriver);
2686 if (retval) {
2687 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family "
2688 "tty driver !\n");
2689 goto err_put;
1da177e4 2690 }
1c45607a 2691
1c45607a 2692 /* Start finding ISA boards here */
1df00924
JS		 2693 for (m = 0, b = 0; b < MXSER_BOARDS; b++) {
2694 if (!ioaddr[b])
2695 continue;
2696
2697 brd = &mxser_boards[m];
96050dfb 2698 retval = mxser_get_ISA_conf(ioaddr[b], brd);
1df00924
JS		 2699 if (retval <= 0) {
2700 brd->info = NULL;
2701 continue;
2702 }
1c45607a 2703
1df00924
JS		 2704 printk(KERN_INFO "mxser: found MOXA %s board (CAP=0x%lx)\n",
2705 brd->info->name, ioaddr[b]);
83766bc6 2706
1df00924
JS		 2707 /* mxser_initbrd will hook ISR. */
2708 if (mxser_initbrd(brd, NULL) < 0) {
2709 brd->info = NULL;
2710 continue;
2711 }
1c45607a 2712
1df00924
JS		 2713 brd->idx = m * MXSER_PORTS_PER_BOARD;
2714 for (i = 0; i < brd->info->nports; i++)
2715 tty_register_device(mxvar_sdriver, brd->idx + i, NULL);
1c45607a 2716
1df00924
JS		 2717 m++;
2718 }
1c45607a
JS		 2719
2720 retval = pci_register_driver(&mxser_driver);
2721 if (retval) {
83766bc6 2722 printk(KERN_ERR "mxser: can't register pci driver\n");
1c45607a
JS		 2723 if (!m) {
2724 retval = -ENODEV;
2725 goto err_unr;
2726 } /* else: we have some ISA cards under control */
2727 }
2728
1c45607a
JS		 2729 return 0;
2730err_unr:
2731 tty_unregister_driver(mxvar_sdriver);
2732err_put:
2733 put_tty_driver(mxvar_sdriver);
2734 return retval;
2735}
2736
2737static void __exit mxser_module_exit(void)
2738{
2739 unsigned int i, j;
2740
1c45607a
JS		 2741 pci_unregister_driver(&mxser_driver);
2742
2743 for (i = 0; i < MXSER_BOARDS; i++) /* ISA remains */
2744 if (mxser_boards[i].info != NULL)
2745 for (j = 0; j < mxser_boards[i].info->nports; j++)
2746 tty_unregister_device(mxvar_sdriver,
2747 mxser_boards[i].idx + j);
2748 tty_unregister_driver(mxvar_sdriver);
2749 put_tty_driver(mxvar_sdriver);
2750
2751 for (i = 0; i < MXSER_BOARDS; i++)
2752 if (mxser_boards[i].info != NULL)
df480518 2753 mxser_release_ISA_res(&mxser_boards[i]);
1da177e4
LT		 2754}
2755
2756module_init(mxser_module_init);
2757module_exit(mxser_module_exit);
kernel source for telekom puls (alcatel/mediatek)