projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
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1 | /************************************************************************** |
| 2 | ||
| 3 | Copyright (C) 2004-2005 Nicolai Haehnle et al. | |
| 4 | ||
| 5 | Permission is hereby granted, free of charge, to any person obtaining a | |
| 6 | copy of this software and associated documentation files (the "Software"), | |
| 7 | to deal in the Software without restriction, including without limitation | |
| 8 | on the rights to use, copy, modify, merge, publish, distribute, sub | |
| 9 | license, and/or sell copies of the Software, and to permit persons to whom | |
| 10 | the Software is furnished to do so, subject to the following conditions: | |
| 11 | ||
| 12 | The above copyright notice and this permission notice (including the next | |
| 13 | paragraph) shall be included in all copies or substantial portions of the | |
| 14 | Software. | |
| 15 | ||
| 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 18 | FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
| 19 | THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
| 20 | DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
| 21 | OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
| 22 | USE OR OTHER DEALINGS IN THE SOFTWARE. | |
| 23 | ||
| 24 | **************************************************************************/ | |
| 25 | ||
| 26 | #ifndef _R300_REG_H | |
| 27 | #define _R300_REG_H | |
| 28 | ||
| 29 | #define R300_MC_INIT_MISC_LAT_TIMER 0x180 | |
| 30 | # define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT 0 | |
| 31 | # define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT 4 | |
| 32 | # define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT 8 | |
| 33 | # define R300_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT 12 | |
| 34 | # define R300_MC_MISC__MC_FIXED_INIT_LAT_SHIFT 16 | |
| 35 | # define R300_MC_MISC__MC_E2R_INIT_LAT_SHIFT 20 | |
| 36 | # define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT 24 | |
| 37 | # define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT 28 | |
| 38 | ||
| 414ed537 DA |
39 | #define R300_MC_INIT_GFX_LAT_TIMER 0x154 |
| 40 | # define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT 0 | |
| 41 | # define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT 4 | |
| 42 | # define R300_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT 8 | |
| 43 | # define R300_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT 12 | |
| 44 | # define R300_MC_MISC__MC_TX0R_INIT_LAT_SHIFT 16 | |
| 45 | # define R300_MC_MISC__MC_TX1R_INIT_LAT_SHIFT 20 | |
| 46 | # define R300_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT 24 | |
| 47 | # define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT 28 | |
| 48 | ||
| 49 | /* | |
| 50 | This file contains registers and constants for the R300. They have been | |
| 51 | found mostly by examining command buffers captured using glxtest, as well | |
| 52 | as by extrapolating some known registers and constants from the R200. | |
| 53 | ||
| 54 | I am fairly certain that they are correct unless stated otherwise in comments. | |
| 55 | */ | |
| 56 | ||
| 57 | #define R300_SE_VPORT_XSCALE 0x1D98 | |
| 58 | #define R300_SE_VPORT_XOFFSET 0x1D9C | |
| 59 | #define R300_SE_VPORT_YSCALE 0x1DA0 | |
| 60 | #define R300_SE_VPORT_YOFFSET 0x1DA4 | |
| 61 | #define R300_SE_VPORT_ZSCALE 0x1DA8 | |
| 62 | #define R300_SE_VPORT_ZOFFSET 0x1DAC | |
| 63 | ||
| 414ed537 DA |
64 | /* This register is written directly and also starts data section in many 3d CP_PACKET3's */ |
| 65 | #define R300_VAP_VF_CNTL 0x2084 | |
| 66 | ||
| 67 | # define R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT 0 | |
| 68 | # define R300_VAP_VF_CNTL__PRIM_NONE (0<<0) | |
| 69 | # define R300_VAP_VF_CNTL__PRIM_POINTS (1<<0) | |
| 70 | # define R300_VAP_VF_CNTL__PRIM_LINES (2<<0) | |
| 71 | # define R300_VAP_VF_CNTL__PRIM_LINE_STRIP (3<<0) | |
| 72 | # define R300_VAP_VF_CNTL__PRIM_TRIANGLES (4<<0) | |
| 73 | # define R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN (5<<0) | |
| 74 | # define R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0) | |
| 75 | # define R300_VAP_VF_CNTL__PRIM_LINE_LOOP (12<<0) | |
| 76 | # define R300_VAP_VF_CNTL__PRIM_QUADS (13<<0) | |
| 77 | # define R300_VAP_VF_CNTL__PRIM_QUAD_STRIP (14<<0) | |
| 78 | # define R300_VAP_VF_CNTL__PRIM_POLYGON (15<<0) | |
| 79 | ||
| 80 | # define R300_VAP_VF_CNTL__PRIM_WALK__SHIFT 4 | |
| 81 | /* State based - direct writes to registers trigger vertex generation */ | |
| 82 | # define R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4) | |
| 83 | # define R300_VAP_VF_CNTL__PRIM_WALK_INDICES (1<<4) | |
| 84 | # define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4) | |
| 85 | # define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4) | |
| 86 | ||
| 87 | /* I don't think I saw these three used.. */ | |
| 88 | # define R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT 6 | |
| 89 | # define R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9 | |
| 90 | # define R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10 | |
| 91 | ||
| 92 | /* index size - when not set the indices are assumed to be 16 bit */ | |
| 93 | # define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11) | |
| b5e89ed5 | 94 | /* number of vertices */ |
| 414ed537 DA |
95 | # define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16 |
| 96 | ||
| 97 | /* BEGIN: Wild guesses */ | |
| 98 | #define R300_VAP_OUTPUT_VTX_FMT_0 0x2090 | |
| 99 | # define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0) | |
| 100 | # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT (1<<1) | |
| b5e89ed5 DA |
101 | # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) /* GUESS */ |
| 102 | # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) /* GUESS */ | |
| 103 | # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) /* GUESS */ | |
| 104 | # define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) /* GUESS */ | |
| 414ed537 DA |
105 | |
| 106 | #define R300_VAP_OUTPUT_VTX_FMT_1 0x2094 | |
| 107 | # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 | |
| 108 | # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 | |
| 109 | # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 | |
| 110 | # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 | |
| 111 | # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 | |
| 112 | # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 | |
| 113 | # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 | |
| 114 | # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 | |
| 115 | /* END */ | |
| 116 | ||
| 117 | #define R300_SE_VTE_CNTL 0x20b0 | |
| 118 | # define R300_VPORT_X_SCALE_ENA 0x00000001 | |
| 119 | # define R300_VPORT_X_OFFSET_ENA 0x00000002 | |
| 120 | # define R300_VPORT_Y_SCALE_ENA 0x00000004 | |
| 121 | # define R300_VPORT_Y_OFFSET_ENA 0x00000008 | |
| 122 | # define R300_VPORT_Z_SCALE_ENA 0x00000010 | |
| 123 | # define R300_VPORT_Z_OFFSET_ENA 0x00000020 | |
| 124 | # define R300_VTX_XY_FMT 0x00000100 | |
| 125 | # define R300_VTX_Z_FMT 0x00000200 | |
| 126 | # define R300_VTX_W0_FMT 0x00000400 | |
| 127 | # define R300_VTX_W0_NORMALIZE 0x00000800 | |
| 128 | # define R300_VTX_ST_DENORMALIZED 0x00001000 | |
| 129 | ||
| 130 | /* BEGIN: Vertex data assembly - lots of uncertainties */ | |
| 131 | /* gap */ | |
| 132 | /* Where do we get our vertex data? | |
| 133 | // | |
| 134 | // Vertex data either comes either from immediate mode registers or from | |
| 135 | // vertex arrays. | |
| 136 | // There appears to be no mixed mode (though we can force the pitch of | |
| 137 | // vertex arrays to 0, effectively reusing the same element over and over | |
| 138 | // again). | |
| 139 | // | |
| 140 | // Immediate mode is controlled by the INPUT_CNTL registers. I am not sure | |
| 141 | // if these registers influence vertex array processing. | |
| 142 | // | |
| 143 | // Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3. | |
| 144 | // | |
| 145 | // In both cases, vertex attributes are then passed through INPUT_ROUTE. | |
| 146 | ||
| 147 | // Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data | |
| 148 | // into the vertex processor's input registers. | |
| 149 | // The first word routes the first input, the second word the second, etc. | |
| 150 | // The corresponding input is routed into the register with the given index. | |
| 151 | // The list is ended by a word with INPUT_ROUTE_END set. | |
| 152 | // | |
| 153 | // Always set COMPONENTS_4 in immediate mode. */ | |
| 154 | ||
| 155 | #define R300_VAP_INPUT_ROUTE_0_0 0x2150 | |
| 156 | # define R300_INPUT_ROUTE_COMPONENTS_1 (0 << 0) | |
| 157 | # define R300_INPUT_ROUTE_COMPONENTS_2 (1 << 0) | |
| 158 | # define R300_INPUT_ROUTE_COMPONENTS_3 (2 << 0) | |
| 159 | # define R300_INPUT_ROUTE_COMPONENTS_4 (3 << 0) | |
| b5e89ed5 | 160 | # define R300_INPUT_ROUTE_COMPONENTS_RGBA (4 << 0) /* GUESS */ |
| 414ed537 | 161 | # define R300_VAP_INPUT_ROUTE_IDX_SHIFT 8 |
| b5e89ed5 | 162 | # define R300_VAP_INPUT_ROUTE_IDX_MASK (31 << 8) /* GUESS */ |
| 414ed537 | 163 | # define R300_VAP_INPUT_ROUTE_END (1 << 13) |
| b5e89ed5 DA |
164 | # define R300_INPUT_ROUTE_IMMEDIATE_MODE (0 << 14) /* GUESS */ |
| 165 | # define R300_INPUT_ROUTE_FLOAT (1 << 14) /* GUESS */ | |
| 166 | # define R300_INPUT_ROUTE_UNSIGNED_BYTE (2 << 14) /* GUESS */ | |
| 167 | # define R300_INPUT_ROUTE_FLOAT_COLOR (3 << 14) /* GUESS */ | |
| 414ed537 DA |
168 | #define R300_VAP_INPUT_ROUTE_0_1 0x2154 |
| 169 | #define R300_VAP_INPUT_ROUTE_0_2 0x2158 | |
| 170 | #define R300_VAP_INPUT_ROUTE_0_3 0x215C | |
| 171 | #define R300_VAP_INPUT_ROUTE_0_4 0x2160 | |
| 172 | #define R300_VAP_INPUT_ROUTE_0_5 0x2164 | |
| 173 | #define R300_VAP_INPUT_ROUTE_0_6 0x2168 | |
| 174 | #define R300_VAP_INPUT_ROUTE_0_7 0x216C | |
| 175 | ||
| 176 | /* gap */ | |
| 177 | /* Notes: | |
| 178 | // - always set up to produce at least two attributes: | |
| 179 | // if vertex program uses only position, fglrx will set normal, too | |
| 180 | // - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal */ | |
| 181 | #define R300_VAP_INPUT_CNTL_0 0x2180 | |
| 182 | # define R300_INPUT_CNTL_0_COLOR 0x00000001 | |
| 183 | #define R300_VAP_INPUT_CNTL_1 0x2184 | |
| 184 | # define R300_INPUT_CNTL_POS 0x00000001 | |
| 185 | # define R300_INPUT_CNTL_NORMAL 0x00000002 | |
| 186 | # define R300_INPUT_CNTL_COLOR 0x00000004 | |
| 187 | # define R300_INPUT_CNTL_TC0 0x00000400 | |
| 188 | # define R300_INPUT_CNTL_TC1 0x00000800 | |
| b5e89ed5 DA |
189 | # define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */ |
| 190 | # define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */ | |
| 191 | # define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */ | |
| 192 | # define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */ | |
| 193 | # define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */ | |
| 194 | # define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */ | |
| 414ed537 DA |
195 | |
| 196 | /* gap */ | |
| 197 | /* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0 | |
| 198 | // are set to a swizzling bit pattern, other words are 0. | |
| 199 | // | |
| 200 | // In immediate mode, the pattern is always set to xyzw. In vertex array | |
| 201 | // mode, the swizzling pattern is e.g. used to set zw components in texture | |
| 202 | // coordinates with only tweo components. */ | |
| 203 | #define R300_VAP_INPUT_ROUTE_1_0 0x21E0 | |
| 204 | # define R300_INPUT_ROUTE_SELECT_X 0 | |
| 205 | # define R300_INPUT_ROUTE_SELECT_Y 1 | |
| 206 | # define R300_INPUT_ROUTE_SELECT_Z 2 | |
| 207 | # define R300_INPUT_ROUTE_SELECT_W 3 | |
| 208 | # define R300_INPUT_ROUTE_SELECT_ZERO 4 | |
| 209 | # define R300_INPUT_ROUTE_SELECT_ONE 5 | |
| 210 | # define R300_INPUT_ROUTE_SELECT_MASK 7 | |
| 211 | # define R300_INPUT_ROUTE_X_SHIFT 0 | |
| 212 | # define R300_INPUT_ROUTE_Y_SHIFT 3 | |
| 213 | # define R300_INPUT_ROUTE_Z_SHIFT 6 | |
| 214 | # define R300_INPUT_ROUTE_W_SHIFT 9 | |
| 215 | # define R300_INPUT_ROUTE_ENABLE (15 << 12) | |
| 216 | #define R300_VAP_INPUT_ROUTE_1_1 0x21E4 | |
| 217 | #define R300_VAP_INPUT_ROUTE_1_2 0x21E8 | |
| 218 | #define R300_VAP_INPUT_ROUTE_1_3 0x21EC | |
| 219 | #define R300_VAP_INPUT_ROUTE_1_4 0x21F0 | |
| 220 | #define R300_VAP_INPUT_ROUTE_1_5 0x21F4 | |
| 221 | #define R300_VAP_INPUT_ROUTE_1_6 0x21F8 | |
| 222 | #define R300_VAP_INPUT_ROUTE_1_7 0x21FC | |
| 223 | ||
| 224 | /* END */ | |
| 225 | ||
| 226 | /* gap */ | |
| 227 | /* BEGIN: Upload vertex program and data | |
| 228 | // The programmable vertex shader unit has a memory bank of unknown size | |
| 229 | // that can be written to in 16 byte units by writing the address into | |
| 230 | // UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs). | |
| 231 | // | |
| 232 | // Pointers into the memory bank are always in multiples of 16 bytes. | |
| 233 | // | |
| 234 | // The memory bank is divided into areas with fixed meaning. | |
| 235 | // | |
| 236 | // Starting at address UPLOAD_PROGRAM: Vertex program instructions. | |
| 237 | // Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB), | |
| 238 | // whereas the difference between known addresses suggests size 512. | |
| 239 | // | |
| 240 | // Starting at address UPLOAD_PARAMETERS: Vertex program parameters. | |
| 241 | // Native reported limits and the VPI layout suggest size 256, whereas | |
| 242 | // difference between known addresses suggests size 512. | |
| 243 | // | |
| 244 | // At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the | |
| 245 | // floating point pointsize. The exact purpose of this state is uncertain, | |
| 246 | // as there is also the R300_RE_POINTSIZE register. | |
| 247 | // | |
| 248 | // Multiple vertex programs and parameter sets can be loaded at once, | |
| 249 | // which could explain the size discrepancy. */ | |
| 250 | #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200 | |
| 251 | # define R300_PVS_UPLOAD_PROGRAM 0x00000000 | |
| 252 | # define R300_PVS_UPLOAD_PARAMETERS 0x00000200 | |
| 253 | # define R300_PVS_UPLOAD_POINTSIZE 0x00000406 | |
| 254 | /* gap */ | |
| 255 | #define R300_VAP_PVS_UPLOAD_DATA 0x2208 | |
| 256 | /* END */ | |
| 257 | ||
| 258 | /* gap */ | |
| 259 | /* I do not know the purpose of this register. However, I do know that | |
| 260 | // it is set to 221C_CLEAR for clear operations and to 221C_NORMAL | |
| 261 | // for normal rendering. */ | |
| 262 | #define R300_VAP_UNKNOWN_221C 0x221C | |
| 263 | # define R300_221C_NORMAL 0x00000000 | |
| 264 | # define R300_221C_CLEAR 0x0001C000 | |
| 265 | ||
| 266 | /* gap */ | |
| 267 | /* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between | |
| 268 | // rendering commands and overwriting vertex program parameters. | |
| 269 | // Therefore, I suspect writing zero to 0x2284 synchronizes the engine and | |
| 270 | // avoids bugs caused by still running shaders reading bad data from memory. */ | |
| b5e89ed5 | 271 | #define R300_VAP_PVS_WAITIDLE 0x2284 /* GUESS */ |
| 414ed537 DA |
272 | |
| 273 | /* Absolutely no clue what this register is about. */ | |
| 274 | #define R300_VAP_UNKNOWN_2288 0x2288 | |
| b5e89ed5 DA |
275 | # define R300_2288_R300 0x00750000 /* -- nh */ |
| 276 | # define R300_2288_RV350 0x0000FFFF /* -- Vladimir */ | |
| 414ed537 DA |
277 | |
| 278 | /* gap */ | |
| 279 | /* Addresses are relative to the vertex program instruction area of the | |
| 280 | // memory bank. PROGRAM_END points to the last instruction of the active | |
| 281 | // program | |
| 282 | // | |
| 283 | // The meaning of the two UNKNOWN fields is obviously not known. However, | |
| 284 | // experiments so far have shown that both *must* point to an instruction | |
| 285 | // inside the vertex program, otherwise the GPU locks up. | |
| 286 | // fglrx usually sets CNTL_3_UNKNOWN to the end of the program and | |
| b5e89ed5 | 287 | // CNTL_1_UNKNOWN points to instruction where last write to position takes place. |
| 414ed537 DA |
288 | // Most likely this is used to ignore rest of the program in cases where group of verts arent visible. |
| 289 | // For some reason this "section" is sometimes accepted other instruction that have | |
| b5e89ed5 | 290 | // no relationship with position calculations. |
| 414ed537 DA |
291 | */ |
| 292 | #define R300_VAP_PVS_CNTL_1 0x22D0 | |
| 293 | # define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0 | |
| 294 | # define R300_PVS_CNTL_1_POS_END_SHIFT 10 | |
| 295 | # define R300_PVS_CNTL_1_PROGRAM_END_SHIFT 20 | |
| 296 | /* Addresses are relative the the vertex program parameters area. */ | |
| 297 | #define R300_VAP_PVS_CNTL_2 0x22D4 | |
| 298 | # define R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT 0 | |
| 299 | # define R300_PVS_CNTL_2_PARAM_COUNT_SHIFT 16 | |
| 300 | #define R300_VAP_PVS_CNTL_3 0x22D8 | |
| 301 | # define R300_PVS_CNTL_3_PROGRAM_UNKNOWN_SHIFT 10 | |
| 302 | # define R300_PVS_CNTL_3_PROGRAM_UNKNOWN2_SHIFT 0 | |
| 303 | ||
| 304 | /* The entire range from 0x2300 to 0x2AC inclusive seems to be used for | |
| 305 | // immediate vertices */ | |
| 306 | #define R300_VAP_VTX_COLOR_R 0x2464 | |
| 307 | #define R300_VAP_VTX_COLOR_G 0x2468 | |
| 308 | #define R300_VAP_VTX_COLOR_B 0x246C | |
| b5e89ed5 | 309 | #define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */ |
| 414ed537 | 310 | #define R300_VAP_VTX_POS_0_Y_1 0x2494 |
| b5e89ed5 DA |
311 | #define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */ |
| 312 | #define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */ | |
| 414ed537 DA |
313 | #define R300_VAP_VTX_POS_0_Y_2 0x24A4 |
| 314 | #define R300_VAP_VTX_POS_0_Z_2 0x24A8 | |
| b5e89ed5 | 315 | #define R300_VAP_VTX_END_OF_PKT 0x24AC /* write 0 to indicate end of packet? */ |
| 414ed537 DA |
316 | |
| 317 | /* gap */ | |
| 318 | ||
| 319 | /* These are values from r300_reg/r300_reg.h - they are known to be correct | |
| 320 | and are here so we can use one register file instead of several | |
| 321 | - Vladimir */ | |
| 322 | #define R300_GB_VAP_RASTER_VTX_FMT_0 0x4000 | |
| 323 | # define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0) | |
| 324 | # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1) | |
| 325 | # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT (1<<2) | |
| 326 | # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT (1<<3) | |
| 327 | # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT (1<<4) | |
| 328 | # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE (0xf<<5) | |
| 329 | # define R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT (0x1<<16) | |
| 330 | ||
| 331 | #define R300_GB_VAP_RASTER_VTX_FMT_1 0x4004 | |
| 332 | /* each of the following is 3 bits wide, specifies number | |
| 333 | of components */ | |
| 334 | # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 | |
| 335 | # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 | |
| 336 | # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 | |
| 337 | # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 | |
| 338 | # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 | |
| 339 | # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 | |
| 340 | # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 | |
| 341 | # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 | |
| 342 | ||
| 343 | /* UNK30 seems to enables point to quad transformation on textures | |
| 344 | (or something closely related to that). | |
| 345 | This bit is rather fatal at the time being due to lackings at pixel shader side */ | |
| 346 | #define R300_GB_ENABLE 0x4008 | |
| 347 | # define R300_GB_POINT_STUFF_ENABLE (1<<0) | |
| 348 | # define R300_GB_LINE_STUFF_ENABLE (1<<1) | |
| 349 | # define R300_GB_TRIANGLE_STUFF_ENABLE (1<<2) | |
| 350 | # define R300_GB_STENCIL_AUTO_ENABLE (1<<4) | |
| 351 | # define R300_GB_UNK30 (1<<30) | |
| 352 | /* each of the following is 2 bits wide */ | |
| 353 | #define R300_GB_TEX_REPLICATE 0 | |
| 354 | #define R300_GB_TEX_ST 1 | |
| 355 | #define R300_GB_TEX_STR 2 | |
| 356 | # define R300_GB_TEX0_SOURCE_SHIFT 16 | |
| 357 | # define R300_GB_TEX1_SOURCE_SHIFT 18 | |
| 358 | # define R300_GB_TEX2_SOURCE_SHIFT 20 | |
| 359 | # define R300_GB_TEX3_SOURCE_SHIFT 22 | |
| 360 | # define R300_GB_TEX4_SOURCE_SHIFT 24 | |
| 361 | # define R300_GB_TEX5_SOURCE_SHIFT 26 | |
| 362 | # define R300_GB_TEX6_SOURCE_SHIFT 28 | |
| 363 | # define R300_GB_TEX7_SOURCE_SHIFT 30 | |
| 364 | ||
| 365 | /* MSPOS - positions for multisample antialiasing (?) */ | |
| 366 | #define R300_GB_MSPOS0 0x4010 | |
| 367 | /* shifts - each of the fields is 4 bits */ | |
| 368 | # define R300_GB_MSPOS0__MS_X0_SHIFT 0 | |
| 369 | # define R300_GB_MSPOS0__MS_Y0_SHIFT 4 | |
| 370 | # define R300_GB_MSPOS0__MS_X1_SHIFT 8 | |
| 371 | # define R300_GB_MSPOS0__MS_Y1_SHIFT 12 | |
| 372 | # define R300_GB_MSPOS0__MS_X2_SHIFT 16 | |
| 373 | # define R300_GB_MSPOS0__MS_Y2_SHIFT 20 | |
| 374 | # define R300_GB_MSPOS0__MSBD0_Y 24 | |
| 375 | # define R300_GB_MSPOS0__MSBD0_X 28 | |
| 376 | ||
| 377 | #define R300_GB_MSPOS1 0x4014 | |
| 378 | # define R300_GB_MSPOS1__MS_X3_SHIFT 0 | |
| 379 | # define R300_GB_MSPOS1__MS_Y3_SHIFT 4 | |
| 380 | # define R300_GB_MSPOS1__MS_X4_SHIFT 8 | |
| 381 | # define R300_GB_MSPOS1__MS_Y4_SHIFT 12 | |
| 382 | # define R300_GB_MSPOS1__MS_X5_SHIFT 16 | |
| 383 | # define R300_GB_MSPOS1__MS_Y5_SHIFT 20 | |
| 384 | # define R300_GB_MSPOS1__MSBD1 24 | |
| 385 | ||
| 414ed537 DA |
386 | #define R300_GB_TILE_CONFIG 0x4018 |
| 387 | # define R300_GB_TILE_ENABLE (1<<0) | |
| 388 | # define R300_GB_TILE_PIPE_COUNT_RV300 0 | |
| 389 | # define R300_GB_TILE_PIPE_COUNT_R300 (3<<1) | |
| 390 | # define R300_GB_TILE_PIPE_COUNT_R420 (7<<1) | |
| 391 | # define R300_GB_TILE_SIZE_8 0 | |
| 392 | # define R300_GB_TILE_SIZE_16 (1<<4) | |
| 393 | # define R300_GB_TILE_SIZE_32 (2<<4) | |
| 394 | # define R300_GB_SUPER_SIZE_1 (0<<6) | |
| 395 | # define R300_GB_SUPER_SIZE_2 (1<<6) | |
| 396 | # define R300_GB_SUPER_SIZE_4 (2<<6) | |
| 397 | # define R300_GB_SUPER_SIZE_8 (3<<6) | |
| 398 | # define R300_GB_SUPER_SIZE_16 (4<<6) | |
| 399 | # define R300_GB_SUPER_SIZE_32 (5<<6) | |
| 400 | # define R300_GB_SUPER_SIZE_64 (6<<6) | |
| 401 | # define R300_GB_SUPER_SIZE_128 (7<<6) | |
| 402 | # define R300_GB_SUPER_X_SHIFT 9 /* 3 bits wide */ | |
| 403 | # define R300_GB_SUPER_Y_SHIFT 12 /* 3 bits wide */ | |
| 404 | # define R300_GB_SUPER_TILE_A 0 | |
| 405 | # define R300_GB_SUPER_TILE_B (1<<15) | |
| 406 | # define R300_GB_SUBPIXEL_1_12 0 | |
| 407 | # define R300_GB_SUBPIXEL_1_16 (1<<16) | |
| 408 | ||
| 409 | #define R300_GB_FIFO_SIZE 0x4024 | |
| 410 | /* each of the following is 2 bits wide */ | |
| 411 | #define R300_GB_FIFO_SIZE_32 0 | |
| 412 | #define R300_GB_FIFO_SIZE_64 1 | |
| 413 | #define R300_GB_FIFO_SIZE_128 2 | |
| 414 | #define R300_GB_FIFO_SIZE_256 3 | |
| 415 | # define R300_SC_IFIFO_SIZE_SHIFT 0 | |
| 416 | # define R300_SC_TZFIFO_SIZE_SHIFT 2 | |
| 417 | # define R300_SC_BFIFO_SIZE_SHIFT 4 | |
| 418 | ||
| 419 | # define R300_US_OFIFO_SIZE_SHIFT 12 | |
| 420 | # define R300_US_WFIFO_SIZE_SHIFT 14 | |
| 421 | /* the following use the same constants as above, but meaning is | |
| 422 | is times 2 (i.e. instead of 32 words it means 64 */ | |
| 423 | # define R300_RS_TFIFO_SIZE_SHIFT 6 | |
| 424 | # define R300_RS_CFIFO_SIZE_SHIFT 8 | |
| 425 | # define R300_US_RAM_SIZE_SHIFT 10 | |
| 426 | /* watermarks, 3 bits wide */ | |
| 427 | # define R300_RS_HIGHWATER_COL_SHIFT 16 | |
| 428 | # define R300_RS_HIGHWATER_TEX_SHIFT 19 | |
| 429 | # define R300_OFIFO_HIGHWATER_SHIFT 22 /* two bits only */ | |
| 430 | # define R300_CUBE_FIFO_HIGHWATER_COL_SHIFT 24 | |
| 431 | ||
| 432 | #define R300_GB_SELECT 0x401C | |
| 433 | # define R300_GB_FOG_SELECT_C0A 0 | |
| 434 | # define R300_GB_FOG_SELECT_C1A 1 | |
| 435 | # define R300_GB_FOG_SELECT_C2A 2 | |
| 436 | # define R300_GB_FOG_SELECT_C3A 3 | |
| 437 | # define R300_GB_FOG_SELECT_1_1_W 4 | |
| 438 | # define R300_GB_FOG_SELECT_Z 5 | |
| 439 | # define R300_GB_DEPTH_SELECT_Z 0 | |
| 440 | # define R300_GB_DEPTH_SELECT_1_1_W (1<<3) | |
| 441 | # define R300_GB_W_SELECT_1_W 0 | |
| 442 | # define R300_GB_W_SELECT_1 (1<<4) | |
| 443 | ||
| 444 | #define R300_GB_AA_CONFIG 0x4020 | |
| 445 | # define R300_AA_ENABLE 0x01 | |
| 446 | # define R300_AA_SUBSAMPLES_2 0 | |
| 447 | # define R300_AA_SUBSAMPLES_3 (1<<1) | |
| 448 | # define R300_AA_SUBSAMPLES_4 (2<<1) | |
| 449 | # define R300_AA_SUBSAMPLES_6 (3<<1) | |
| 450 | ||
| 451 | /* END */ | |
| 452 | ||
| 453 | /* gap */ | |
| 454 | /* The upper enable bits are guessed, based on fglrx reported limits. */ | |
| 455 | #define R300_TX_ENABLE 0x4104 | |
| 456 | # define R300_TX_ENABLE_0 (1 << 0) | |
| 457 | # define R300_TX_ENABLE_1 (1 << 1) | |
| 458 | # define R300_TX_ENABLE_2 (1 << 2) | |
| 459 | # define R300_TX_ENABLE_3 (1 << 3) | |
| 460 | # define R300_TX_ENABLE_4 (1 << 4) | |
| 461 | # define R300_TX_ENABLE_5 (1 << 5) | |
| 462 | # define R300_TX_ENABLE_6 (1 << 6) | |
| 463 | # define R300_TX_ENABLE_7 (1 << 7) | |
| 464 | # define R300_TX_ENABLE_8 (1 << 8) | |
| 465 | # define R300_TX_ENABLE_9 (1 << 9) | |
| 466 | # define R300_TX_ENABLE_10 (1 << 10) | |
| 467 | # define R300_TX_ENABLE_11 (1 << 11) | |
| 468 | # define R300_TX_ENABLE_12 (1 << 12) | |
| 469 | # define R300_TX_ENABLE_13 (1 << 13) | |
| 470 | # define R300_TX_ENABLE_14 (1 << 14) | |
| 471 | # define R300_TX_ENABLE_15 (1 << 15) | |
| 472 | ||
| 473 | /* The pointsize is given in multiples of 6. The pointsize can be | |
| 474 | // enormous: Clear() renders a single point that fills the entire | |
| 475 | // framebuffer. */ | |
| 476 | #define R300_RE_POINTSIZE 0x421C | |
| 477 | # define R300_POINTSIZE_Y_SHIFT 0 | |
| b5e89ed5 | 478 | # define R300_POINTSIZE_Y_MASK (0xFFFF << 0) /* GUESS */ |
| 414ed537 | 479 | # define R300_POINTSIZE_X_SHIFT 16 |
| b5e89ed5 | 480 | # define R300_POINTSIZE_X_MASK (0xFFFF << 16) /* GUESS */ |
| 414ed537 DA |
481 | # define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6) |
| 482 | ||
| 483 | /* The line width is given in multiples of 6. | |
| 484 | In default mode lines are classified as vertical lines. | |
| 485 | HO: horizontal | |
| 486 | VE: vertical or horizontal | |
| 487 | HO & VE: no classification | |
| 488 | */ | |
| 489 | #define R300_RE_LINE_CNT 0x4234 | |
| 490 | # define R300_LINESIZE_SHIFT 0 | |
| b5e89ed5 | 491 | # define R300_LINESIZE_MASK (0xFFFF << 0) /* GUESS */ |
| 414ed537 DA |
492 | # define R300_LINESIZE_MAX (R300_LINESIZE_MASK / 6) |
| 493 | # define R300_LINE_CNT_HO (1 << 16) | |
| 494 | # define R300_LINE_CNT_VE (1 << 17) | |
| 495 | ||
| 496 | /* Some sort of scale or clamp value for texcoordless textures. */ | |
| 497 | #define R300_RE_UNK4238 0x4238 | |
| 498 | ||
| 499 | #define R300_RE_SHADE_MODEL 0x4278 | |
| 500 | # define R300_RE_SHADE_MODEL_SMOOTH 0x3aaaa | |
| 501 | # define R300_RE_SHADE_MODEL_FLAT 0x39595 | |
| 502 | ||
| 503 | /* Dangerous */ | |
| 504 | #define R300_RE_POLYGON_MODE 0x4288 | |
| 505 | # define R300_PM_ENABLED (1 << 0) | |
| 506 | # define R300_PM_FRONT_POINT (0 << 0) | |
| 507 | # define R300_PM_BACK_POINT (0 << 0) | |
| 508 | # define R300_PM_FRONT_LINE (1 << 4) | |
| 509 | # define R300_PM_FRONT_FILL (1 << 5) | |
| 510 | # define R300_PM_BACK_LINE (1 << 7) | |
| 511 | # define R300_PM_BACK_FILL (1 << 8) | |
| 512 | ||
| b5e89ed5 DA |
513 | /* Not sure why there are duplicate of factor and constant values. |
| 514 | My best guess so far is that there are seperate zbiases for test and write. | |
| 414ed537 DA |
515 | Ordering might be wrong. |
| 516 | Some of the tests indicate that fgl has a fallback implementation of zbias | |
| 517 | via pixel shaders. */ | |
| 518 | #define R300_RE_ZBIAS_T_FACTOR 0x42A4 | |
| 519 | #define R300_RE_ZBIAS_T_CONSTANT 0x42A8 | |
| 520 | #define R300_RE_ZBIAS_W_FACTOR 0x42AC | |
| 521 | #define R300_RE_ZBIAS_W_CONSTANT 0x42B0 | |
| 522 | ||
| 523 | /* This register needs to be set to (1<<1) for RV350 to correctly | |
| 524 | perform depth test (see --vb-triangles in r300_demo) | |
| 525 | Don't know about other chips. - Vladimir | |
| 526 | This is set to 3 when GL_POLYGON_OFFSET_FILL is on. | |
| 527 | My guess is that there are two bits for each zbias primitive (FILL, LINE, POINT). | |
| 528 | One to enable depth test and one for depth write. | |
| 529 | Yet this doesnt explain why depth writes work ... | |
| 530 | */ | |
| 531 | #define R300_RE_OCCLUSION_CNTL 0x42B4 | |
| 532 | # define R300_OCCLUSION_ON (1<<1) | |
| 533 | ||
| 534 | #define R300_RE_CULL_CNTL 0x42B8 | |
| 535 | # define R300_CULL_FRONT (1 << 0) | |
| 536 | # define R300_CULL_BACK (1 << 1) | |
| 537 | # define R300_FRONT_FACE_CCW (0 << 2) | |
| 538 | # define R300_FRONT_FACE_CW (1 << 2) | |
| 539 | ||
| 414ed537 DA |
540 | /* BEGIN: Rasterization / Interpolators - many guesses |
| 541 | // 0_UNKNOWN_18 has always been set except for clear operations. | |
| 542 | // TC_CNT is the number of incoming texture coordinate sets (i.e. it depends | |
| 543 | // on the vertex program, *not* the fragment program) */ | |
| 544 | #define R300_RS_CNTL_0 0x4300 | |
| 545 | # define R300_RS_CNTL_TC_CNT_SHIFT 2 | |
| 546 | # define R300_RS_CNTL_TC_CNT_MASK (7 << 2) | |
| b5e89ed5 | 547 | # define R300_RS_CNTL_CI_CNT_SHIFT 7 /* number of color interpolators used */ |
| 414ed537 DA |
548 | # define R300_RS_CNTL_0_UNKNOWN_18 (1 << 18) |
| 549 | /* Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n register. */ | |
| 550 | #define R300_RS_CNTL_1 0x4304 | |
| 551 | ||
| 552 | /* gap */ | |
| 553 | /* Only used for texture coordinates. | |
| 554 | // Use the source field to route texture coordinate input from the vertex program | |
| 555 | // to the desired interpolator. Note that the source field is relative to the | |
| 556 | // outputs the vertex program *actually* writes. If a vertex program only writes | |
| 557 | // texcoord[1], this will be source index 0. | |
| 558 | // Set INTERP_USED on all interpolators that produce data used by the | |
| 559 | // fragment program. INTERP_USED looks like a swizzling mask, but | |
| 560 | // I haven't seen it used that way. | |
| 561 | // | |
| 562 | // Note: The _UNKNOWN constants are always set in their respective register. | |
| 563 | // I don't know if this is necessary. */ | |
| 564 | #define R300_RS_INTERP_0 0x4310 | |
| 565 | #define R300_RS_INTERP_1 0x4314 | |
| 566 | # define R300_RS_INTERP_1_UNKNOWN 0x40 | |
| 567 | #define R300_RS_INTERP_2 0x4318 | |
| 568 | # define R300_RS_INTERP_2_UNKNOWN 0x80 | |
| 569 | #define R300_RS_INTERP_3 0x431C | |
| 570 | # define R300_RS_INTERP_3_UNKNOWN 0xC0 | |
| 571 | #define R300_RS_INTERP_4 0x4320 | |
| 572 | #define R300_RS_INTERP_5 0x4324 | |
| 573 | #define R300_RS_INTERP_6 0x4328 | |
| 574 | #define R300_RS_INTERP_7 0x432C | |
| 575 | # define R300_RS_INTERP_SRC_SHIFT 2 | |
| 576 | # define R300_RS_INTERP_SRC_MASK (7 << 2) | |
| 577 | # define R300_RS_INTERP_USED 0x00D10000 | |
| 578 | ||
| 579 | /* These DWORDs control how vertex data is routed into fragment program | |
| 580 | // registers, after interpolators. */ | |
| 581 | #define R300_RS_ROUTE_0 0x4330 | |
| 582 | #define R300_RS_ROUTE_1 0x4334 | |
| 583 | #define R300_RS_ROUTE_2 0x4338 | |
| b5e89ed5 DA |
584 | #define R300_RS_ROUTE_3 0x433C /* GUESS */ |
| 585 | #define R300_RS_ROUTE_4 0x4340 /* GUESS */ | |
| 586 | #define R300_RS_ROUTE_5 0x4344 /* GUESS */ | |
| 587 | #define R300_RS_ROUTE_6 0x4348 /* GUESS */ | |
| 588 | #define R300_RS_ROUTE_7 0x434C /* GUESS */ | |
| 414ed537 DA |
589 | # define R300_RS_ROUTE_SOURCE_INTERP_0 0 |
| 590 | # define R300_RS_ROUTE_SOURCE_INTERP_1 1 | |
| 591 | # define R300_RS_ROUTE_SOURCE_INTERP_2 2 | |
| 592 | # define R300_RS_ROUTE_SOURCE_INTERP_3 3 | |
| 593 | # define R300_RS_ROUTE_SOURCE_INTERP_4 4 | |
| b5e89ed5 DA |
594 | # define R300_RS_ROUTE_SOURCE_INTERP_5 5 /* GUESS */ |
| 595 | # define R300_RS_ROUTE_SOURCE_INTERP_6 6 /* GUESS */ | |
| 596 | # define R300_RS_ROUTE_SOURCE_INTERP_7 7 /* GUESS */ | |
| 597 | # define R300_RS_ROUTE_ENABLE (1 << 3) /* GUESS */ | |
| 414ed537 | 598 | # define R300_RS_ROUTE_DEST_SHIFT 6 |
| b5e89ed5 | 599 | # define R300_RS_ROUTE_DEST_MASK (31 << 6) /* GUESS */ |
| 414ed537 DA |
600 | |
| 601 | /* Special handling for color: When the fragment program uses color, | |
| 602 | // the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the | |
| 603 | // color register index. */ | |
| 604 | # define R300_RS_ROUTE_0_COLOR (1 << 14) | |
| 605 | # define R300_RS_ROUTE_0_COLOR_DEST_SHIFT 17 | |
| b5e89ed5 | 606 | # define R300_RS_ROUTE_0_COLOR_DEST_MASK (31 << 17) /* GUESS */ |
| 414ed537 DA |
607 | /* As above, but for secondary color */ |
| 608 | # define R300_RS_ROUTE_1_COLOR1 (1 << 14) | |
| 609 | # define R300_RS_ROUTE_1_COLOR1_DEST_SHIFT 17 | |
| 610 | # define R300_RS_ROUTE_1_COLOR1_DEST_MASK (31 << 17) | |
| 611 | # define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11) | |
| 612 | /* END */ | |
| 613 | ||
| 614 | /* BEGIN: Scissors and cliprects | |
| 615 | // There are four clipping rectangles. Their corner coordinates are inclusive. | |
| 616 | // Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending | |
| 617 | // on whether the pixel is inside cliprects 0-3, respectively. For example, | |
| 618 | // if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned | |
| 619 | // the number 3 (binary 0011). | |
| 620 | // Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set, | |
| 621 | // the pixel is rasterized. | |
| 622 | // | |
| 623 | // In addition to this, there is a scissors rectangle. Only pixels inside the | |
| 624 | // scissors rectangle are drawn. (coordinates are inclusive) | |
| 625 | // | |
| 626 | // For some reason, the top-left corner of the framebuffer is at (1440, 1440) | |
| 627 | // for the purpose of clipping and scissors. */ | |
| 628 | #define R300_RE_CLIPRECT_TL_0 0x43B0 | |
| 629 | #define R300_RE_CLIPRECT_BR_0 0x43B4 | |
| 630 | #define R300_RE_CLIPRECT_TL_1 0x43B8 | |
| 631 | #define R300_RE_CLIPRECT_BR_1 0x43BC | |
| 632 | #define R300_RE_CLIPRECT_TL_2 0x43C0 | |
| 633 | #define R300_RE_CLIPRECT_BR_2 0x43C4 | |
| 634 | #define R300_RE_CLIPRECT_TL_3 0x43C8 | |
| 635 | #define R300_RE_CLIPRECT_BR_3 0x43CC | |
| 636 | # define R300_CLIPRECT_OFFSET 1440 | |
| 637 | # define R300_CLIPRECT_MASK 0x1FFF | |
| 638 | # define R300_CLIPRECT_X_SHIFT 0 | |
| 639 | # define R300_CLIPRECT_X_MASK (0x1FFF << 0) | |
| 640 | # define R300_CLIPRECT_Y_SHIFT 13 | |
| 641 | # define R300_CLIPRECT_Y_MASK (0x1FFF << 13) | |
| 642 | #define R300_RE_CLIPRECT_CNTL 0x43D0 | |
| 643 | # define R300_CLIP_OUT (1 << 0) | |
| 644 | # define R300_CLIP_0 (1 << 1) | |
| 645 | # define R300_CLIP_1 (1 << 2) | |
| 646 | # define R300_CLIP_10 (1 << 3) | |
| 647 | # define R300_CLIP_2 (1 << 4) | |
| 648 | # define R300_CLIP_20 (1 << 5) | |
| 649 | # define R300_CLIP_21 (1 << 6) | |
| 650 | # define R300_CLIP_210 (1 << 7) | |
| 651 | # define R300_CLIP_3 (1 << 8) | |
| 652 | # define R300_CLIP_30 (1 << 9) | |
| 653 | # define R300_CLIP_31 (1 << 10) | |
| 654 | # define R300_CLIP_310 (1 << 11) | |
| 655 | # define R300_CLIP_32 (1 << 12) | |
| 656 | # define R300_CLIP_320 (1 << 13) | |
| 657 | # define R300_CLIP_321 (1 << 14) | |
| 658 | # define R300_CLIP_3210 (1 << 15) | |
| 659 | ||
| 660 | /* gap */ | |
| 661 | #define R300_RE_SCISSORS_TL 0x43E0 | |
| 662 | #define R300_RE_SCISSORS_BR 0x43E4 | |
| 663 | # define R300_SCISSORS_OFFSET 1440 | |
| 664 | # define R300_SCISSORS_X_SHIFT 0 | |
| 665 | # define R300_SCISSORS_X_MASK (0x1FFF << 0) | |
| 666 | # define R300_SCISSORS_Y_SHIFT 13 | |
| 667 | # define R300_SCISSORS_Y_MASK (0x1FFF << 13) | |
| 668 | /* END */ | |
| 669 | ||
| 670 | /* BEGIN: Texture specification | |
| 671 | // The texture specification dwords are grouped by meaning and not by texture unit. | |
| 672 | // This means that e.g. the offset for texture image unit N is found in register | |
| 673 | // TX_OFFSET_0 + (4*N) */ | |
| 674 | #define R300_TX_FILTER_0 0x4400 | |
| 675 | # define R300_TX_REPEAT 0 | |
| 676 | # define R300_TX_MIRRORED 1 | |
| 677 | # define R300_TX_CLAMP 4 | |
| 678 | # define R300_TX_CLAMP_TO_EDGE 2 | |
| 679 | # define R300_TX_CLAMP_TO_BORDER 6 | |
| 680 | # define R300_TX_WRAP_S_SHIFT 0 | |
| 681 | # define R300_TX_WRAP_S_MASK (7 << 0) | |
| 682 | # define R300_TX_WRAP_T_SHIFT 3 | |
| 683 | # define R300_TX_WRAP_T_MASK (7 << 3) | |
| 684 | # define R300_TX_WRAP_Q_SHIFT 6 | |
| 685 | # define R300_TX_WRAP_Q_MASK (7 << 6) | |
| 686 | # define R300_TX_MAG_FILTER_NEAREST (1 << 9) | |
| 687 | # define R300_TX_MAG_FILTER_LINEAR (2 << 9) | |
| 688 | # define R300_TX_MAG_FILTER_MASK (3 << 9) | |
| 689 | # define R300_TX_MIN_FILTER_NEAREST (1 << 11) | |
| 690 | # define R300_TX_MIN_FILTER_LINEAR (2 << 11) | |
| 691 | # define R300_TX_MIN_FILTER_NEAREST_MIP_NEAREST (5 << 11) | |
| 692 | # define R300_TX_MIN_FILTER_NEAREST_MIP_LINEAR (9 << 11) | |
| 693 | # define R300_TX_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 11) | |
| 694 | # define R300_TX_MIN_FILTER_LINEAR_MIP_LINEAR (10 << 11) | |
| 695 | ||
| 696 | /* NOTE: NEAREST doesnt seem to exist. | |
| 697 | Im not seting MAG_FILTER_MASK and (3 << 11) on for all | |
| 698 | anisotropy modes because that would void selected mag filter */ | |
| 699 | # define R300_TX_MIN_FILTER_ANISO_NEAREST ((0 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/) | |
| 700 | # define R300_TX_MIN_FILTER_ANISO_LINEAR ((0 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/) | |
| 701 | # define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST ((1 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/) | |
| 702 | # define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR ((2 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/) | |
| 703 | # define R300_TX_MIN_FILTER_MASK ( (15 << 11) | (3 << 13) ) | |
| 704 | # define R300_TX_MAX_ANISO_1_TO_1 (0 << 21) | |
| 705 | # define R300_TX_MAX_ANISO_2_TO_1 (2 << 21) | |
| 706 | # define R300_TX_MAX_ANISO_4_TO_1 (4 << 21) | |
| 707 | # define R300_TX_MAX_ANISO_8_TO_1 (6 << 21) | |
| 708 | # define R300_TX_MAX_ANISO_16_TO_1 (8 << 21) | |
| 709 | # define R300_TX_MAX_ANISO_MASK (14 << 21) | |
| 710 | ||
| 711 | #define R300_TX_UNK1_0 0x4440 | |
| 712 | # define R300_LOD_BIAS_MASK 0x1fff | |
| 713 | ||
| 714 | #define R300_TX_SIZE_0 0x4480 | |
| 715 | # define R300_TX_WIDTHMASK_SHIFT 0 | |
| 716 | # define R300_TX_WIDTHMASK_MASK (2047 << 0) | |
| 717 | # define R300_TX_HEIGHTMASK_SHIFT 11 | |
| 718 | # define R300_TX_HEIGHTMASK_MASK (2047 << 11) | |
| 719 | # define R300_TX_UNK23 (1 << 23) | |
| b5e89ed5 | 720 | # define R300_TX_SIZE_SHIFT 26 /* largest of width, height */ |
| 414ed537 DA |
721 | # define R300_TX_SIZE_MASK (15 << 26) |
| 722 | #define R300_TX_FORMAT_0 0x44C0 | |
| 723 | /* The interpretation of the format word by Wladimir van der Laan */ | |
| 724 | /* The X, Y, Z and W refer to the layout of the components. | |
| 725 | They are given meanings as R, G, B and Alpha by the swizzle | |
| 726 | specification */ | |
| 727 | # define R300_TX_FORMAT_X8 0x0 | |
| 728 | # define R300_TX_FORMAT_X16 0x1 | |
| 729 | # define R300_TX_FORMAT_Y4X4 0x2 | |
| 730 | # define R300_TX_FORMAT_Y8X8 0x3 | |
| 731 | # define R300_TX_FORMAT_Y16X16 0x4 | |
| 732 | # define R300_TX_FORMAT_Z3Y3X2 0x5 | |
| 733 | # define R300_TX_FORMAT_Z5Y6X5 0x6 | |
| 734 | # define R300_TX_FORMAT_Z6Y5X5 0x7 | |
| 735 | # define R300_TX_FORMAT_Z11Y11X10 0x8 | |
| 736 | # define R300_TX_FORMAT_Z10Y11X11 0x9 | |
| 737 | # define R300_TX_FORMAT_W4Z4Y4X4 0xA | |
| 738 | # define R300_TX_FORMAT_W1Z5Y5X5 0xB | |
| 739 | # define R300_TX_FORMAT_W8Z8Y8X8 0xC | |
| 740 | # define R300_TX_FORMAT_W2Z10Y10X10 0xD | |
| 741 | # define R300_TX_FORMAT_W16Z16Y16X16 0xE | |
| 742 | # define R300_TX_FORMAT_DXT1 0xF | |
| 743 | # define R300_TX_FORMAT_DXT3 0x10 | |
| 744 | # define R300_TX_FORMAT_DXT5 0x11 | |
| b5e89ed5 DA |
745 | # define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ |
| 746 | # define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ | |
| 747 | # define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ | |
| 748 | # define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ | |
| 414ed537 | 749 | /* 0x16 - some 16 bit green format.. ?? */ |
| b5e89ed5 | 750 | # define R300_TX_FORMAT_UNK25 (1 << 25) /* no swizzle */ |
| 414ed537 DA |
751 | |
| 752 | /* gap */ | |
| 753 | /* Floating point formats */ | |
| 754 | /* Note - hardware supports both 16 and 32 bit floating point */ | |
| 755 | # define R300_TX_FORMAT_FL_I16 0x18 | |
| 756 | # define R300_TX_FORMAT_FL_I16A16 0x19 | |
| 757 | # define R300_TX_FORMAT_FL_R16G16B16A16 0x1A | |
| 758 | # define R300_TX_FORMAT_FL_I32 0x1B | |
| 759 | # define R300_TX_FORMAT_FL_I32A32 0x1C | |
| 760 | # define R300_TX_FORMAT_FL_R32G32B32A32 0x1D | |
| 761 | /* alpha modes, convenience mostly */ | |
| 762 | /* if you have alpha, pick constant appropriate to the | |
| 763 | number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */ | |
| 764 | # define R300_TX_FORMAT_ALPHA_1CH 0x000 | |
| 765 | # define R300_TX_FORMAT_ALPHA_2CH 0x200 | |
| 766 | # define R300_TX_FORMAT_ALPHA_4CH 0x600 | |
| 767 | # define R300_TX_FORMAT_ALPHA_NONE 0xA00 | |
| 768 | /* Swizzling */ | |
| 769 | /* constants */ | |
| 770 | # define R300_TX_FORMAT_X 0 | |
| 771 | # define R300_TX_FORMAT_Y 1 | |
| 772 | # define R300_TX_FORMAT_Z 2 | |
| 773 | # define R300_TX_FORMAT_W 3 | |
| 774 | # define R300_TX_FORMAT_ZERO 4 | |
| 775 | # define R300_TX_FORMAT_ONE 5 | |
| b5e89ed5 DA |
776 | # define R300_TX_FORMAT_CUT_Z 6 /* 2.0*Z, everything above 1.0 is set to 0.0 */ |
| 777 | # define R300_TX_FORMAT_CUT_W 7 /* 2.0*W, everything above 1.0 is set to 0.0 */ | |
| 414ed537 DA |
778 | |
| 779 | # define R300_TX_FORMAT_B_SHIFT 18 | |
| 780 | # define R300_TX_FORMAT_G_SHIFT 15 | |
| 781 | # define R300_TX_FORMAT_R_SHIFT 12 | |
| 782 | # define R300_TX_FORMAT_A_SHIFT 9 | |
| 783 | /* Convenience macro to take care of layout and swizzling */ | |
| 784 | # define R300_EASY_TX_FORMAT(B, G, R, A, FMT) (\ | |
| 785 | ((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT) \ | |
| 786 | | ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT) \ | |
| 787 | | ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT) \ | |
| 788 | | ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT) \ | |
| 789 | | (R300_TX_FORMAT_##FMT) \ | |
| 790 | ) | |
| 791 | /* These can be ORed with result of R300_EASY_TX_FORMAT() */ | |
| 792 | /* We don't really know what they do. Take values from a constant color ? */ | |
| 793 | # define R300_TX_FORMAT_CONST_X (1<<5) | |
| 794 | # define R300_TX_FORMAT_CONST_Y (2<<5) | |
| 795 | # define R300_TX_FORMAT_CONST_Z (4<<5) | |
| 796 | # define R300_TX_FORMAT_CONST_W (8<<5) | |
| 797 | ||
| 798 | # define R300_TX_FORMAT_YUV_MODE 0x00800000 | |
| 799 | ||
| d985c108 | 800 | #define R300_TX_PITCH_0 0x4500 |
| 414ed537 DA |
801 | #define R300_TX_OFFSET_0 0x4540 |
| 802 | /* BEGIN: Guess from R200 */ | |
| 803 | # define R300_TXO_ENDIAN_NO_SWAP (0 << 0) | |
| 804 | # define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0) | |
| 805 | # define R300_TXO_ENDIAN_WORD_SWAP (2 << 0) | |
| 806 | # define R300_TXO_ENDIAN_HALFDW_SWAP (3 << 0) | |
| 807 | # define R300_TXO_OFFSET_MASK 0xffffffe0 | |
| 808 | # define R300_TXO_OFFSET_SHIFT 5 | |
| 809 | /* END */ | |
| 810 | #define R300_TX_UNK4_0 0x4580 | |
| b5e89ed5 | 811 | #define R300_TX_BORDER_COLOR_0 0x45C0 //ff00ff00 == { 0, 1.0, 0, 1.0 } |
| 414ed537 DA |
812 | |
| 813 | /* END */ | |
| 814 | ||
| 815 | /* BEGIN: Fragment program instruction set | |
| 816 | // Fragment programs are written directly into register space. | |
| 817 | // There are separate instruction streams for texture instructions and ALU | |
| 818 | // instructions. | |
| 819 | // In order to synchronize these streams, the program is divided into up | |
| 820 | // to 4 nodes. Each node begins with a number of TEX operations, followed | |
| 821 | // by a number of ALU operations. | |
| 822 | // The first node can have zero TEX ops, all subsequent nodes must have at least | |
| 823 | // one TEX ops. | |
| 824 | // All nodes must have at least one ALU op. | |
| 825 | // | |
| 826 | // The index of the last node is stored in PFS_CNTL_0: A value of 0 means | |
| 827 | // 1 node, a value of 3 means 4 nodes. | |
| 828 | // The total amount of instructions is defined in PFS_CNTL_2. The offsets are | |
| 829 | // offsets into the respective instruction streams, while *_END points to the | |
| 830 | // last instruction relative to this offset. */ | |
| 831 | #define R300_PFS_CNTL_0 0x4600 | |
| 832 | # define R300_PFS_CNTL_LAST_NODES_SHIFT 0 | |
| 833 | # define R300_PFS_CNTL_LAST_NODES_MASK (3 << 0) | |
| 834 | # define R300_PFS_CNTL_FIRST_NODE_HAS_TEX (1 << 3) | |
| 835 | #define R300_PFS_CNTL_1 0x4604 | |
| 836 | /* There is an unshifted value here which has so far always been equal to the | |
| 837 | // index of the highest used temporary register. */ | |
| 838 | #define R300_PFS_CNTL_2 0x4608 | |
| 839 | # define R300_PFS_CNTL_ALU_OFFSET_SHIFT 0 | |
| 840 | # define R300_PFS_CNTL_ALU_OFFSET_MASK (63 << 0) | |
| 841 | # define R300_PFS_CNTL_ALU_END_SHIFT 6 | |
| 842 | # define R300_PFS_CNTL_ALU_END_MASK (63 << 0) | |
| 843 | # define R300_PFS_CNTL_TEX_OFFSET_SHIFT 12 | |
| b5e89ed5 | 844 | # define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 12) /* GUESS */ |
| 414ed537 | 845 | # define R300_PFS_CNTL_TEX_END_SHIFT 18 |
| b5e89ed5 | 846 | # define R300_PFS_CNTL_TEX_END_MASK (31 << 18) /* GUESS */ |
| 414ed537 DA |
847 | |
| 848 | /* gap */ | |
| 849 | /* Nodes are stored backwards. The last active node is always stored in | |
| 850 | // PFS_NODE_3. | |
| 851 | // Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The | |
| 852 | // first node is stored in NODE_2, the second node is stored in NODE_3. | |
| 853 | // | |
| 854 | // Offsets are relative to the master offset from PFS_CNTL_2. | |
| 855 | // LAST_NODE is set for the last node, and only for the last node. */ | |
| 856 | #define R300_PFS_NODE_0 0x4610 | |
| 857 | #define R300_PFS_NODE_1 0x4614 | |
| 858 | #define R300_PFS_NODE_2 0x4618 | |
| 859 | #define R300_PFS_NODE_3 0x461C | |
| 860 | # define R300_PFS_NODE_ALU_OFFSET_SHIFT 0 | |
| 861 | # define R300_PFS_NODE_ALU_OFFSET_MASK (63 << 0) | |
| 862 | # define R300_PFS_NODE_ALU_END_SHIFT 6 | |
| 863 | # define R300_PFS_NODE_ALU_END_MASK (63 << 6) | |
| 864 | # define R300_PFS_NODE_TEX_OFFSET_SHIFT 12 | |
| 865 | # define R300_PFS_NODE_TEX_OFFSET_MASK (31 << 12) | |
| 866 | # define R300_PFS_NODE_TEX_END_SHIFT 17 | |
| 867 | # define R300_PFS_NODE_TEX_END_MASK (31 << 17) | |
| 868 | # define R300_PFS_NODE_LAST_NODE (1 << 22) | |
| 869 | ||
| 870 | /* TEX | |
| 871 | // As far as I can tell, texture instructions cannot write into output | |
| 872 | // registers directly. A subsequent ALU instruction is always necessary, | |
| 873 | // even if it's just MAD o0, r0, 1, 0 */ | |
| 874 | #define R300_PFS_TEXI_0 0x4620 | |
| 875 | # define R300_FPITX_SRC_SHIFT 0 | |
| 876 | # define R300_FPITX_SRC_MASK (31 << 0) | |
| b5e89ed5 | 877 | # define R300_FPITX_SRC_CONST (1 << 5) /* GUESS */ |
| 414ed537 DA |
878 | # define R300_FPITX_DST_SHIFT 6 |
| 879 | # define R300_FPITX_DST_MASK (31 << 6) | |
| 880 | # define R300_FPITX_IMAGE_SHIFT 11 | |
| b5e89ed5 | 881 | # define R300_FPITX_IMAGE_MASK (15 << 11) /* GUESS based on layout and native limits */ |
| 414ed537 DA |
882 | /* Unsure if these are opcodes, or some kind of bitfield, but this is how |
| 883 | * they were set when I checked | |
| 884 | */ | |
| 885 | # define R300_FPITX_OPCODE_SHIFT 15 | |
| 886 | # define R300_FPITX_OP_TEX 1 | |
| 887 | # define R300_FPITX_OP_TXP 3 | |
| 888 | # define R300_FPITX_OP_TXB 4 | |
| 889 | ||
| 890 | /* ALU | |
| 891 | // The ALU instructions register blocks are enumerated according to the order | |
| 892 | // in which fglrx. I assume there is space for 64 instructions, since | |
| 893 | // each block has space for a maximum of 64 DWORDs, and this matches reported | |
| 894 | // native limits. | |
| 895 | // | |
| 896 | // The basic functional block seems to be one MAD for each color and alpha, | |
| 897 | // and an adder that adds all components after the MUL. | |
| 898 | // - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands | |
| 899 | // - DP4: Use OUTC_DP4, OUTA_DP4 | |
| 900 | // - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands | |
| 901 | // - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands | |
| 902 | // - CMP: If ARG2 < 0, return ARG1, else return ARG0 | |
| 903 | // - FLR: use FRC+MAD | |
| 904 | // - XPD: use MAD+MAD | |
| 905 | // - SGE, SLT: use MAD+CMP | |
| 906 | // - RSQ: use ABS modifier for argument | |
| 907 | // - Use OUTC_REPL_ALPHA to write results of an alpha-only operation (e.g. RCP) | |
| 908 | // into color register | |
| 909 | // - apparently, there's no quick DST operation | |
| 910 | // - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2" | |
| 911 | // - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0" | |
| 912 | // - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1" | |
| 913 | // | |
| 914 | // Operand selection | |
| 915 | // First stage selects three sources from the available registers and | |
| 916 | // constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha). | |
| 917 | // fglrx sorts the three source fields: Registers before constants, | |
| 918 | // lower indices before higher indices; I do not know whether this is necessary. | |
| 919 | // fglrx fills unused sources with "read constant 0" | |
| 920 | // According to specs, you cannot select more than two different constants. | |
| 921 | // | |
| 922 | // Second stage selects the operands from the sources. This is defined in | |
| 923 | // INSTR0 (color) and INSTR2 (alpha). You can also select the special constants | |
| 924 | // zero and one. | |
| 925 | // Swizzling and negation happens in this stage, as well. | |
| 926 | // | |
| 927 | // Important: Color and alpha seem to be mostly separate, i.e. their sources | |
| 928 | // selection appears to be fully independent (the register storage is probably | |
| 929 | // physically split into a color and an alpha section). | |
| 930 | // However (because of the apparent physical split), there is some interaction | |
| 931 | // WRT swizzling. If, for example, you want to load an R component into an | |
| 932 | // Alpha operand, this R component is taken from a *color* source, not from | |
| 933 | // an alpha source. The corresponding register doesn't even have to appear in | |
| 934 | // the alpha sources list. (I hope this alll makes sense to you) | |
| 935 | // | |
| 936 | // Destination selection | |
| 937 | // The destination register index is in FPI1 (color) and FPI3 (alpha) together | |
| 938 | // with enable bits. | |
| 939 | // There are separate enable bits for writing into temporary registers | |
| 940 | // (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_* /DSTA_OUTPUT). | |
| 941 | // You can write to both at once, or not write at all (the same index | |
| 942 | // must be used for both). | |
| 943 | // | |
| 944 | // Note: There is a special form for LRP | |
| 945 | // - Argument order is the same as in ARB_fragment_program. | |
| 946 | // - Operation is MAD | |
| 947 | // - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP | |
| 948 | // - Set FPI0/FPI2_SPECIAL_LRP | |
| 949 | // Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD */ | |
| 950 | #define R300_PFS_INSTR1_0 0x46C0 | |
| 951 | # define R300_FPI1_SRC0C_SHIFT 0 | |
| 952 | # define R300_FPI1_SRC0C_MASK (31 << 0) | |
| 953 | # define R300_FPI1_SRC0C_CONST (1 << 5) | |
| 954 | # define R300_FPI1_SRC1C_SHIFT 6 | |
| 955 | # define R300_FPI1_SRC1C_MASK (31 << 6) | |
| 956 | # define R300_FPI1_SRC1C_CONST (1 << 11) | |
| 957 | # define R300_FPI1_SRC2C_SHIFT 12 | |
| 958 | # define R300_FPI1_SRC2C_MASK (31 << 12) | |
| 959 | # define R300_FPI1_SRC2C_CONST (1 << 17) | |
| 960 | # define R300_FPI1_DSTC_SHIFT 18 | |
| 961 | # define R300_FPI1_DSTC_MASK (31 << 18) | |
| 962 | # define R300_FPI1_DSTC_REG_X (1 << 23) | |
| 963 | # define R300_FPI1_DSTC_REG_Y (1 << 24) | |
| 964 | # define R300_FPI1_DSTC_REG_Z (1 << 25) | |
| 965 | # define R300_FPI1_DSTC_OUTPUT_X (1 << 26) | |
| 966 | # define R300_FPI1_DSTC_OUTPUT_Y (1 << 27) | |
| 967 | # define R300_FPI1_DSTC_OUTPUT_Z (1 << 28) | |
| 968 | ||
| 969 | #define R300_PFS_INSTR3_0 0x47C0 | |
| 970 | # define R300_FPI3_SRC0A_SHIFT 0 | |
| 971 | # define R300_FPI3_SRC0A_MASK (31 << 0) | |
| 972 | # define R300_FPI3_SRC0A_CONST (1 << 5) | |
| 973 | # define R300_FPI3_SRC1A_SHIFT 6 | |
| 974 | # define R300_FPI3_SRC1A_MASK (31 << 6) | |
| 975 | # define R300_FPI3_SRC1A_CONST (1 << 11) | |
| 976 | # define R300_FPI3_SRC2A_SHIFT 12 | |
| 977 | # define R300_FPI3_SRC2A_MASK (31 << 12) | |
| 978 | # define R300_FPI3_SRC2A_CONST (1 << 17) | |
| 979 | # define R300_FPI3_DSTA_SHIFT 18 | |
| 980 | # define R300_FPI3_DSTA_MASK (31 << 18) | |
| 981 | # define R300_FPI3_DSTA_REG (1 << 23) | |
| 982 | # define R300_FPI3_DSTA_OUTPUT (1 << 24) | |
| 983 | ||
| 984 | #define R300_PFS_INSTR0_0 0x48C0 | |
| 985 | # define R300_FPI0_ARGC_SRC0C_XYZ 0 | |
| 986 | # define R300_FPI0_ARGC_SRC0C_XXX 1 | |
| 987 | # define R300_FPI0_ARGC_SRC0C_YYY 2 | |
| 988 | # define R300_FPI0_ARGC_SRC0C_ZZZ 3 | |
| 989 | # define R300_FPI0_ARGC_SRC1C_XYZ 4 | |
| 990 | # define R300_FPI0_ARGC_SRC1C_XXX 5 | |
| 991 | # define R300_FPI0_ARGC_SRC1C_YYY 6 | |
| 992 | # define R300_FPI0_ARGC_SRC1C_ZZZ 7 | |
| 993 | # define R300_FPI0_ARGC_SRC2C_XYZ 8 | |
| 994 | # define R300_FPI0_ARGC_SRC2C_XXX 9 | |
| 995 | # define R300_FPI0_ARGC_SRC2C_YYY 10 | |
| 996 | # define R300_FPI0_ARGC_SRC2C_ZZZ 11 | |
| 997 | # define R300_FPI0_ARGC_SRC0A 12 | |
| 998 | # define R300_FPI0_ARGC_SRC1A 13 | |
| 999 | # define R300_FPI0_ARGC_SRC2A 14 | |
| 1000 | # define R300_FPI0_ARGC_SRC1C_LRP 15 | |
| 1001 | # define R300_FPI0_ARGC_ZERO 20 | |
| 1002 | # define R300_FPI0_ARGC_ONE 21 | |
| b5e89ed5 | 1003 | # define R300_FPI0_ARGC_HALF 22 /* GUESS */ |
| 414ed537 DA |
1004 | # define R300_FPI0_ARGC_SRC0C_YZX 23 |
| 1005 | # define R300_FPI0_ARGC_SRC1C_YZX 24 | |
| 1006 | # define R300_FPI0_ARGC_SRC2C_YZX 25 | |
| 1007 | # define R300_FPI0_ARGC_SRC0C_ZXY 26 | |
| 1008 | # define R300_FPI0_ARGC_SRC1C_ZXY 27 | |
| 1009 | # define R300_FPI0_ARGC_SRC2C_ZXY 28 | |
| 1010 | # define R300_FPI0_ARGC_SRC0CA_WZY 29 | |
| 1011 | # define R300_FPI0_ARGC_SRC1CA_WZY 30 | |
| 1012 | # define R300_FPI0_ARGC_SRC2CA_WZY 31 | |
| 1013 | ||
| 1014 | # define R300_FPI0_ARG0C_SHIFT 0 | |
| 1015 | # define R300_FPI0_ARG0C_MASK (31 << 0) | |
| 1016 | # define R300_FPI0_ARG0C_NEG (1 << 5) | |
| 1017 | # define R300_FPI0_ARG0C_ABS (1 << 6) | |
| 1018 | # define R300_FPI0_ARG1C_SHIFT 7 | |
| 1019 | # define R300_FPI0_ARG1C_MASK (31 << 7) | |
| 1020 | # define R300_FPI0_ARG1C_NEG (1 << 12) | |
| 1021 | # define R300_FPI0_ARG1C_ABS (1 << 13) | |
| 1022 | # define R300_FPI0_ARG2C_SHIFT 14 | |
| 1023 | # define R300_FPI0_ARG2C_MASK (31 << 14) | |
| 1024 | # define R300_FPI0_ARG2C_NEG (1 << 19) | |
| 1025 | # define R300_FPI0_ARG2C_ABS (1 << 20) | |
| 1026 | # define R300_FPI0_SPECIAL_LRP (1 << 21) | |
| 1027 | # define R300_FPI0_OUTC_MAD (0 << 23) | |
| 1028 | # define R300_FPI0_OUTC_DP3 (1 << 23) | |
| 1029 | # define R300_FPI0_OUTC_DP4 (2 << 23) | |
| 1030 | # define R300_FPI0_OUTC_MIN (4 << 23) | |
| 1031 | # define R300_FPI0_OUTC_MAX (5 << 23) | |
| 1032 | # define R300_FPI0_OUTC_CMP (8 << 23) | |
| 1033 | # define R300_FPI0_OUTC_FRC (9 << 23) | |
| 1034 | # define R300_FPI0_OUTC_REPL_ALPHA (10 << 23) | |
| 1035 | # define R300_FPI0_OUTC_SAT (1 << 30) | |
| 1036 | # define R300_FPI0_UNKNOWN_31 (1 << 31) | |
| 1037 | ||
| 1038 | #define R300_PFS_INSTR2_0 0x49C0 | |
| 1039 | # define R300_FPI2_ARGA_SRC0C_X 0 | |
| 1040 | # define R300_FPI2_ARGA_SRC0C_Y 1 | |
| 1041 | # define R300_FPI2_ARGA_SRC0C_Z 2 | |
| 1042 | # define R300_FPI2_ARGA_SRC1C_X 3 | |
| 1043 | # define R300_FPI2_ARGA_SRC1C_Y 4 | |
| 1044 | # define R300_FPI2_ARGA_SRC1C_Z 5 | |
| 1045 | # define R300_FPI2_ARGA_SRC2C_X 6 | |
| 1046 | # define R300_FPI2_ARGA_SRC2C_Y 7 | |
| 1047 | # define R300_FPI2_ARGA_SRC2C_Z 8 | |
| 1048 | # define R300_FPI2_ARGA_SRC0A 9 | |
| 1049 | # define R300_FPI2_ARGA_SRC1A 10 | |
| 1050 | # define R300_FPI2_ARGA_SRC2A 11 | |
| 1051 | # define R300_FPI2_ARGA_SRC1A_LRP 15 | |
| 1052 | # define R300_FPI2_ARGA_ZERO 16 | |
| 1053 | # define R300_FPI2_ARGA_ONE 17 | |
| b5e89ed5 | 1054 | # define R300_FPI2_ARGA_HALF 18 /* GUESS */ |
| 414ed537 DA |
1055 | |
| 1056 | # define R300_FPI2_ARG0A_SHIFT 0 | |
| 1057 | # define R300_FPI2_ARG0A_MASK (31 << 0) | |
| 1058 | # define R300_FPI2_ARG0A_NEG (1 << 5) | |
| b5e89ed5 | 1059 | # define R300_FPI2_ARG0A_ABS (1 << 6) /* GUESS */ |
| 414ed537 DA |
1060 | # define R300_FPI2_ARG1A_SHIFT 7 |
| 1061 | # define R300_FPI2_ARG1A_MASK (31 << 7) | |
| 1062 | # define R300_FPI2_ARG1A_NEG (1 << 12) | |
| b5e89ed5 | 1063 | # define R300_FPI2_ARG1A_ABS (1 << 13) /* GUESS */ |
| 414ed537 DA |
1064 | # define R300_FPI2_ARG2A_SHIFT 14 |
| 1065 | # define R300_FPI2_ARG2A_MASK (31 << 14) | |
| 1066 | # define R300_FPI2_ARG2A_NEG (1 << 19) | |
| b5e89ed5 | 1067 | # define R300_FPI2_ARG2A_ABS (1 << 20) /* GUESS */ |
| 414ed537 DA |
1068 | # define R300_FPI2_SPECIAL_LRP (1 << 21) |
| 1069 | # define R300_FPI2_OUTA_MAD (0 << 23) | |
| 1070 | # define R300_FPI2_OUTA_DP4 (1 << 23) | |
| 1071 | # define R300_FPI2_OUTA_MIN (2 << 23) | |
| 1072 | # define R300_FPI2_OUTA_MAX (3 << 23) | |
| 1073 | # define R300_FPI2_OUTA_CMP (6 << 23) | |
| 1074 | # define R300_FPI2_OUTA_FRC (7 << 23) | |
| 1075 | # define R300_FPI2_OUTA_EX2 (8 << 23) | |
| 1076 | # define R300_FPI2_OUTA_LG2 (9 << 23) | |
| 1077 | # define R300_FPI2_OUTA_RCP (10 << 23) | |
| 1078 | # define R300_FPI2_OUTA_RSQ (11 << 23) | |
| 1079 | # define R300_FPI2_OUTA_SAT (1 << 30) | |
| 1080 | # define R300_FPI2_UNKNOWN_31 (1 << 31) | |
| 1081 | /* END */ | |
| 1082 | ||
| 1083 | /* gap */ | |
| 1084 | #define R300_PP_ALPHA_TEST 0x4BD4 | |
| 1085 | # define R300_REF_ALPHA_MASK 0x000000ff | |
| 1086 | # define R300_ALPHA_TEST_FAIL (0 << 8) | |
| 1087 | # define R300_ALPHA_TEST_LESS (1 << 8) | |
| 1088 | # define R300_ALPHA_TEST_LEQUAL (3 << 8) | |
| 1089 | # define R300_ALPHA_TEST_EQUAL (2 << 8) | |
| 1090 | # define R300_ALPHA_TEST_GEQUAL (6 << 8) | |
| 1091 | # define R300_ALPHA_TEST_GREATER (4 << 8) | |
| 1092 | # define R300_ALPHA_TEST_NEQUAL (5 << 8) | |
| 1093 | # define R300_ALPHA_TEST_PASS (7 << 8) | |
| 1094 | # define R300_ALPHA_TEST_OP_MASK (7 << 8) | |
| 1095 | # define R300_ALPHA_TEST_ENABLE (1 << 11) | |
| 1096 | ||
| 1097 | /* gap */ | |
| 1098 | /* Fragment program parameters in 7.16 floating point */ | |
| 1099 | #define R300_PFS_PARAM_0_X 0x4C00 | |
| 1100 | #define R300_PFS_PARAM_0_Y 0x4C04 | |
| 1101 | #define R300_PFS_PARAM_0_Z 0x4C08 | |
| 1102 | #define R300_PFS_PARAM_0_W 0x4C0C | |
| 1103 | /* GUESS: PARAM_31 is last, based on native limits reported by fglrx */ | |
| 1104 | #define R300_PFS_PARAM_31_X 0x4DF0 | |
| 1105 | #define R300_PFS_PARAM_31_Y 0x4DF4 | |
| 1106 | #define R300_PFS_PARAM_31_Z 0x4DF8 | |
| 1107 | #define R300_PFS_PARAM_31_W 0x4DFC | |
| 1108 | ||
| 1109 | /* Notes: | |
| 1110 | // - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in the application | |
| 1111 | // - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND are set to the same | |
| 1112 | // function (both registers are always set up completely in any case) | |
| 1113 | // - Most blend flags are simply copied from R200 and not tested yet */ | |
| 1114 | #define R300_RB3D_CBLEND 0x4E04 | |
| 1115 | #define R300_RB3D_ABLEND 0x4E08 | |
| 1116 | /* the following only appear in CBLEND */ | |
| 1117 | # define R300_BLEND_ENABLE (1 << 0) | |
| 1118 | # define R300_BLEND_UNKNOWN (3 << 1) | |
| 1119 | # define R300_BLEND_NO_SEPARATE (1 << 3) | |
| 1120 | /* the following are shared between CBLEND and ABLEND */ | |
| 1121 | # define R300_FCN_MASK (3 << 12) | |
| 1122 | # define R300_COMB_FCN_ADD_CLAMP (0 << 12) | |
| 1123 | # define R300_COMB_FCN_ADD_NOCLAMP (1 << 12) | |
| 1124 | # define R300_COMB_FCN_SUB_CLAMP (2 << 12) | |
| 1125 | # define R300_COMB_FCN_SUB_NOCLAMP (3 << 12) | |
| 1126 | # define R300_SRC_BLEND_GL_ZERO (32 << 16) | |
| 1127 | # define R300_SRC_BLEND_GL_ONE (33 << 16) | |
| 1128 | # define R300_SRC_BLEND_GL_SRC_COLOR (34 << 16) | |
| 1129 | # define R300_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16) | |
| 1130 | # define R300_SRC_BLEND_GL_DST_COLOR (36 << 16) | |
| 1131 | # define R300_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16) | |
| 1132 | # define R300_SRC_BLEND_GL_SRC_ALPHA (38 << 16) | |
| 1133 | # define R300_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16) | |
| 1134 | # define R300_SRC_BLEND_GL_DST_ALPHA (40 << 16) | |
| 1135 | # define R300_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16) | |
| 1136 | # define R300_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16) | |
| 1137 | # define R300_SRC_BLEND_MASK (63 << 16) | |
| 1138 | # define R300_DST_BLEND_GL_ZERO (32 << 24) | |
| 1139 | # define R300_DST_BLEND_GL_ONE (33 << 24) | |
| 1140 | # define R300_DST_BLEND_GL_SRC_COLOR (34 << 24) | |
| 1141 | # define R300_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24) | |
| 1142 | # define R300_DST_BLEND_GL_DST_COLOR (36 << 24) | |
| 1143 | # define R300_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24) | |
| 1144 | # define R300_DST_BLEND_GL_SRC_ALPHA (38 << 24) | |
| 1145 | # define R300_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24) | |
| 1146 | # define R300_DST_BLEND_GL_DST_ALPHA (40 << 24) | |
| 1147 | # define R300_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24) | |
| 1148 | # define R300_DST_BLEND_MASK (63 << 24) | |
| 1149 | #define R300_RB3D_COLORMASK 0x4E0C | |
| 1150 | # define R300_COLORMASK0_B (1<<0) | |
| 1151 | # define R300_COLORMASK0_G (1<<1) | |
| 1152 | # define R300_COLORMASK0_R (1<<2) | |
| 1153 | # define R300_COLORMASK0_A (1<<3) | |
| 1154 | ||
| 1155 | /* gap */ | |
| 1156 | #define R300_RB3D_COLOROFFSET0 0x4E28 | |
| b5e89ed5 DA |
1157 | # define R300_COLOROFFSET_MASK 0xFFFFFFF0 /* GUESS */ |
| 1158 | #define R300_RB3D_COLOROFFSET1 0x4E2C /* GUESS */ | |
| 1159 | #define R300_RB3D_COLOROFFSET2 0x4E30 /* GUESS */ | |
| 1160 | #define R300_RB3D_COLOROFFSET3 0x4E34 /* GUESS */ | |
| 414ed537 DA |
1161 | /* gap */ |
| 1162 | /* Bit 16: Larger tiles | |
| 1163 | // Bit 17: 4x2 tiles | |
| 1164 | // Bit 18: Extremely weird tile like, but some pixels duplicated? */ | |
| 1165 | #define R300_RB3D_COLORPITCH0 0x4E38 | |
| b5e89ed5 DA |
1166 | # define R300_COLORPITCH_MASK 0x00001FF8 /* GUESS */ |
| 1167 | # define R300_COLOR_TILE_ENABLE (1 << 16) /* GUESS */ | |
| 1168 | # define R300_COLOR_MICROTILE_ENABLE (1 << 17) /* GUESS */ | |
| 1169 | # define R300_COLOR_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ | |
| 1170 | # define R300_COLOR_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ | |
| 1171 | # define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ | |
| 414ed537 DA |
1172 | # define R300_COLOR_FORMAT_RGB565 (2 << 22) |
| 1173 | # define R300_COLOR_FORMAT_ARGB8888 (3 << 22) | |
| b5e89ed5 DA |
1174 | #define R300_RB3D_COLORPITCH1 0x4E3C /* GUESS */ |
| 1175 | #define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */ | |
| 1176 | #define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */ | |
| 414ed537 DA |
1177 | |
| 1178 | /* gap */ | |
| 1179 | /* Guess by Vladimir. | |
| 1180 | // Set to 0A before 3D operations, set to 02 afterwards. */ | |
| 1181 | #define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C | |
| 1182 | # define R300_RB3D_DSTCACHE_02 0x00000002 | |
| 1183 | # define R300_RB3D_DSTCACHE_0A 0x0000000A | |
| 1184 | ||
| 1185 | /* gap */ | |
| 1186 | /* There seems to be no "write only" setting, so use Z-test = ALWAYS for this. */ | |
| 1187 | /* Bit (1<<8) is the "test" bit. so plain write is 6 - vd */ | |
| 1188 | #define R300_RB3D_ZSTENCIL_CNTL_0 0x4F00 | |
| b5e89ed5 DA |
1189 | # define R300_RB3D_Z_DISABLED_1 0x00000010 /* GUESS */ |
| 1190 | # define R300_RB3D_Z_DISABLED_2 0x00000014 /* GUESS */ | |
| 414ed537 DA |
1191 | # define R300_RB3D_Z_TEST 0x00000012 |
| 1192 | # define R300_RB3D_Z_TEST_AND_WRITE 0x00000016 | |
| 1193 | # define R300_RB3D_Z_WRITE_ONLY 0x00000006 | |
| 1194 | ||
| 1195 | # define R300_RB3D_Z_TEST 0x00000012 | |
| 1196 | # define R300_RB3D_Z_TEST_AND_WRITE 0x00000016 | |
| 1197 | # define R300_RB3D_Z_WRITE_ONLY 0x00000006 | |
| 1198 | # define R300_RB3D_STENCIL_ENABLE 0x00000001 | |
| 1199 | ||
| 1200 | #define R300_RB3D_ZSTENCIL_CNTL_1 0x4F04 | |
| 1201 | /* functions */ | |
| 1202 | # define R300_ZS_NEVER 0 | |
| 1203 | # define R300_ZS_LESS 1 | |
| 1204 | # define R300_ZS_LEQUAL 2 | |
| 1205 | # define R300_ZS_EQUAL 3 | |
| 1206 | # define R300_ZS_GEQUAL 4 | |
| 1207 | # define R300_ZS_GREATER 5 | |
| 1208 | # define R300_ZS_NOTEQUAL 6 | |
| 1209 | # define R300_ZS_ALWAYS 7 | |
| 1210 | # define R300_ZS_MASK 7 | |
| 1211 | /* operations */ | |
| 1212 | # define R300_ZS_KEEP 0 | |
| 1213 | # define R300_ZS_ZERO 1 | |
| 1214 | # define R300_ZS_REPLACE 2 | |
| 1215 | # define R300_ZS_INCR 3 | |
| 1216 | # define R300_ZS_DECR 4 | |
| 1217 | # define R300_ZS_INVERT 5 | |
| 1218 | # define R300_ZS_INCR_WRAP 6 | |
| 1219 | # define R300_ZS_DECR_WRAP 7 | |
| 1220 | ||
| 1221 | /* front and back refer to operations done for front | |
| 1222 | and back faces, i.e. separate stencil function support */ | |
| 1223 | # define R300_RB3D_ZS1_DEPTH_FUNC_SHIFT 0 | |
| 1224 | # define R300_RB3D_ZS1_FRONT_FUNC_SHIFT 3 | |
| 1225 | # define R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT 6 | |
| 1226 | # define R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT 9 | |
| 1227 | # define R300_RB3D_ZS1_FRONT_ZFAIL_OP_SHIFT 12 | |
| 1228 | # define R300_RB3D_ZS1_BACK_FUNC_SHIFT 15 | |
| 1229 | # define R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT 18 | |
| 1230 | # define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT 21 | |
| 1231 | # define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT 24 | |
| 1232 | ||
| 414ed537 DA |
1233 | #define R300_RB3D_ZSTENCIL_CNTL_2 0x4F08 |
| 1234 | # define R300_RB3D_ZS2_STENCIL_REF_SHIFT 0 | |
| 1235 | # define R300_RB3D_ZS2_STENCIL_MASK 0xFF | |
| 1236 | # define R300_RB3D_ZS2_STENCIL_MASK_SHIFT 8 | |
| 1237 | # define R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT 16 | |
| 1238 | ||
| 1239 | /* gap */ | |
| 1240 | ||
| 1241 | #define R300_RB3D_ZSTENCIL_FORMAT 0x4F10 | |
| 1242 | # define R300_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) | |
| 1243 | # define R300_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) | |
| 1244 | ||
| 1245 | /* gap */ | |
| 1246 | #define R300_RB3D_DEPTHOFFSET 0x4F20 | |
| 1247 | #define R300_RB3D_DEPTHPITCH 0x4F24 | |
| b5e89ed5 DA |
1248 | # define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */ |
| 1249 | # define R300_DEPTH_TILE_ENABLE (1 << 16) /* GUESS */ | |
| 1250 | # define R300_DEPTH_MICROTILE_ENABLE (1 << 17) /* GUESS */ | |
| 1251 | # define R300_DEPTH_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ | |
| 1252 | # define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ | |
| 1253 | # define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ | |
| 414ed537 DA |
1254 | |
| 1255 | /* BEGIN: Vertex program instruction set | |
| 1256 | // Every instruction is four dwords long: | |
| 1257 | // DWORD 0: output and opcode | |
| 1258 | // DWORD 1: first argument | |
| 1259 | // DWORD 2: second argument | |
| 1260 | // DWORD 3: third argument | |
| 1261 | // | |
| 1262 | // Notes: | |
| 1263 | // - ABS r, a is implemented as MAX r, a, -a | |
| 1264 | // - MOV is implemented as ADD to zero | |
| 1265 | // - XPD is implemented as MUL + MAD | |
| 1266 | // - FLR is implemented as FRC + ADD | |
| 1267 | // - apparently, fglrx tries to schedule instructions so that there is at least | |
| 1268 | // one instruction between the write to a temporary and the first read | |
| 1269 | // from said temporary; however, violations of this scheduling are allowed | |
| 1270 | // - register indices seem to be unrelated with OpenGL aliasing to conventional state | |
| 1271 | // - only one attribute and one parameter can be loaded at a time; however, the | |
| 1272 | // same attribute/parameter can be used for more than one argument | |
| 1273 | // - the second software argument for POW is the third hardware argument (no idea why) | |
| 1274 | // - MAD with only temporaries as input seems to use VPI_OUT_SELECT_MAD_2 | |
| 1275 | // | |
| 1276 | // There is some magic surrounding LIT: | |
| 1277 | // The single argument is replicated across all three inputs, but swizzled: | |
| 1278 | // First argument: xyzy | |
| 1279 | // Second argument: xyzx | |
| 1280 | // Third argument: xyzw | |
| 1281 | // Whenever the result is used later in the fragment program, fglrx forces x and w | |
| 1282 | // to be 1.0 in the input selection; I don't know whether this is strictly necessary */ | |
| 1283 | #define R300_VPI_OUT_OP_DOT (1 << 0) | |
| 1284 | #define R300_VPI_OUT_OP_MUL (2 << 0) | |
| 1285 | #define R300_VPI_OUT_OP_ADD (3 << 0) | |
| 1286 | #define R300_VPI_OUT_OP_MAD (4 << 0) | |
| 1287 | #define R300_VPI_OUT_OP_DST (5 << 0) | |
| 1288 | #define R300_VPI_OUT_OP_FRC (6 << 0) | |
| 1289 | #define R300_VPI_OUT_OP_MAX (7 << 0) | |
| 1290 | #define R300_VPI_OUT_OP_MIN (8 << 0) | |
| 1291 | #define R300_VPI_OUT_OP_SGE (9 << 0) | |
| 1292 | #define R300_VPI_OUT_OP_SLT (10 << 0) | |
| b5e89ed5 | 1293 | #define R300_VPI_OUT_OP_UNK12 (12 << 0) /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, vector(scalar, vector) */ |
| 414ed537 DA |
1294 | #define R300_VPI_OUT_OP_EXP (65 << 0) |
| 1295 | #define R300_VPI_OUT_OP_LOG (66 << 0) | |
| b5e89ed5 | 1296 | #define R300_VPI_OUT_OP_UNK67 (67 << 0) /* Used in fog computations, scalar(scalar) */ |
| 414ed537 DA |
1297 | #define R300_VPI_OUT_OP_LIT (68 << 0) |
| 1298 | #define R300_VPI_OUT_OP_POW (69 << 0) | |
| 1299 | #define R300_VPI_OUT_OP_RCP (70 << 0) | |
| 1300 | #define R300_VPI_OUT_OP_RSQ (72 << 0) | |
| b5e89ed5 | 1301 | #define R300_VPI_OUT_OP_UNK73 (73 << 0) /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, scalar(scalar) */ |
| 414ed537 DA |
1302 | #define R300_VPI_OUT_OP_EX2 (75 << 0) |
| 1303 | #define R300_VPI_OUT_OP_LG2 (76 << 0) | |
| 1304 | #define R300_VPI_OUT_OP_MAD_2 (128 << 0) | |
| b5e89ed5 | 1305 | #define R300_VPI_OUT_OP_UNK129 (129 << 0) /* all temps, vector(scalar, vector, vector) */ |
| 414ed537 DA |
1306 | |
| 1307 | #define R300_VPI_OUT_REG_CLASS_TEMPORARY (0 << 8) | |
| 1308 | #define R300_VPI_OUT_REG_CLASS_RESULT (2 << 8) | |
| 1309 | #define R300_VPI_OUT_REG_CLASS_MASK (31 << 8) | |
| 1310 | ||
| 1311 | #define R300_VPI_OUT_REG_INDEX_SHIFT 13 | |
| b5e89ed5 | 1312 | #define R300_VPI_OUT_REG_INDEX_MASK (31 << 13) /* GUESS based on fglrx native limits */ |
| 414ed537 DA |
1313 | |
| 1314 | #define R300_VPI_OUT_WRITE_X (1 << 20) | |
| 1315 | #define R300_VPI_OUT_WRITE_Y (1 << 21) | |
| 1316 | #define R300_VPI_OUT_WRITE_Z (1 << 22) | |
| 1317 | #define R300_VPI_OUT_WRITE_W (1 << 23) | |
| 1318 | ||
| 1319 | #define R300_VPI_IN_REG_CLASS_TEMPORARY (0 << 0) | |
| 1320 | #define R300_VPI_IN_REG_CLASS_ATTRIBUTE (1 << 0) | |
| 1321 | #define R300_VPI_IN_REG_CLASS_PARAMETER (2 << 0) | |
| 1322 | #define R300_VPI_IN_REG_CLASS_NONE (9 << 0) | |
| b5e89ed5 | 1323 | #define R300_VPI_IN_REG_CLASS_MASK (31 << 0) /* GUESS */ |
| 414ed537 DA |
1324 | |
| 1325 | #define R300_VPI_IN_REG_INDEX_SHIFT 5 | |
| b5e89ed5 | 1326 | #define R300_VPI_IN_REG_INDEX_MASK (255 << 5) /* GUESS based on fglrx native limits */ |
| 414ed537 DA |
1327 | |
| 1328 | /* The R300 can select components from the input register arbitrarily. | |
| 1329 | // Use the following constants, shifted by the component shift you | |
| 1330 | // want to select */ | |
| 1331 | #define R300_VPI_IN_SELECT_X 0 | |
| 1332 | #define R300_VPI_IN_SELECT_Y 1 | |
| 1333 | #define R300_VPI_IN_SELECT_Z 2 | |
| 1334 | #define R300_VPI_IN_SELECT_W 3 | |
| 1335 | #define R300_VPI_IN_SELECT_ZERO 4 | |
| 1336 | #define R300_VPI_IN_SELECT_ONE 5 | |
| 1337 | #define R300_VPI_IN_SELECT_MASK 7 | |
| 1338 | ||
| 1339 | #define R300_VPI_IN_X_SHIFT 13 | |
| 1340 | #define R300_VPI_IN_Y_SHIFT 16 | |
| 1341 | #define R300_VPI_IN_Z_SHIFT 19 | |
| 1342 | #define R300_VPI_IN_W_SHIFT 22 | |
| 1343 | ||
| 1344 | #define R300_VPI_IN_NEG_X (1 << 25) | |
| 1345 | #define R300_VPI_IN_NEG_Y (1 << 26) | |
| 1346 | #define R300_VPI_IN_NEG_Z (1 << 27) | |
| 1347 | #define R300_VPI_IN_NEG_W (1 << 28) | |
| 1348 | /* END */ | |
| 1349 | ||
| 1350 | //BEGIN: Packet 3 commands | |
| 1351 | ||
| 1352 | // A primitive emission dword. | |
| 1353 | #define R300_PRIM_TYPE_NONE (0 << 0) | |
| 1354 | #define R300_PRIM_TYPE_POINT (1 << 0) | |
| 1355 | #define R300_PRIM_TYPE_LINE (2 << 0) | |
| 1356 | #define R300_PRIM_TYPE_LINE_STRIP (3 << 0) | |
| 1357 | #define R300_PRIM_TYPE_TRI_LIST (4 << 0) | |
| 1358 | #define R300_PRIM_TYPE_TRI_FAN (5 << 0) | |
| 1359 | #define R300_PRIM_TYPE_TRI_STRIP (6 << 0) | |
| 1360 | #define R300_PRIM_TYPE_TRI_TYPE2 (7 << 0) | |
| 1361 | #define R300_PRIM_TYPE_RECT_LIST (8 << 0) | |
| 1362 | #define R300_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) | |
| 1363 | #define R300_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) | |
| b5e89ed5 | 1364 | #define R300_PRIM_TYPE_POINT_SPRITES (11 << 0) // GUESS (based on r200) |
| 414ed537 DA |
1365 | #define R300_PRIM_TYPE_LINE_LOOP (12 << 0) |
| 1366 | #define R300_PRIM_TYPE_QUADS (13 << 0) | |
| 1367 | #define R300_PRIM_TYPE_QUAD_STRIP (14 << 0) | |
| 1368 | #define R300_PRIM_TYPE_POLYGON (15 << 0) | |
| 1369 | #define R300_PRIM_TYPE_MASK 0xF | |
| 1370 | #define R300_PRIM_WALK_IND (1 << 4) | |
| 1371 | #define R300_PRIM_WALK_LIST (2 << 4) | |
| 1372 | #define R300_PRIM_WALK_RING (3 << 4) | |
| 1373 | #define R300_PRIM_WALK_MASK (3 << 4) | |
| b5e89ed5 DA |
1374 | #define R300_PRIM_COLOR_ORDER_BGRA (0 << 6) // GUESS (based on r200) |
| 1375 | #define R300_PRIM_COLOR_ORDER_RGBA (1 << 6) // GUESS | |
| 414ed537 DA |
1376 | #define R300_PRIM_NUM_VERTICES_SHIFT 16 |
| 1377 | ||
| 1378 | // Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR. | |
| 1379 | // Two parameter dwords: | |
| 1380 | // 0. The first parameter appears to be always 0 | |
| 1381 | // 1. The second parameter is a standard primitive emission dword. | |
| 1382 | #define R300_PACKET3_3D_DRAW_VBUF 0x00002800 | |
| 1383 | ||
| 1384 | // Specify the full set of vertex arrays as (address, stride). | |
| 1385 | // The first parameter is the number of vertex arrays specified. | |
| 1386 | // The rest of the command is a variable length list of blocks, where | |
| 1387 | // each block is three dwords long and specifies two arrays. | |
| 1388 | // The first dword of a block is split into two words, the lower significant | |
| 1389 | // word refers to the first array, the more significant word to the second | |
| 1390 | // array in the block. | |
| 1391 | // The low byte of each word contains the size of an array entry in dwords, | |
| 1392 | // the high byte contains the stride of the array. | |
| 1393 | // The second dword of a block contains the pointer to the first array, | |
| 1394 | // the third dword of a block contains the pointer to the second array. | |
| 1395 | // Note that if the total number of arrays is odd, the third dword of | |
| 1396 | // the last block is omitted. | |
| 1397 | #define R300_PACKET3_3D_LOAD_VBPNTR 0x00002F00 | |
| 1398 | ||
| 1399 | #define R300_PACKET3_INDX_BUFFER 0x00003300 | |
| 1400 | # define R300_EB_UNK1_SHIFT 24 | |
| 1401 | # define R300_EB_UNK1 (0x80<<24) | |
| 1402 | # define R300_EB_UNK2 0x0810 | |
| 1403 | #define R300_PACKET3_3D_DRAW_INDX_2 0x00003600 | |
| 1404 | ||
| 1405 | //END | |
| 1406 | ||
| b5e89ed5 | 1407 | #endif /* _R300_REG_H */ |