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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / char / agp / uninorth-agp.c
CommitLineData
1da177e4
LT		 1/*
2 * UniNorth AGPGART routines.
3 */
4#include <linux/module.h>
5#include <linux/pci.h>
5a0e3ad6 6#include <linux/slab.h>
1da177e4
LT		 7#include <linux/init.h>
8#include <linux/pagemap.h>
9#include <linux/agp_backend.h>
10#include <linux/delay.h>
e8a5f900 11#include <linux/vmalloc.h>
1da177e4
LT		 12#include <asm/uninorth.h>
13#include <asm/pci-bridge.h>
14#include <asm/prom.h>
0c541b44 15#include <asm/pmac_feature.h>
1da177e4
LT		 16#include "agp.h"
17
18/*
19 * NOTES for uninorth3 (G5 AGP) supports :
20 *
21 * There maybe also possibility to have bigger cache line size for
22 * agp (see pmac_pci.c and look for cache line). Need to be investigated
23 * by someone.
24 *
25 * PAGE size are hardcoded but this may change, see asm/page.h.
26 *
27 * Jerome Glisse <j.glisse@gmail.com>
28 */
29static int uninorth_rev;
30static int is_u3;
31
52f072cb
MD		 32#define DEFAULT_APERTURE_SIZE 256
33#define DEFAULT_APERTURE_STRING "256"
b0385146 34static char *aperture = NULL;
0c541b44 35
1da177e4
LT		 36static int uninorth_fetch_size(void)
37{
18088748
MD		 38 int i, size = 0;
39 struct aper_size_info_32 *values =
40 A_SIZE_32(agp_bridge->driver->aperture_sizes);
41
42 if (aperture) {
43 char *save = aperture;
44
45 size = memparse(aperture, &aperture) >> 20;
46 aperture = save;
47
48 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++)
49 if (size == values[i].size)
50 break;
51
52 if (i == agp_bridge->driver->num_aperture_sizes) {
e3cf6951
BH		 53 dev_err(&agp_bridge->dev->dev, "invalid aperture size, "
54 "using default\n");
18088748
MD		 55 size = 0;
56 aperture = NULL;
1da177e4
LT		 57 }
58 }
59
18088748
MD		 60 if (!size) {
61 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++)
52f072cb 62 if (values[i].size == DEFAULT_APERTURE_SIZE)
18088748
MD		 63 break;
64 }
1da177e4 65
18088748
MD		 66 agp_bridge->previous_size =
67 agp_bridge->current_size = (void *)(values + i);
68 agp_bridge->aperture_size_idx = i;
69 return values[i].size;
1da177e4
LT		 70}
71
72static void uninorth_tlbflush(struct agp_memory *mem)
73{
74 u32 ctrl = UNI_N_CFG_GART_ENABLE;
75
76 if (is_u3)
77 ctrl |= U3_N_CFG_GART_PERFRD;
78 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
79 ctrl | UNI_N_CFG_GART_INVAL);
80 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, ctrl);
81
82 if (uninorth_rev <= 0x30) {
83 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
84 ctrl | UNI_N_CFG_GART_2xRESET);
85 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
86 ctrl);
87 }
88}
89
90static void uninorth_cleanup(void)
91{
92 u32 tmp;
93
94 pci_read_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, &tmp);
95 if (!(tmp & UNI_N_CFG_GART_ENABLE))
96 return;
97 tmp |= UNI_N_CFG_GART_INVAL;
98 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, tmp);
99 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 0);
100
101 if (uninorth_rev <= 0x30) {
102 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
103 UNI_N_CFG_GART_2xRESET);
104 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
105 0);
106 }
107}
108
109static int uninorth_configure(void)
110{
111 struct aper_size_info_32 *current_size;
6a92a4e0 112
1da177e4
LT		 113 current_size = A_SIZE_32(agp_bridge->current_size);
114
e3cf6951
BH		 115 dev_info(&agp_bridge->dev->dev, "configuring for size idx: %d\n",
116 current_size->size_value);
6a92a4e0 117
1da177e4
LT		 118 /* aperture size and gatt addr */
119 pci_write_config_dword(agp_bridge->dev,
120 UNI_N_CFG_GART_BASE,
121 (agp_bridge->gatt_bus_addr & 0xfffff000)
122 | current_size->size_value);
123
124 /* HACK ALERT
125 * UniNorth seem to be buggy enough not to handle properly when
126 * the AGP aperture isn't mapped at bus physical address 0
127 */
128 agp_bridge->gart_bus_addr = 0;
129#ifdef CONFIG_PPC64
130 /* Assume U3 or later on PPC64 systems */
131 /* high 4 bits of GART physical address go in UNI_N_CFG_AGP_BASE */
132 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_AGP_BASE,
133 (agp_bridge->gatt_bus_addr >> 32) & 0xf);
134#else
135 pci_write_config_dword(agp_bridge->dev,
136 UNI_N_CFG_AGP_BASE, agp_bridge->gart_bus_addr);
137#endif
138
139 if (is_u3) {
140 pci_write_config_dword(agp_bridge->dev,
141 UNI_N_CFG_GART_DUMMY_PAGE,
5e8d6b8b 142 page_to_phys(agp_bridge->scratch_page_page) >> 12);
1da177e4 143 }
6a92a4e0 144
1da177e4
LT		 145 return 0;
146}
147
37580f3f 148static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
1da177e4
LT		 149{
150 int i, num_entries;
151 void *temp;
152 u32 *gp;
62369028 153 int mask_type;
1da177e4 154
62369028
MD		 155 if (type != mem->type)
156 return -EINVAL;
157
158 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
159 if (mask_type != 0) {
1da177e4
LT		 160 /* We know nothing of memory types */
161 return -EINVAL;
62369028
MD		 162 }
163
3fc3a6b4
MD		 164 if (mem->page_count == 0)
165 return 0;
166
167 temp = agp_bridge->current_size;
168 num_entries = A_SIZE_32(temp)->num_entries;
169
1da177e4
LT		 170 if ((pg_start + mem->page_count) > num_entries)
171 return -EINVAL;
172
173 gp = (u32 *) &agp_bridge->gatt_table[pg_start];
174 for (i = 0; i < mem->page_count; ++i) {
175 if (gp[i]) {
e3cf6951 176 dev_info(&agp_bridge->dev->dev,
37580f3f 177 "uninorth_insert_memory: entry 0x%x occupied (%x)\n",
e3cf6951 178 i, gp[i]);
1da177e4
LT		 179 return -EBUSY;
180 }
181 }
182
183 for (i = 0; i < mem->page_count; i++) {
37580f3f
MD		 184 if (is_u3)
185 gp[i] = (page_to_phys(mem->pages[i]) >> PAGE_SHIFT) | 0x80000000UL;
186 else
187 gp[i] = cpu_to_le32((page_to_phys(mem->pages[i]) & 0xFFFFF000UL) |
188 0x1UL);
07613ba2
DA		 189 flush_dcache_range((unsigned long)__va(page_to_phys(mem->pages[i])),
190 (unsigned long)__va(page_to_phys(mem->pages[i]))+0x1000);
1da177e4
LT		 191 }
192 mb();
1da177e4
LT		 193 uninorth_tlbflush(mem);
194
195 return 0;
196}
197
37580f3f 198int uninorth_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
1da177e4
LT		 199{
200 size_t i;
201 u32 *gp;
3fc3a6b4 202 int mask_type;
1da177e4 203
3fc3a6b4
MD		 204 if (type != mem->type)
205 return -EINVAL;
206
207 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
208 if (mask_type != 0) {
1da177e4
LT		 209 /* We know nothing of memory types */
210 return -EINVAL;
3fc3a6b4
MD		 211 }
212
213 if (mem->page_count == 0)
214 return 0;
1da177e4
LT		 215
216 gp = (u32 *) &agp_bridge->gatt_table[pg_start];
217 for (i = 0; i < mem->page_count; ++i)
218 gp[i] = 0;
219 mb();
1da177e4
LT		 220 uninorth_tlbflush(mem);
221
222 return 0;
223}
224
225static void uninorth_agp_enable(struct agp_bridge_data *bridge, u32 mode)
226{
227 u32 command, scratch, status;
228 int timeout;
229
230 pci_read_config_dword(bridge->dev,
231 bridge->capndx + PCI_AGP_STATUS,
232 &status);
233
234 command = agp_collect_device_status(bridge, mode, status);
235 command |= PCI_AGP_COMMAND_AGP;
6a92a4e0 236
1da177e4
LT		 237 if (uninorth_rev == 0x21) {
238 /*
239 * Darwin disable AGP 4x on this revision, thus we
240 * may assume it's broken. This is an AGP2 controller.
241 */
242 command &= ~AGPSTAT2_4X;
243 }
244
245 if ((uninorth_rev >= 0x30) && (uninorth_rev <= 0x33)) {
246 /*
fd589a8f 247 * We need to set REQ_DEPTH to 7 for U3 versions 1.0, 2.1,
1da177e4
LT		 248 * 2.2 and 2.3, Darwin do so.
249 */
250 if ((command >> AGPSTAT_RQ_DEPTH_SHIFT) > 7)
251 command = (command & ~AGPSTAT_RQ_DEPTH)
252 | (7 << AGPSTAT_RQ_DEPTH_SHIFT);
253 }
254
255 uninorth_tlbflush(NULL);
256
257 timeout = 0;
258 do {
259 pci_write_config_dword(bridge->dev,
260 bridge->capndx + PCI_AGP_COMMAND,
261 command);
262 pci_read_config_dword(bridge->dev,
263 bridge->capndx + PCI_AGP_COMMAND,
264 &scratch);
265 } while ((scratch & PCI_AGP_COMMAND_AGP) == 0 && ++timeout < 1000);
266 if ((scratch & PCI_AGP_COMMAND_AGP) == 0)
e3cf6951
BH		 267 dev_err(&bridge->dev->dev, "can't write UniNorth AGP "
268 "command register\n");
1da177e4
LT		 269
270 if (uninorth_rev >= 0x30) {
271 /* This is an AGP V3 */
c7258012 272 agp_device_command(command, (status & AGPSTAT_MODE_3_0) != 0);
1da177e4
LT		 273 } else {
274 /* AGP V2 */
c7258012 275 agp_device_command(command, false);
1da177e4
LT		 276 }
277
278 uninorth_tlbflush(NULL);
279}
280
281#ifdef CONFIG_PM
0c541b44
BH		 282/*
283 * These Power Management routines are _not_ called by the normal PCI PM layer,
284 * but directly by the video driver through function pointers in the device
285 * tree.
286 */
287static int agp_uninorth_suspend(struct pci_dev *pdev)
1da177e4 288{
0c541b44 289 struct agp_bridge_data *bridge;
1da177e4
LT		 290 u32 cmd;
291 u8 agp;
292 struct pci_dev *device = NULL;
293
0c541b44
BH		 294 bridge = agp_find_bridge(pdev);
295 if (bridge == NULL)
296 return -ENODEV;
297
298 /* Only one suspend supported */
299 if (bridge->dev_private_data)
1da177e4
LT		 300 return 0;
301
302 /* turn off AGP on the video chip, if it was enabled */
303 for_each_pci_dev(device) {
304 /* Don't touch the bridge yet, device first */
305 if (device == pdev)
306 continue;
307 /* Only deal with devices on the same bus here, no Mac has a P2P
308 * bridge on the AGP port, and mucking around the entire PCI
309 * tree is source of problems on some machines because of a bug
310 * in some versions of pci_find_capability() when hitting a dead
311 * device
312 */
313 if (device->bus != pdev->bus)
314 continue;
315 agp = pci_find_capability(device, PCI_CAP_ID_AGP);
316 if (!agp)
317 continue;
318 pci_read_config_dword(device, agp + PCI_AGP_COMMAND, &cmd);
319 if (!(cmd & PCI_AGP_COMMAND_AGP))
320 continue;
e3cf6951
BH		 321 dev_info(&pdev->dev, "disabling AGP on device %s\n",
322 pci_name(device));
1da177e4
LT		 323 cmd &= ~PCI_AGP_COMMAND_AGP;
324 pci_write_config_dword(device, agp + PCI_AGP_COMMAND, cmd);
325 }
326
327 /* turn off AGP on the bridge */
328 agp = pci_find_capability(pdev, PCI_CAP_ID_AGP);
329 pci_read_config_dword(pdev, agp + PCI_AGP_COMMAND, &cmd);
b07cd518 330 bridge->dev_private_data = (void *)(long)cmd;
1da177e4 331 if (cmd & PCI_AGP_COMMAND_AGP) {
e3cf6951 332 dev_info(&pdev->dev, "disabling AGP on bridge\n");
1da177e4
LT		 333 cmd &= ~PCI_AGP_COMMAND_AGP;
334 pci_write_config_dword(pdev, agp + PCI_AGP_COMMAND, cmd);
335 }
336 /* turn off the GART */
337 uninorth_cleanup();
338
339 return 0;
340}
341
342static int agp_uninorth_resume(struct pci_dev *pdev)
343{
0c541b44
BH		 344 struct agp_bridge_data *bridge;
345 u32 command;
346
347 bridge = agp_find_bridge(pdev);
348 if (bridge == NULL)
349 return -ENODEV;
350
b07cd518 351 command = (long)bridge->dev_private_data;
0c541b44
BH		 352 bridge->dev_private_data = NULL;
353 if (!(command & PCI_AGP_COMMAND_AGP))
354 return 0;
355
356 uninorth_agp_enable(bridge, command);
357
1da177e4
LT		 358 return 0;
359}
0c541b44 360#endif /* CONFIG_PM */
1da177e4
LT		 361
362static int uninorth_create_gatt_table(struct agp_bridge_data *bridge)
363{
364 char *table;
365 char *table_end;
366 int size;
367 int page_order;
368 int num_entries;
369 int i;
370 void *temp;
371 struct page *page;
e8a5f900 372 struct page **pages;
1da177e4
LT		 373
374 /* We can't handle 2 level gatt's */
375 if (bridge->driver->size_type == LVL2_APER_SIZE)
376 return -EINVAL;
377
378 table = NULL;
379 i = bridge->aperture_size_idx;
380 temp = bridge->current_size;
381 size = page_order = num_entries = 0;
382
383 do {
384 size = A_SIZE_32(temp)->size;
385 page_order = A_SIZE_32(temp)->page_order;
386 num_entries = A_SIZE_32(temp)->num_entries;
387
388 table = (char *) __get_free_pages(GFP_KERNEL, page_order);
389
390 if (table == NULL) {
391 i++;
392 bridge->current_size = A_IDX32(bridge);
393 } else {
394 bridge->aperture_size_idx = i;
395 }
396 } while (!table && (i < bridge->driver->num_aperture_sizes));
397
398 if (table == NULL)
399 return -ENOMEM;
400
e8a5f900
MD		 401 pages = kmalloc((1 << page_order) * sizeof(struct page*), GFP_KERNEL);
402 if (pages == NULL)
403 goto enomem;
404
1da177e4
LT		 405 table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1);
406
e8a5f900
MD		 407 for (page = virt_to_page(table), i = 0; page <= virt_to_page(table_end);
408 page++, i++) {
1da177e4 409 SetPageReserved(page);
e8a5f900
MD		 410 pages[i] = page;
411 }
1da177e4
LT		 412
413 bridge->gatt_table_real = (u32 *) table;
e8a5f900
MD		 414 /* Need to clear out any dirty data still sitting in caches */
415 flush_dcache_range((unsigned long)table,
416 (unsigned long)(table_end + PAGE_SIZE));
417 bridge->gatt_table = vmap(pages, (1 << page_order), 0, PAGE_KERNEL_NCG);
418
419 if (bridge->gatt_table == NULL)
420 goto enomem;
421
6a12235c 422 bridge->gatt_bus_addr = virt_to_phys(table);
1da177e4
LT		 423
424 for (i = 0; i < num_entries; i++)
425 bridge->gatt_table[i] = 0;
426
1da177e4 427 return 0;
e8a5f900
MD		 428
429enomem:
430 kfree(pages);
431 if (table)
432 free_pages((unsigned long)table, page_order);
433 return -ENOMEM;
1da177e4
LT		 434}
435
436static int uninorth_free_gatt_table(struct agp_bridge_data *bridge)
437{
438 int page_order;
439 char *table, *table_end;
440 void *temp;
441 struct page *page;
442
443 temp = bridge->current_size;
444 page_order = A_SIZE_32(temp)->page_order;
445
446 /* Do not worry about freeing memory, because if this is
447 * called, then all agp memory is deallocated and removed
448 * from the table.
449 */
450
e8a5f900 451 vunmap(bridge->gatt_table);
1da177e4
LT		 452 table = (char *) bridge->gatt_table_real;
453 table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1);
454
455 for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
456 ClearPageReserved(page);
457
458 free_pages((unsigned long) bridge->gatt_table_real, page_order);
459
460 return 0;
461}
462
463void null_cache_flush(void)
464{
465 mb();
466}
467
468/* Setup function */
469
52f072cb 470static const struct aper_size_info_32 uninorth_sizes[] =
1da177e4 471{
1da177e4
LT		 472 {256, 65536, 6, 64},
473 {128, 32768, 5, 32},
474 {64, 16384, 4, 16},
1da177e4
LT		 475 {32, 8192, 3, 8},
476 {16, 4096, 2, 4},
477 {8, 2048, 1, 2},
478 {4, 1024, 0, 1}
479};
480
481/*
482 * Not sure that u3 supports that high aperture sizes but it
483 * would strange if it did not :)
484 */
52f072cb 485static const struct aper_size_info_32 u3_sizes[] =
1da177e4
LT		 486{
487 {512, 131072, 7, 128},
488 {256, 65536, 6, 64},
489 {128, 32768, 5, 32},
490 {64, 16384, 4, 16},
491 {32, 8192, 3, 8},
492 {16, 4096, 2, 4},
493 {8, 2048, 1, 2},
494 {4, 1024, 0, 1}
495};
496
e047d1cf 497const struct agp_bridge_driver uninorth_agp_driver = {
1da177e4
LT		 498 .owner = THIS_MODULE,
499 .aperture_sizes = (void *)uninorth_sizes,
500 .size_type = U32_APER_SIZE,
52f072cb 501 .num_aperture_sizes = ARRAY_SIZE(uninorth_sizes),
1da177e4
LT		 502 .configure = uninorth_configure,
503 .fetch_size = uninorth_fetch_size,
504 .cleanup = uninorth_cleanup,
505 .tlb_flush = uninorth_tlbflush,
506 .mask_memory = agp_generic_mask_memory,
507 .masks = NULL,
508 .cache_flush = null_cache_flush,
509 .agp_enable = uninorth_agp_enable,
510 .create_gatt_table = uninorth_create_gatt_table,
511 .free_gatt_table = uninorth_free_gatt_table,
512 .insert_memory = uninorth_insert_memory,
37580f3f 513 .remove_memory = uninorth_remove_memory,
1da177e4
LT		 514 .alloc_by_type = agp_generic_alloc_by_type,
515 .free_by_type = agp_generic_free_by_type,
516 .agp_alloc_page = agp_generic_alloc_page,
5f310b63 517 .agp_alloc_pages = agp_generic_alloc_pages,
1da177e4 518 .agp_destroy_page = agp_generic_destroy_page,
5f310b63 519 .agp_destroy_pages = agp_generic_destroy_pages,
a030ce44 520 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
c7258012 521 .cant_use_aperture = true,
1da177e4
LT		 522};
523
e047d1cf 524const struct agp_bridge_driver u3_agp_driver = {
1da177e4
LT		 525 .owner = THIS_MODULE,
526 .aperture_sizes = (void *)u3_sizes,
527 .size_type = U32_APER_SIZE,
52f072cb 528 .num_aperture_sizes = ARRAY_SIZE(u3_sizes),
1da177e4
LT		 529 .configure = uninorth_configure,
530 .fetch_size = uninorth_fetch_size,
531 .cleanup = uninorth_cleanup,
532 .tlb_flush = uninorth_tlbflush,
533 .mask_memory = agp_generic_mask_memory,
534 .masks = NULL,
535 .cache_flush = null_cache_flush,
536 .agp_enable = uninorth_agp_enable,
537 .create_gatt_table = uninorth_create_gatt_table,
538 .free_gatt_table = uninorth_free_gatt_table,
37580f3f
MD		 539 .insert_memory = uninorth_insert_memory,
540 .remove_memory = uninorth_remove_memory,
1da177e4
LT		 541 .alloc_by_type = agp_generic_alloc_by_type,
542 .free_by_type = agp_generic_free_by_type,
543 .agp_alloc_page = agp_generic_alloc_page,
5f310b63 544 .agp_alloc_pages = agp_generic_alloc_pages,
1da177e4 545 .agp_destroy_page = agp_generic_destroy_page,
c09ff7e1 546 .agp_destroy_pages = agp_generic_destroy_pages,
a030ce44 547 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
c7258012
JP		 548 .cant_use_aperture = true,
549 .needs_scratch_page = true,
1da177e4
LT		 550};
551
552static struct agp_device_ids uninorth_agp_device_ids[] __devinitdata = {
553 {
554 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP,
555 .chipset_name = "UniNorth",
556 },
557 {
558 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP_P,
559 .chipset_name = "UniNorth/Pangea",
560 },
561 {
562 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP15,
563 .chipset_name = "UniNorth 1.5",
564 },
565 {
566 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP2,
567 .chipset_name = "UniNorth 2",
568 },
569 {
570 .device_id = PCI_DEVICE_ID_APPLE_U3_AGP,
571 .chipset_name = "U3",
572 },
573 {
574 .device_id = PCI_DEVICE_ID_APPLE_U3L_AGP,
575 .chipset_name = "U3L",
576 },
577 {
578 .device_id = PCI_DEVICE_ID_APPLE_U3H_AGP,
579 .chipset_name = "U3H",
580 },
7fce260a
OJ		 581 {
582 .device_id = PCI_DEVICE_ID_APPLE_IPID2_AGP,
583 .chipset_name = "UniNorth/Intrepid2",
584 },
1da177e4
LT		 585};
586
587static int __devinit agp_uninorth_probe(struct pci_dev *pdev,
588 const struct pci_device_id *ent)
589{
590 struct agp_device_ids *devs = uninorth_agp_device_ids;
591 struct agp_bridge_data *bridge;
592 struct device_node *uninorth_node;
593 u8 cap_ptr;
594 int j;
595
596 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
597 if (cap_ptr == 0)
598 return -ENODEV;
599
600 /* probe for known chipsets */
601 for (j = 0; devs[j].chipset_name != NULL; ++j) {
602 if (pdev->device == devs[j].device_id) {
e3cf6951
BH		 603 dev_info(&pdev->dev, "Apple %s chipset\n",
604 devs[j].chipset_name);
1da177e4
LT		 605 goto found;
606 }
607 }
608
e3cf6951
BH		 609 dev_err(&pdev->dev, "unsupported Apple chipset [%04x/%04x]\n",
610 pdev->vendor, pdev->device);
1da177e4
LT		 611 return -ENODEV;
612
613 found:
614 /* Set revision to 0 if we could not read it. */
615 uninorth_rev = 0;
616 is_u3 = 0;
617 /* Locate core99 Uni-N */
618 uninorth_node = of_find_node_by_name(NULL, "uni-n");
619 /* Locate G5 u3 */
620 if (uninorth_node == NULL) {
621 is_u3 = 1;
622 uninorth_node = of_find_node_by_name(NULL, "u3");
623 }
624 if (uninorth_node) {
40cd3a45 625 const int *revprop = of_get_property(uninorth_node,
b04e3dd4 626 "device-rev", NULL);
1da177e4
LT		 627 if (revprop != NULL)
628 uninorth_rev = *revprop & 0x3f;
629 of_node_put(uninorth_node);
630 }
631
0c541b44
BH		 632#ifdef CONFIG_PM
633 /* Inform platform of our suspend/resume caps */
634 pmac_register_agp_pm(pdev, agp_uninorth_suspend, agp_uninorth_resume);
635#endif
636
637 /* Allocate & setup our driver */
1da177e4
LT		 638 bridge = agp_alloc_bridge();
639 if (!bridge)
640 return -ENOMEM;
641
642 if (is_u3)
643 bridge->driver = &u3_agp_driver;
644 else
645 bridge->driver = &uninorth_agp_driver;
646
647 bridge->dev = pdev;
648 bridge->capndx = cap_ptr;
649 bridge->flags = AGP_ERRATA_FASTWRITES;
650
651 /* Fill in the mode register */
652 pci_read_config_dword(pdev, cap_ptr+PCI_AGP_STATUS, &bridge->mode);
653
654 pci_set_drvdata(pdev, bridge);
655 return agp_add_bridge(bridge);
656}
657
658static void __devexit agp_uninorth_remove(struct pci_dev *pdev)
659{
660 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
661
0c541b44
BH		 662#ifdef CONFIG_PM
663 /* Inform platform of our suspend/resume caps */
664 pmac_register_agp_pm(pdev, NULL, NULL);
665#endif
666
1da177e4
LT		 667 agp_remove_bridge(bridge);
668 agp_put_bridge(bridge);
669}
670
671static struct pci_device_id agp_uninorth_pci_table[] = {
672 {
673 .class = (PCI_CLASS_BRIDGE_HOST << 8),
674 .class_mask = ~0,
675 .vendor = PCI_VENDOR_ID_APPLE,
676 .device = PCI_ANY_ID,
677 .subvendor = PCI_ANY_ID,
678 .subdevice = PCI_ANY_ID,
679 },
680 { }
681};
682
683MODULE_DEVICE_TABLE(pci, agp_uninorth_pci_table);
684
685static struct pci_driver agp_uninorth_pci_driver = {
686 .name = "agpgart-uninorth",
687 .id_table = agp_uninorth_pci_table,
688 .probe = agp_uninorth_probe,
689 .remove = agp_uninorth_remove,
1da177e4
LT		 690};
691
692static int __init agp_uninorth_init(void)
693{
694 if (agp_off)
695 return -EINVAL;
696 return pci_register_driver(&agp_uninorth_pci_driver);
697}
698
699static void __exit agp_uninorth_cleanup(void)
700{
701 pci_unregister_driver(&agp_uninorth_pci_driver);
702}
703
704module_init(agp_uninorth_init);
705module_exit(agp_uninorth_cleanup);
706
18088748
MD		 707module_param(aperture, charp, 0);
708MODULE_PARM_DESC(aperture,
709 "Aperture size, must be power of two between 4MB and an\n"
710 "\t\tupper limit specific to the UniNorth revision.\n"
52f072cb 711 "\t\tDefault: " DEFAULT_APERTURE_STRING "M");
18088748 712
1da177e4
LT		 713MODULE_AUTHOR("Ben Herrenschmidt & Paul Mackerras");
714MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)