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[PATCH] devfs: Remove devfs_remove() function from the kernel tree
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / block / cpqarray.c
CommitLineData
1da177e4
LT		 1/*
2 * Disk Array driver for Compaq SMART2 Controllers
3 * Copyright 1998 Compaq Computer Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
20 *
21 */
22#include <linux/config.h> /* CONFIG_PROC_FS */
23#include <linux/module.h>
24#include <linux/types.h>
25#include <linux/pci.h>
26#include <linux/bio.h>
27#include <linux/interrupt.h>
28#include <linux/kernel.h>
29#include <linux/slab.h>
30#include <linux/delay.h>
31#include <linux/major.h>
32#include <linux/fs.h>
33#include <linux/blkpg.h>
34#include <linux/timer.h>
35#include <linux/proc_fs.h>
36#include <linux/devfs_fs_kernel.h>
37#include <linux/init.h>
38#include <linux/hdreg.h>
39#include <linux/spinlock.h>
40#include <linux/blkdev.h>
41#include <linux/genhd.h>
42#include <asm/uaccess.h>
43#include <asm/io.h>
44
45
46#define SMART2_DRIVER_VERSION(maj,min,submin) ((maj<<16)|(min<<8)|(submin))
47
48#define DRIVER_NAME "Compaq SMART2 Driver (v 2.6.0)"
49#define DRIVER_VERSION SMART2_DRIVER_VERSION(2,6,0)
50
51/* Embedded module documentation macros - see modules.h */
52/* Original author Chris Frantz - Compaq Computer Corporation */
53MODULE_AUTHOR("Compaq Computer Corporation");
54MODULE_DESCRIPTION("Driver for Compaq Smart2 Array Controllers version 2.6.0");
55MODULE_LICENSE("GPL");
56
57#include "cpqarray.h"
58#include "ida_cmd.h"
59#include "smart1,2.h"
60#include "ida_ioctl.h"
61
62#define READ_AHEAD 128
63#define NR_CMDS 128 /* This could probably go as high as ~400 */
64
65#define MAX_CTLR 8
66#define CTLR_SHIFT 8
67
68#define CPQARRAY_DMA_MASK 0xFFFFFFFF /* 32 bit DMA */
69
70static int nr_ctlr;
71static ctlr_info_t *hba[MAX_CTLR];
72
73static int eisa[8];
74
945f390f 75#define NR_PRODUCTS ARRAY_SIZE(products)
1da177e4
LT		 76
77/* board_id = Subsystem Device ID & Vendor ID
78 * product = Marketing Name for the board
945f390f 79 * access = Address of the struct of function pointers
1da177e4
LT		 80 */
81static struct board_type products[] = {
82 { 0x0040110E, "IDA", &smart1_access },
83 { 0x0140110E, "IDA-2", &smart1_access },
84 { 0x1040110E, "IAES", &smart1_access },
85 { 0x2040110E, "SMART", &smart1_access },
86 { 0x3040110E, "SMART-2/E", &smart2e_access },
87 { 0x40300E11, "SMART-2/P", &smart2_access },
88 { 0x40310E11, "SMART-2SL", &smart2_access },
89 { 0x40320E11, "Smart Array 3200", &smart2_access },
90 { 0x40330E11, "Smart Array 3100ES", &smart2_access },
91 { 0x40340E11, "Smart Array 221", &smart2_access },
92 { 0x40400E11, "Integrated Array", &smart4_access },
93 { 0x40480E11, "Compaq Raid LC2", &smart4_access },
94 { 0x40500E11, "Smart Array 4200", &smart4_access },
95 { 0x40510E11, "Smart Array 4250ES", &smart4_access },
96 { 0x40580E11, "Smart Array 431", &smart4_access },
97};
98
99/* define the PCI info for the PCI cards this driver can control */
100static const struct pci_device_id cpqarray_pci_device_id[] =
101{
102 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_COMPAQ_42XX,
103 0x0E11, 0x4058, 0, 0, 0}, /* SA431 */
104 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_COMPAQ_42XX,
105 0x0E11, 0x4051, 0, 0, 0}, /* SA4250ES */
106 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_COMPAQ_42XX,
107 0x0E11, 0x4050, 0, 0, 0}, /* SA4200 */
108 { PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C1510,
109 0x0E11, 0x4048, 0, 0, 0}, /* LC2 */
110 { PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C1510,
111 0x0E11, 0x4040, 0, 0, 0}, /* Integrated Array */
112 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
113 0x0E11, 0x4034, 0, 0, 0}, /* SA 221 */
114 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
115 0x0E11, 0x4033, 0, 0, 0}, /* SA 3100ES*/
116 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
117 0x0E11, 0x4032, 0, 0, 0}, /* SA 3200*/
118 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
119 0x0E11, 0x4031, 0, 0, 0}, /* SA 2SL*/
120 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
121 0x0E11, 0x4030, 0, 0, 0}, /* SA 2P */
122 { 0 }
123};
124
125MODULE_DEVICE_TABLE(pci, cpqarray_pci_device_id);
126
127static struct gendisk *ida_gendisk[MAX_CTLR][NWD];
128
129/* Debug... */
130#define DBG(s) do { s } while(0)
131/* Debug (general info)... */
132#define DBGINFO(s) do { } while(0)
133/* Debug Paranoid... */
134#define DBGP(s) do { } while(0)
135/* Debug Extra Paranoid... */
136#define DBGPX(s) do { } while(0)
137
138static int cpqarray_pci_init(ctlr_info_t *c, struct pci_dev *pdev);
139static void __iomem *remap_pci_mem(ulong base, ulong size);
140static int cpqarray_eisa_detect(void);
141static int pollcomplete(int ctlr);
142static void getgeometry(int ctlr);
143static void start_fwbk(int ctlr);
144
145static cmdlist_t * cmd_alloc(ctlr_info_t *h, int get_from_pool);
146static void cmd_free(ctlr_info_t *h, cmdlist_t *c, int got_from_pool);
147
148static void free_hba(int i);
149static int alloc_cpqarray_hba(void);
150
151static int sendcmd(
152 __u8 cmd,
153 int ctlr,
154 void *buff,
155 size_t size,
156 unsigned int blk,
157 unsigned int blkcnt,
158 unsigned int log_unit );
159
160static int ida_open(struct inode *inode, struct file *filep);
161static int ida_release(struct inode *inode, struct file *filep);
162static int ida_ioctl(struct inode *inode, struct file *filep, unsigned int cmd, unsigned long arg);
a885c8c4 163static int ida_getgeo(struct block_device *bdev, struct hd_geometry *geo);
1da177e4
LT		 164static int ida_ctlr_ioctl(ctlr_info_t *h, int dsk, ida_ioctl_t *io);
165
166static void do_ida_request(request_queue_t *q);
167static void start_io(ctlr_info_t *h);
168
169static inline void addQ(cmdlist_t **Qptr, cmdlist_t *c);
170static inline cmdlist_t *removeQ(cmdlist_t **Qptr, cmdlist_t *c);
171static inline void complete_buffers(struct bio *bio, int ok);
172static inline void complete_command(cmdlist_t *cmd, int timeout);
173
174static irqreturn_t do_ida_intr(int irq, void *dev_id, struct pt_regs * regs);
175static void ida_timer(unsigned long tdata);
176static int ida_revalidate(struct gendisk *disk);
177static int revalidate_allvol(ctlr_info_t *host);
178static int cpqarray_register_ctlr(int ctlr, struct pci_dev *pdev);
179
180#ifdef CONFIG_PROC_FS
181static void ida_procinit(int i);
182static int ida_proc_get_info(char *buffer, char **start, off_t offset, int length, int *eof, void *data);
183#else
184static void ida_procinit(int i) {}
185#endif
186
187static inline drv_info_t *get_drv(struct gendisk *disk)
188{
189 return disk->private_data;
190}
191
192static inline ctlr_info_t *get_host(struct gendisk *disk)
193{
194 return disk->queue->queuedata;
195}
196
197
198static struct block_device_operations ida_fops = {
199 .owner = THIS_MODULE,
200 .open = ida_open,
201 .release = ida_release,
202 .ioctl = ida_ioctl,
a885c8c4 203 .getgeo = ida_getgeo,
1da177e4
LT		 204 .revalidate_disk= ida_revalidate,
205};
206
207
208#ifdef CONFIG_PROC_FS
209
210static struct proc_dir_entry *proc_array;
211
212/*
213 * Get us a file in /proc/array that says something about each controller.
214 * Create /proc/array if it doesn't exist yet.
215 */
216static void __init ida_procinit(int i)
217{
218 if (proc_array == NULL) {
219 proc_array = proc_mkdir("cpqarray", proc_root_driver);
220 if (!proc_array) return;
221 }
222
223 create_proc_read_entry(hba[i]->devname, 0, proc_array,
224 ida_proc_get_info, hba[i]);
225}
226
227/*
228 * Report information about this controller.
229 */
230static int ida_proc_get_info(char *buffer, char **start, off_t offset, int length, int *eof, void *data)
231{
232 off_t pos = 0;
233 off_t len = 0;
234 int size, i, ctlr;
235 ctlr_info_t *h = (ctlr_info_t*)data;
236 drv_info_t *drv;
237#ifdef CPQ_PROC_PRINT_QUEUES
238 cmdlist_t *c;
239 unsigned long flags;
240#endif
241
242 ctlr = h->ctlr;
243 size = sprintf(buffer, "%s: Compaq %s Controller\n"
244 " Board ID: 0x%08lx\n"
245 " Firmware Revision: %c%c%c%c\n"
246 " Controller Sig: 0x%08lx\n"
247 " Memory Address: 0x%08lx\n"
248 " I/O Port: 0x%04x\n"
249 " IRQ: %d\n"
250 " Logical drives: %d\n"
251 " Physical drives: %d\n\n"
252 " Current Q depth: %d\n"
253 " Max Q depth since init: %d\n\n",
254 h->devname,
255 h->product_name,
256 (unsigned long)h->board_id,
257 h->firm_rev[0], h->firm_rev[1], h->firm_rev[2], h->firm_rev[3],
258 (unsigned long)h->ctlr_sig, (unsigned long)h->vaddr,
259 (unsigned int) h->io_mem_addr, (unsigned int)h->intr,
260 h->log_drives, h->phys_drives,
261 h->Qdepth, h->maxQsinceinit);
262
263 pos += size; len += size;
264
265 size = sprintf(buffer+len, "Logical Drive Info:\n");
266 pos += size; len += size;
267
268 for(i=0; i<h->log_drives; i++) {
269 drv = &h->drv[i];
270 size = sprintf(buffer+len, "ida/c%dd%d: blksz=%d nr_blks=%d\n",
271 ctlr, i, drv->blk_size, drv->nr_blks);
272 pos += size; len += size;
273 }
274
275#ifdef CPQ_PROC_PRINT_QUEUES
276 spin_lock_irqsave(IDA_LOCK(h->ctlr), flags);
277 size = sprintf(buffer+len, "\nCurrent Queues:\n");
278 pos += size; len += size;
279
280 c = h->reqQ;
281 size = sprintf(buffer+len, "reqQ = %p", c); pos += size; len += size;
282 if (c) c=c->next;
283 while(c && c != h->reqQ) {
284 size = sprintf(buffer+len, "->%p", c);
285 pos += size; len += size;
286 c=c->next;
287 }
288
289 c = h->cmpQ;
290 size = sprintf(buffer+len, "\ncmpQ = %p", c); pos += size; len += size;
291 if (c) c=c->next;
292 while(c && c != h->cmpQ) {
293 size = sprintf(buffer+len, "->%p", c);
294 pos += size; len += size;
295 c=c->next;
296 }
297
298 size = sprintf(buffer+len, "\n"); pos += size; len += size;
299 spin_unlock_irqrestore(IDA_LOCK(h->ctlr), flags);
300#endif
301 size = sprintf(buffer+len, "nr_allocs = %d\nnr_frees = %d\n",
302 h->nr_allocs, h->nr_frees);
303 pos += size; len += size;
304
305 *eof = 1;
306 *start = buffer+offset;
307 len -= offset;
308 if (len>length)
309 len = length;
310 return len;
311}
312#endif /* CONFIG_PROC_FS */
313
314module_param_array(eisa, int, NULL, 0);
315
316static void release_io_mem(ctlr_info_t *c)
317{
318 /* if IO mem was not protected do nothing */
319 if( c->io_mem_addr == 0)
320 return;
321 release_region(c->io_mem_addr, c->io_mem_length);
322 c->io_mem_addr = 0;
323 c->io_mem_length = 0;
324}
325
326static void __devexit cpqarray_remove_one(int i)
327{
328 int j;
329 char buff[4];
330
331 /* sendcmd will turn off interrupt, and send the flush...
332 * To write all data in the battery backed cache to disks
333 * no data returned, but don't want to send NULL to sendcmd */
334 if( sendcmd(FLUSH_CACHE, i, buff, 4, 0, 0, 0))
335 {
336 printk(KERN_WARNING "Unable to flush cache on controller %d\n",
337 i);
338 }
339 free_irq(hba[i]->intr, hba[i]);
340 iounmap(hba[i]->vaddr);
341 unregister_blkdev(COMPAQ_SMART2_MAJOR+i, hba[i]->devname);
342 del_timer(&hba[i]->timer);
343 remove_proc_entry(hba[i]->devname, proc_array);
344 pci_free_consistent(hba[i]->pci_dev,
345 NR_CMDS * sizeof(cmdlist_t), (hba[i]->cmd_pool),
346 hba[i]->cmd_pool_dhandle);
347 kfree(hba[i]->cmd_pool_bits);
348 for(j = 0; j < NWD; j++) {
349 if (ida_gendisk[i][j]->flags & GENHD_FL_UP)
350 del_gendisk(ida_gendisk[i][j]);
1da177e4
LT		 351 put_disk(ida_gendisk[i][j]);
352 }
353 blk_cleanup_queue(hba[i]->queue);
354 release_io_mem(hba[i]);
355 free_hba(i);
356}
357
358static void __devexit cpqarray_remove_one_pci (struct pci_dev *pdev)
359{
360 int i;
361 ctlr_info_t *tmp_ptr;
362
363 if (pci_get_drvdata(pdev) == NULL) {
364 printk( KERN_ERR "cpqarray: Unable to remove device \n");
365 return;
366 }
367
368 tmp_ptr = pci_get_drvdata(pdev);
369 i = tmp_ptr->ctlr;
370 if (hba[i] == NULL) {
371 printk(KERN_ERR "cpqarray: controller %d appears to have"
372 "already been removed \n", i);
373 return;
374 }
375 pci_set_drvdata(pdev, NULL);
376
377 cpqarray_remove_one(i);
378}
379
380/* removing an instance that was not removed automatically..
381 * must be an eisa card.
382 */
383static void __devexit cpqarray_remove_one_eisa (int i)
384{
385 if (hba[i] == NULL) {
386 printk(KERN_ERR "cpqarray: controller %d appears to have"
387 "already been removed \n", i);
388 return;
389 }
390 cpqarray_remove_one(i);
391}
392
393/* pdev is NULL for eisa */
bc648638 394static int __init cpqarray_register_ctlr( int i, struct pci_dev *pdev)
1da177e4
LT		 395{
396 request_queue_t *q;
397 int j;
398
399 /*
400 * register block devices
401 * Find disks and fill in structs
402 * Get an interrupt, set the Q depth and get into /proc
403 */
404
405 /* If this successful it should insure that we are the only */
406 /* instance of the driver */
407 if (register_blkdev(COMPAQ_SMART2_MAJOR+i, hba[i]->devname)) {
408 goto Enomem4;
409 }
410 hba[i]->access.set_intr_mask(hba[i], 0);
411 if (request_irq(hba[i]->intr, do_ida_intr,
0f41a53a 412 SA_INTERRUPT|SA_SHIRQ, hba[i]->devname, hba[i]))
1da177e4
LT		 413 {
414 printk(KERN_ERR "cpqarray: Unable to get irq %d for %s\n",
415 hba[i]->intr, hba[i]->devname);
416 goto Enomem3;
417 }
418
419 for (j=0; j<NWD; j++) {
420 ida_gendisk[i][j] = alloc_disk(1 << NWD_SHIFT);
421 if (!ida_gendisk[i][j])
422 goto Enomem2;
423 }
424
425 hba[i]->cmd_pool = (cmdlist_t *)pci_alloc_consistent(
426 hba[i]->pci_dev, NR_CMDS * sizeof(cmdlist_t),
427 &(hba[i]->cmd_pool_dhandle));
428 hba[i]->cmd_pool_bits = kmalloc(
429 ((NR_CMDS+BITS_PER_LONG-1)/BITS_PER_LONG)*sizeof(unsigned long),
430 GFP_KERNEL);
431
432 if (!hba[i]->cmd_pool_bits || !hba[i]->cmd_pool)
433 goto Enomem1;
434
435 memset(hba[i]->cmd_pool, 0, NR_CMDS * sizeof(cmdlist_t));
436 memset(hba[i]->cmd_pool_bits, 0, ((NR_CMDS+BITS_PER_LONG-1)/BITS_PER_LONG)*sizeof(unsigned long));
437 printk(KERN_INFO "cpqarray: Finding drives on %s",
438 hba[i]->devname);
439
440 spin_lock_init(&hba[i]->lock);
441 q = blk_init_queue(do_ida_request, &hba[i]->lock);
442 if (!q)
443 goto Enomem1;
444
445 hba[i]->queue = q;
446 q->queuedata = hba[i];
447
448 getgeometry(i);
449 start_fwbk(i);
450
451 ida_procinit(i);
452
453 if (pdev)
454 blk_queue_bounce_limit(q, hba[i]->pci_dev->dma_mask);
455
456 /* This is a hardware imposed limit. */
457 blk_queue_max_hw_segments(q, SG_MAX);
458
459 /* This is a driver limit and could be eliminated. */
460 blk_queue_max_phys_segments(q, SG_MAX);
461
462 init_timer(&hba[i]->timer);
463 hba[i]->timer.expires = jiffies + IDA_TIMER;
464 hba[i]->timer.data = (unsigned long)hba[i];
465 hba[i]->timer.function = ida_timer;
466 add_timer(&hba[i]->timer);
467
468 /* Enable IRQ now that spinlock and rate limit timer are set up */
469 hba[i]->access.set_intr_mask(hba[i], FIFO_NOT_EMPTY);
470
471 for(j=0; j<NWD; j++) {
472 struct gendisk *disk = ida_gendisk[i][j];
473 drv_info_t *drv = &hba[i]->drv[j];
474 sprintf(disk->disk_name, "ida/c%dd%d", i, j);
475 disk->major = COMPAQ_SMART2_MAJOR + i;
476 disk->first_minor = j<<NWD_SHIFT;
477 disk->fops = &ida_fops;
478 if (j && !drv->nr_blks)
479 continue;
480 blk_queue_hardsect_size(hba[i]->queue, drv->blk_size);
481 set_capacity(disk, drv->nr_blks);
482 disk->queue = hba[i]->queue;
483 disk->private_data = drv;
484 add_disk(disk);
485 }
486
487 /* done ! */
488 return(i);
489
490Enomem1:
491 nr_ctlr = i;
492 kfree(hba[i]->cmd_pool_bits);
493 if (hba[i]->cmd_pool)
494 pci_free_consistent(hba[i]->pci_dev, NR_CMDS*sizeof(cmdlist_t),
495 hba[i]->cmd_pool, hba[i]->cmd_pool_dhandle);
496Enomem2:
497 while (j--) {
498 put_disk(ida_gendisk[i][j]);
499 ida_gendisk[i][j] = NULL;
500 }
501 free_irq(hba[i]->intr, hba[i]);
502Enomem3:
503 unregister_blkdev(COMPAQ_SMART2_MAJOR+i, hba[i]->devname);
504Enomem4:
505 if (pdev)
506 pci_set_drvdata(pdev, NULL);
507 release_io_mem(hba[i]);
508 free_hba(i);
509
510 printk( KERN_ERR "cpqarray: out of memory");
511
512 return -1;
513}
514
515static int __init cpqarray_init_one( struct pci_dev *pdev,
516 const struct pci_device_id *ent)
517{
518 int i;
519
520 printk(KERN_DEBUG "cpqarray: Device 0x%x has been found at"
521 " bus %d dev %d func %d\n",
522 pdev->device, pdev->bus->number, PCI_SLOT(pdev->devfn),
523 PCI_FUNC(pdev->devfn));
524 i = alloc_cpqarray_hba();
525 if( i < 0 )
526 return (-1);
527 memset(hba[i], 0, sizeof(ctlr_info_t));
528 sprintf(hba[i]->devname, "ida%d", i);
529 hba[i]->ctlr = i;
530 /* Initialize the pdev driver private data */
531 pci_set_drvdata(pdev, hba[i]);
532
533 if (cpqarray_pci_init(hba[i], pdev) != 0) {
534 pci_set_drvdata(pdev, NULL);
535 release_io_mem(hba[i]);
536 free_hba(i);
537 return -1;
538 }
539
540 return (cpqarray_register_ctlr(i, pdev));
541}
542
543static struct pci_driver cpqarray_pci_driver = {
544 .name = "cpqarray",
545 .probe = cpqarray_init_one,
546 .remove = __devexit_p(cpqarray_remove_one_pci),
547 .id_table = cpqarray_pci_device_id,
548};
549
550/*
551 * This is it. Find all the controllers and register them.
552 * returns the number of block devices registered.
553 */
554static int __init cpqarray_init(void)
555{
556 int num_cntlrs_reg = 0;
557 int i;
558 int rc = 0;
559
560 /* detect controllers */
561 printk(DRIVER_NAME "\n");
562
563 rc = pci_register_driver(&cpqarray_pci_driver);
564 if (rc)
565 return rc;
566 cpqarray_eisa_detect();
567
568 for (i=0; i < MAX_CTLR; i++) {
569 if (hba[i] != NULL)
570 num_cntlrs_reg++;
571 }
572
573 return(num_cntlrs_reg);
574}
575
576/* Function to find the first free pointer into our hba[] array */
577/* Returns -1 if no free entries are left. */
578static int alloc_cpqarray_hba(void)
579{
580 int i;
581
582 for(i=0; i< MAX_CTLR; i++) {
583 if (hba[i] == NULL) {
584 hba[i] = kmalloc(sizeof(ctlr_info_t), GFP_KERNEL);
585 if(hba[i]==NULL) {
586 printk(KERN_ERR "cpqarray: out of memory.\n");
587 return (-1);
588 }
589 return (i);
590 }
591 }
592 printk(KERN_WARNING "cpqarray: This driver supports a maximum"
593 " of 8 controllers.\n");
594 return(-1);
595}
596
597static void free_hba(int i)
598{
599 kfree(hba[i]);
600 hba[i]=NULL;
601}
602
603/*
604 * Find the IO address of the controller, its IRQ and so forth. Fill
605 * in some basic stuff into the ctlr_info_t structure.
606 */
607static int cpqarray_pci_init(ctlr_info_t *c, struct pci_dev *pdev)
608{
609 ushort vendor_id, device_id, command;
610 unchar cache_line_size, latency_timer;
611 unchar irq, revision;
612 unsigned long addr[6];
613 __u32 board_id;
614
615 int i;
616
617 c->pci_dev = pdev;
618 if (pci_enable_device(pdev)) {
619 printk(KERN_ERR "cpqarray: Unable to Enable PCI device\n");
620 return -1;
621 }
622 vendor_id = pdev->vendor;
623 device_id = pdev->device;
624 irq = pdev->irq;
625
626 for(i=0; i<6; i++)
627 addr[i] = pci_resource_start(pdev, i);
628
629 if (pci_set_dma_mask(pdev, CPQARRAY_DMA_MASK) != 0)
630 {
631 printk(KERN_ERR "cpqarray: Unable to set DMA mask\n");
632 return -1;
633 }
634
635 pci_read_config_word(pdev, PCI_COMMAND, &command);
636 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision);
637 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line_size);
638 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency_timer);
639
640 pci_read_config_dword(pdev, 0x2c, &board_id);
641
642 /* check to see if controller has been disabled */
643 if(!(command & 0x02)) {
644 printk(KERN_WARNING
645 "cpqarray: controller appears to be disabled\n");
646 return(-1);
647 }
648
649DBGINFO(
650 printk("vendor_id = %x\n", vendor_id);
651 printk("device_id = %x\n", device_id);
652 printk("command = %x\n", command);
653 for(i=0; i<6; i++)
654 printk("addr[%d] = %lx\n", i, addr[i]);
655 printk("revision = %x\n", revision);
656 printk("irq = %x\n", irq);
657 printk("cache_line_size = %x\n", cache_line_size);
658 printk("latency_timer = %x\n", latency_timer);
659 printk("board_id = %x\n", board_id);
660);
661
662 c->intr = irq;
663
664 for(i=0; i<6; i++) {
665 if (pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE_IO)
666 { /* IO space */
667 c->io_mem_addr = addr[i];
668 c->io_mem_length = pci_resource_end(pdev, i)
669 - pci_resource_start(pdev, i) + 1;
670 if(!request_region( c->io_mem_addr, c->io_mem_length,
671 "cpqarray"))
672 {
673 printk( KERN_WARNING "cpqarray I/O memory range already in use addr %lx length = %ld\n", c->io_mem_addr, c->io_mem_length);
674 c->io_mem_addr = 0;
675 c->io_mem_length = 0;
676 }
677 break;
678 }
679 }
680
681 c->paddr = 0;
682 for(i=0; i<6; i++)
683 if (!(pci_resource_flags(pdev, i) &
684 PCI_BASE_ADDRESS_SPACE_IO)) {
685 c->paddr = pci_resource_start (pdev, i);
686 break;
687 }
688 if (!c->paddr)
689 return -1;
690 c->vaddr = remap_pci_mem(c->paddr, 128);
691 if (!c->vaddr)
692 return -1;
693 c->board_id = board_id;
694
695 for(i=0; i<NR_PRODUCTS; i++) {
696 if (board_id == products[i].board_id) {
697 c->product_name = products[i].product_name;
698 c->access = *(products[i].access);
699 break;
700 }
701 }
702 if (i == NR_PRODUCTS) {
703 printk(KERN_WARNING "cpqarray: Sorry, I don't know how"
704 " to access the SMART Array controller %08lx\n",
705 (unsigned long)board_id);
706 return -1;
707 }
708
709 return 0;
710}
711
712/*
713 * Map (physical) PCI mem into (virtual) kernel space
714 */
715static void __iomem *remap_pci_mem(ulong base, ulong size)
716{
717 ulong page_base = ((ulong) base) & PAGE_MASK;
718 ulong page_offs = ((ulong) base) - page_base;
719 void __iomem *page_remapped = ioremap(page_base, page_offs+size);
720
721 return (page_remapped ? (page_remapped + page_offs) : NULL);
722}
723
724#ifndef MODULE
725/*
726 * Config string is a comma separated set of i/o addresses of EISA cards.
727 */
728static int cpqarray_setup(char *str)
729{
730 int i, ints[9];
731
732 (void)get_options(str, ARRAY_SIZE(ints), ints);
733
734 for(i=0; i<ints[0] && i<8; i++)
735 eisa[i] = ints[i+1];
736 return 1;
737}
738
739__setup("smart2=", cpqarray_setup);
740
741#endif
742
743/*
744 * Find an EISA controller's signature. Set up an hba if we find it.
745 */
bc648638 746static int __init cpqarray_eisa_detect(void)
1da177e4
LT		 747{
748 int i=0, j;
749 __u32 board_id;
750 int intr;
751 int ctlr;
752 int num_ctlr = 0;
753
754 while(i<8 && eisa[i]) {
755 ctlr = alloc_cpqarray_hba();
756 if(ctlr == -1)
757 break;
758 board_id = inl(eisa[i]+0xC80);
759 for(j=0; j < NR_PRODUCTS; j++)
760 if (board_id == products[j].board_id)
761 break;
762
763 if (j == NR_PRODUCTS) {
764 printk(KERN_WARNING "cpqarray: Sorry, I don't know how"
765 " to access the SMART Array controller %08lx\n", (unsigned long)board_id);
766 continue;
767 }
768
769 memset(hba[ctlr], 0, sizeof(ctlr_info_t));
770 hba[ctlr]->io_mem_addr = eisa[i];
771 hba[ctlr]->io_mem_length = 0x7FF;
772 if(!request_region(hba[ctlr]->io_mem_addr,
773 hba[ctlr]->io_mem_length,
774 "cpqarray"))
775 {
776 printk(KERN_WARNING "cpqarray: I/O range already in "
777 "use addr = %lx length = %ld\n",
778 hba[ctlr]->io_mem_addr,
779 hba[ctlr]->io_mem_length);
780 free_hba(ctlr);
781 continue;
782 }
783
784 /*
785 * Read the config register to find our interrupt
786 */
787 intr = inb(eisa[i]+0xCC0) >> 4;
788 if (intr & 1) intr = 11;
789 else if (intr & 2) intr = 10;
790 else if (intr & 4) intr = 14;
791 else if (intr & 8) intr = 15;
792
793 hba[ctlr]->intr = intr;
794 sprintf(hba[ctlr]->devname, "ida%d", nr_ctlr);
795 hba[ctlr]->product_name = products[j].product_name;
796 hba[ctlr]->access = *(products[j].access);
797 hba[ctlr]->ctlr = ctlr;
798 hba[ctlr]->board_id = board_id;
799 hba[ctlr]->pci_dev = NULL; /* not PCI */
800
801DBGINFO(
802 printk("i = %d, j = %d\n", i, j);
803 printk("irq = %x\n", intr);
804 printk("product name = %s\n", products[j].product_name);
805 printk("board_id = %x\n", board_id);
806);
807
808 num_ctlr++;
809 i++;
810
811 if (cpqarray_register_ctlr(ctlr, NULL) == -1)
812 printk(KERN_WARNING
813 "cpqarray: Can't register EISA controller %d\n",
814 ctlr);
815
816 }
817
818 return num_ctlr;
819}
820
821/*
822 * Open. Make sure the device is really there.
823 */
824static int ida_open(struct inode *inode, struct file *filep)
825{
826 drv_info_t *drv = get_drv(inode->i_bdev->bd_disk);
827 ctlr_info_t *host = get_host(inode->i_bdev->bd_disk);
828
829 DBGINFO(printk("ida_open %s\n", inode->i_bdev->bd_disk->disk_name));
830 /*
831 * Root is allowed to open raw volume zero even if it's not configured
832 * so array config can still work. I don't think I really like this,
833 * but I'm already using way to many device nodes to claim another one
834 * for "raw controller".
835 */
836 if (!drv->nr_blks) {
837 if (!capable(CAP_SYS_RAWIO))
838 return -ENXIO;
839 if (!capable(CAP_SYS_ADMIN) && drv != host->drv)
840 return -ENXIO;
841 }
842 host->usage_count++;
843 return 0;
844}
845
846/*
847 * Close. Sync first.
848 */
849static int ida_release(struct inode *inode, struct file *filep)
850{
851 ctlr_info_t *host = get_host(inode->i_bdev->bd_disk);
852 host->usage_count--;
853 return 0;
854}
855
856/*
857 * Enqueuing and dequeuing functions for cmdlists.
858 */
859static inline void addQ(cmdlist_t **Qptr, cmdlist_t *c)
860{
861 if (*Qptr == NULL) {
862 *Qptr = c;
863 c->next = c->prev = c;
864 } else {
865 c->prev = (*Qptr)->prev;
866 c->next = (*Qptr);
867 (*Qptr)->prev->next = c;
868 (*Qptr)->prev = c;
869 }
870}
871
872static inline cmdlist_t *removeQ(cmdlist_t **Qptr, cmdlist_t *c)
873{
874 if (c && c->next != c) {
875 if (*Qptr == c) *Qptr = c->next;
876 c->prev->next = c->next;
877 c->next->prev = c->prev;
878 } else {
879 *Qptr = NULL;
880 }
881 return c;
882}
883
884/*
885 * Get a request and submit it to the controller.
886 * This routine needs to grab all the requests it possibly can from the
887 * req Q and submit them. Interrupts are off (and need to be off) when you
888 * are in here (either via the dummy do_ida_request functions or by being
889 * called from the interrupt handler
890 */
891static void do_ida_request(request_queue_t *q)
892{
893 ctlr_info_t *h = q->queuedata;
894 cmdlist_t *c;
895 struct request *creq;
896 struct scatterlist tmp_sg[SG_MAX];
897 int i, dir, seg;
898
899 if (blk_queue_plugged(q))
900 goto startio;
901
902queue_next:
903 creq = elv_next_request(q);
904 if (!creq)
905 goto startio;
906
089fe1b2 907 BUG_ON(creq->nr_phys_segments > SG_MAX);
1da177e4
LT		 908
909 if ((c = cmd_alloc(h,1)) == NULL)
910 goto startio;
911
912 blkdev_dequeue_request(creq);
913
914 c->ctlr = h->ctlr;
915 c->hdr.unit = (drv_info_t *)(creq->rq_disk->private_data) - h->drv;
916 c->hdr.size = sizeof(rblk_t) >> 2;
917 c->size += sizeof(rblk_t);
918
919 c->req.hdr.blk = creq->sector;
920 c->rq = creq;
921DBGPX(
922 printk("sector=%d, nr_sectors=%d\n", creq->sector, creq->nr_sectors);
923);
924 seg = blk_rq_map_sg(q, creq, tmp_sg);
925
926 /* Now do all the DMA Mappings */
927 if (rq_data_dir(creq) == READ)
928 dir = PCI_DMA_FROMDEVICE;
929 else
930 dir = PCI_DMA_TODEVICE;
931 for( i=0; i < seg; i++)
932 {
933 c->req.sg[i].size = tmp_sg[i].length;
934 c->req.sg[i].addr = (__u32) pci_map_page(h->pci_dev,
935 tmp_sg[i].page,
936 tmp_sg[i].offset,
937 tmp_sg[i].length, dir);
938 }
939DBGPX( printk("Submitting %d sectors in %d segments\n", creq->nr_sectors, seg); );
940 c->req.hdr.sg_cnt = seg;
941 c->req.hdr.blk_cnt = creq->nr_sectors;
942 c->req.hdr.cmd = (rq_data_dir(creq) == READ) ? IDA_READ : IDA_WRITE;
943 c->type = CMD_RWREQ;
944
945 /* Put the request on the tail of the request queue */
946 addQ(&h->reqQ, c);
947 h->Qdepth++;
948 if (h->Qdepth > h->maxQsinceinit)
949 h->maxQsinceinit = h->Qdepth;
950
951 goto queue_next;
952
953startio:
954 start_io(h);
955}
956
957/*
958 * start_io submits everything on a controller's request queue
959 * and moves it to the completion queue.
960 *
961 * Interrupts had better be off if you're in here
962 */
963static void start_io(ctlr_info_t *h)
964{
965 cmdlist_t *c;
966
967 while((c = h->reqQ) != NULL) {
968 /* Can't do anything if we're busy */
969 if (h->access.fifo_full(h) == 0)
970 return;
971
972 /* Get the first entry from the request Q */
973 removeQ(&h->reqQ, c);
974 h->Qdepth--;
975
976 /* Tell the controller to do our bidding */
977 h->access.submit_command(h, c);
978
979 /* Get onto the completion Q */
980 addQ(&h->cmpQ, c);
981 }
982}
983
984static inline void complete_buffers(struct bio *bio, int ok)
985{
986 struct bio *xbh;
987 while(bio) {
988 int nr_sectors = bio_sectors(bio);
989
990 xbh = bio->bi_next;
991 bio->bi_next = NULL;
992
993 blk_finished_io(nr_sectors);
994 bio_endio(bio, nr_sectors << 9, ok ? 0 : -EIO);
995
996 bio = xbh;
997 }
998}
999/*
1000 * Mark all buffers that cmd was responsible for
1001 */
1002static inline void complete_command(cmdlist_t *cmd, int timeout)
1003{
1004 int ok=1;
1005 int i, ddir;
1006
1007 if (cmd->req.hdr.rcode & RCODE_NONFATAL &&
1008 (hba[cmd->ctlr]->misc_tflags & MISC_NONFATAL_WARN) == 0) {
1009 printk(KERN_NOTICE "Non Fatal error on ida/c%dd%d\n",
1010 cmd->ctlr, cmd->hdr.unit);
1011 hba[cmd->ctlr]->misc_tflags |= MISC_NONFATAL_WARN;
1012 }
1013 if (cmd->req.hdr.rcode & RCODE_FATAL) {
1014 printk(KERN_WARNING "Fatal error on ida/c%dd%d\n",
1015 cmd->ctlr, cmd->hdr.unit);
1016 ok = 0;
1017 }
1018 if (cmd->req.hdr.rcode & RCODE_INVREQ) {
1019 printk(KERN_WARNING "Invalid request on ida/c%dd%d = (cmd=%x sect=%d cnt=%d sg=%d ret=%x)\n",
1020 cmd->ctlr, cmd->hdr.unit, cmd->req.hdr.cmd,
1021 cmd->req.hdr.blk, cmd->req.hdr.blk_cnt,
1022 cmd->req.hdr.sg_cnt, cmd->req.hdr.rcode);
1023 ok = 0;
1024 }
1025 if (timeout) ok = 0;
1026 /* unmap the DMA mapping for all the scatter gather elements */
1027 if (cmd->req.hdr.cmd == IDA_READ)
1028 ddir = PCI_DMA_FROMDEVICE;
1029 else
1030 ddir = PCI_DMA_TODEVICE;
1031 for(i=0; i<cmd->req.hdr.sg_cnt; i++)
1032 pci_unmap_page(hba[cmd->ctlr]->pci_dev, cmd->req.sg[i].addr,
1033 cmd->req.sg[i].size, ddir);
1034
1035 complete_buffers(cmd->rq->bio, ok);
1036
0f41a53a
MM		 1037 add_disk_randomness(cmd->rq->rq_disk);
1038
1da177e4 1039 DBGPX(printk("Done with %p\n", cmd->rq););
8ffdc655 1040 end_that_request_last(cmd->rq, ok ? 1 : -EIO);
1da177e4
LT		 1041}
1042
1043/*
1044 * The controller will interrupt us upon completion of commands.
1045 * Find the command on the completion queue, remove it, tell the OS and
1046 * try to queue up more IO
1047 */
1048static irqreturn_t do_ida_intr(int irq, void *dev_id, struct pt_regs *regs)
1049{
1050 ctlr_info_t *h = dev_id;
1051 cmdlist_t *c;
1052 unsigned long istat;
1053 unsigned long flags;
1054 __u32 a,a1;
1055
1056 istat = h->access.intr_pending(h);
1057 /* Is this interrupt for us? */
1058 if (istat == 0)
1059 return IRQ_NONE;
1060
1061 /*
1062 * If there are completed commands in the completion queue,
1063 * we had better do something about it.
1064 */
1065 spin_lock_irqsave(IDA_LOCK(h->ctlr), flags);
1066 if (istat & FIFO_NOT_EMPTY) {
1067 while((a = h->access.command_completed(h))) {
1068 a1 = a; a &= ~3;
1069 if ((c = h->cmpQ) == NULL)
1070 {
1071 printk(KERN_WARNING "cpqarray: Completion of %08lx ignored\n", (unsigned long)a1);
1072 continue;
1073 }
1074 while(c->busaddr != a) {
1075 c = c->next;
1076 if (c == h->cmpQ)
1077 break;
1078 }
1079 /*
1080 * If we've found the command, take it off the
1081 * completion Q and free it
1082 */
1083 if (c->busaddr == a) {
1084 removeQ(&h->cmpQ, c);
1085 /* Check for invalid command.
1086 * Controller returns command error,
1087 * But rcode = 0.
1088 */
1089
1090 if((a1 & 0x03) && (c->req.hdr.rcode == 0))
1091 {
1092 c->req.hdr.rcode = RCODE_INVREQ;
1093 }
1094 if (c->type == CMD_RWREQ) {
1095 complete_command(c, 0);
1096 cmd_free(h, c, 1);
1097 } else if (c->type == CMD_IOCTL_PEND) {
1098 c->type = CMD_IOCTL_DONE;
1099 }
1100 continue;
1101 }
1102 }
1103 }
1104
1105 /*
1106 * See if we can queue up some more IO
1107 */
1108 do_ida_request(h->queue);
1109 spin_unlock_irqrestore(IDA_LOCK(h->ctlr), flags);
1110 return IRQ_HANDLED;
1111}
1112
1113/*
1114 * This timer was for timing out requests that haven't happened after
1115 * IDA_TIMEOUT. That wasn't such a good idea. This timer is used to
1116 * reset a flags structure so we don't flood the user with
1117 * "Non-Fatal error" messages.
1118 */
1119static void ida_timer(unsigned long tdata)
1120{
1121 ctlr_info_t *h = (ctlr_info_t*)tdata;
1122
1123 h->timer.expires = jiffies + IDA_TIMER;
1124 add_timer(&h->timer);
1125 h->misc_tflags = 0;
1126}
1127
a885c8c4
CH		 1128static int ida_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1129{
1130 drv_info_t *drv = get_drv(bdev->bd_disk);
1131
1132 if (drv->cylinders) {
1133 geo->heads = drv->heads;
1134 geo->sectors = drv->sectors;
1135 geo->cylinders = drv->cylinders;
1136 } else {
1137 geo->heads = 0xff;
1138 geo->sectors = 0x3f;
1139 geo->cylinders = drv->nr_blks / (0xff*0x3f);
1140 }
1141
1142 return 0;
1143}
1144
1da177e4
LT		 1145/*
1146 * ida_ioctl does some miscellaneous stuff like reporting drive geometry,
1147 * setting readahead and submitting commands from userspace to the controller.
1148 */
1149static int ida_ioctl(struct inode *inode, struct file *filep, unsigned int cmd, unsigned long arg)
1150{
1151 drv_info_t *drv = get_drv(inode->i_bdev->bd_disk);
1152 ctlr_info_t *host = get_host(inode->i_bdev->bd_disk);
1153 int error;
1da177e4
LT		 1154 ida_ioctl_t __user *io = (ida_ioctl_t __user *)arg;
1155 ida_ioctl_t *my_io;
1156
1157 switch(cmd) {
1da177e4
LT		 1158 case IDAGETDRVINFO:
1159 if (copy_to_user(&io->c.drv, drv, sizeof(drv_info_t)))
1160 return -EFAULT;
1161 return 0;
1162 case IDAPASSTHRU:
1163 if (!capable(CAP_SYS_RAWIO))
1164 return -EPERM;
1165 my_io = kmalloc(sizeof(ida_ioctl_t), GFP_KERNEL);
1166 if (!my_io)
1167 return -ENOMEM;
1168 error = -EFAULT;
1169 if (copy_from_user(my_io, io, sizeof(*my_io)))
1170 goto out_passthru;
1171 error = ida_ctlr_ioctl(host, drv - host->drv, my_io);
1172 if (error)
1173 goto out_passthru;
1174 error = -EFAULT;
1175 if (copy_to_user(io, my_io, sizeof(*my_io)))
1176 goto out_passthru;
1177 error = 0;
1178out_passthru:
1179 kfree(my_io);
1180 return error;
1181 case IDAGETCTLRSIG:
1182 if (!arg) return -EINVAL;
1183 put_user(host->ctlr_sig, (int __user *)arg);
1184 return 0;
1185 case IDAREVALIDATEVOLS:
1186 if (iminor(inode) != 0)
1187 return -ENXIO;
1188 return revalidate_allvol(host);
1189 case IDADRIVERVERSION:
1190 if (!arg) return -EINVAL;
1191 put_user(DRIVER_VERSION, (unsigned long __user *)arg);
1192 return 0;
1193 case IDAGETPCIINFO:
1194 {
1195
1196 ida_pci_info_struct pciinfo;
1197
1198 if (!arg) return -EINVAL;
1199 pciinfo.bus = host->pci_dev->bus->number;
1200 pciinfo.dev_fn = host->pci_dev->devfn;
1201 pciinfo.board_id = host->board_id;
1202 if(copy_to_user((void __user *) arg, &pciinfo,
1203 sizeof( ida_pci_info_struct)))
1204 return -EFAULT;
1205 return(0);
1206 }
1207
1208 default:
1209 return -EINVAL;
1210 }
1211
1212}
1213/*
1214 * ida_ctlr_ioctl is for passing commands to the controller from userspace.
1215 * The command block (io) has already been copied to kernel space for us,
1216 * however, any elements in the sglist need to be copied to kernel space
1217 * or copied back to userspace.
1218 *
1219 * Only root may perform a controller passthru command, however I'm not doing
1220 * any serious sanity checking on the arguments. Doing an IDA_WRITE_MEDIA and
1221 * putting a 64M buffer in the sglist is probably a *bad* idea.
1222 */
1223static int ida_ctlr_ioctl(ctlr_info_t *h, int dsk, ida_ioctl_t *io)
1224{
1225 int ctlr = h->ctlr;
1226 cmdlist_t *c;
1227 void *p = NULL;
1228 unsigned long flags;
1229 int error;
1230
1231 if ((c = cmd_alloc(h, 0)) == NULL)
1232 return -ENOMEM;
1233 c->ctlr = ctlr;
1234 c->hdr.unit = (io->unit & UNITVALID) ? (io->unit & ~UNITVALID) : dsk;
1235 c->hdr.size = sizeof(rblk_t) >> 2;
1236 c->size += sizeof(rblk_t);
1237
1238 c->req.hdr.cmd = io->cmd;
1239 c->req.hdr.blk = io->blk;
1240 c->req.hdr.blk_cnt = io->blk_cnt;
1241 c->type = CMD_IOCTL_PEND;
1242
1243 /* Pre submit processing */
1244 switch(io->cmd) {
1245 case PASSTHRU_A:
1246 p = kmalloc(io->sg[0].size, GFP_KERNEL);
1247 if (!p)
1248 {
1249 error = -ENOMEM;
1250 cmd_free(h, c, 0);
1251 return(error);
1252 }
1253 if (copy_from_user(p, io->sg[0].addr, io->sg[0].size)) {
1254 kfree(p);
1255 cmd_free(h, c, 0);
1256 return -EFAULT;
1257 }
1258 c->req.hdr.blk = pci_map_single(h->pci_dev, &(io->c),
1259 sizeof(ida_ioctl_t),
1260 PCI_DMA_BIDIRECTIONAL);
1261 c->req.sg[0].size = io->sg[0].size;
1262 c->req.sg[0].addr = pci_map_single(h->pci_dev, p,
1263 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1264 c->req.hdr.sg_cnt = 1;
1265 break;
1266 case IDA_READ:
1267 case READ_FLASH_ROM:
1268 case SENSE_CONTROLLER_PERFORMANCE:
1269 p = kmalloc(io->sg[0].size, GFP_KERNEL);
1270 if (!p)
1271 {
1272 error = -ENOMEM;
1273 cmd_free(h, c, 0);
1274 return(error);
1275 }
1276
1277 c->req.sg[0].size = io->sg[0].size;
1278 c->req.sg[0].addr = pci_map_single(h->pci_dev, p,
1279 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1280 c->req.hdr.sg_cnt = 1;
1281 break;
1282 case IDA_WRITE:
1283 case IDA_WRITE_MEDIA:
1284 case DIAG_PASS_THRU:
1285 case COLLECT_BUFFER:
1286 case WRITE_FLASH_ROM:
1287 p = kmalloc(io->sg[0].size, GFP_KERNEL);
1288 if (!p)
1289 {
1290 error = -ENOMEM;
1291 cmd_free(h, c, 0);
1292 return(error);
1293 }
1294 if (copy_from_user(p, io->sg[0].addr, io->sg[0].size)) {
1295 kfree(p);
1296 cmd_free(h, c, 0);
1297 return -EFAULT;
1298 }
1299 c->req.sg[0].size = io->sg[0].size;
1300 c->req.sg[0].addr = pci_map_single(h->pci_dev, p,
1301 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1302 c->req.hdr.sg_cnt = 1;
1303 break;
1304 default:
1305 c->req.sg[0].size = sizeof(io->c);
1306 c->req.sg[0].addr = pci_map_single(h->pci_dev,&io->c,
1307 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1308 c->req.hdr.sg_cnt = 1;
1309 }
1310
1311 /* Put the request on the tail of the request queue */
1312 spin_lock_irqsave(IDA_LOCK(ctlr), flags);
1313 addQ(&h->reqQ, c);
1314 h->Qdepth++;
1315 start_io(h);
1316 spin_unlock_irqrestore(IDA_LOCK(ctlr), flags);
1317
1318 /* Wait for completion */
1319 while(c->type != CMD_IOCTL_DONE)
1320 schedule();
1321
1322 /* Unmap the DMA */
1323 pci_unmap_single(h->pci_dev, c->req.sg[0].addr, c->req.sg[0].size,
1324 PCI_DMA_BIDIRECTIONAL);
1325 /* Post submit processing */
1326 switch(io->cmd) {
1327 case PASSTHRU_A:
1328 pci_unmap_single(h->pci_dev, c->req.hdr.blk,
1329 sizeof(ida_ioctl_t),
1330 PCI_DMA_BIDIRECTIONAL);
1331 case IDA_READ:
1332 case DIAG_PASS_THRU:
1333 case SENSE_CONTROLLER_PERFORMANCE:
1334 case READ_FLASH_ROM:
1335 if (copy_to_user(io->sg[0].addr, p, io->sg[0].size)) {
1336 kfree(p);
1337 return -EFAULT;
1338 }
1339 /* fall through and free p */
1340 case IDA_WRITE:
1341 case IDA_WRITE_MEDIA:
1342 case COLLECT_BUFFER:
1343 case WRITE_FLASH_ROM:
1344 kfree(p);
1345 break;
1346 default:;
1347 /* Nothing to do */
1348 }
1349
1350 io->rcode = c->req.hdr.rcode;
1351 cmd_free(h, c, 0);
1352 return(0);
1353}
1354
1355/*
1356 * Commands are pre-allocated in a large block. Here we use a simple bitmap
1357 * scheme to suballocte them to the driver. Operations that are not time
1358 * critical (and can wait for kmalloc and possibly sleep) can pass in NULL
1359 * as the first argument to get a new command.
1360 */
1361static cmdlist_t * cmd_alloc(ctlr_info_t *h, int get_from_pool)
1362{
1363 cmdlist_t * c;
1364 int i;
1365 dma_addr_t cmd_dhandle;
1366
1367 if (!get_from_pool) {
1368 c = (cmdlist_t*)pci_alloc_consistent(h->pci_dev,
1369 sizeof(cmdlist_t), &cmd_dhandle);
1370 if(c==NULL)
1371 return NULL;
1372 } else {
1373 do {
1374 i = find_first_zero_bit(h->cmd_pool_bits, NR_CMDS);
1375 if (i == NR_CMDS)
1376 return NULL;
1377 } while(test_and_set_bit(i&(BITS_PER_LONG-1), h->cmd_pool_bits+(i/BITS_PER_LONG)) != 0);
1378 c = h->cmd_pool + i;
1379 cmd_dhandle = h->cmd_pool_dhandle + i*sizeof(cmdlist_t);
1380 h->nr_allocs++;
1381 }
1382
1383 memset(c, 0, sizeof(cmdlist_t));
1384 c->busaddr = cmd_dhandle;
1385 return c;
1386}
1387
1388static void cmd_free(ctlr_info_t *h, cmdlist_t *c, int got_from_pool)
1389{
1390 int i;
1391
1392 if (!got_from_pool) {
1393 pci_free_consistent(h->pci_dev, sizeof(cmdlist_t), c,
1394 c->busaddr);
1395 } else {
1396 i = c - h->cmd_pool;
1397 clear_bit(i&(BITS_PER_LONG-1), h->cmd_pool_bits+(i/BITS_PER_LONG));
1398 h->nr_frees++;
1399 }
1400}
1401
1402/***********************************************************************
1403 name: sendcmd
1404 Send a command to an IDA using the memory mapped FIFO interface
1405 and wait for it to complete.
1406 This routine should only be called at init time.
1407***********************************************************************/
1408static int sendcmd(
1409 __u8 cmd,
1410 int ctlr,
1411 void *buff,
1412 size_t size,
1413 unsigned int blk,
1414 unsigned int blkcnt,
1415 unsigned int log_unit )
1416{
1417 cmdlist_t *c;
1418 int complete;
1419 unsigned long temp;
1420 unsigned long i;
1421 ctlr_info_t *info_p = hba[ctlr];
1422
1423 c = cmd_alloc(info_p, 1);
1424 if(!c)
1425 return IO_ERROR;
1426 c->ctlr = ctlr;
1427 c->hdr.unit = log_unit;
1428 c->hdr.prio = 0;
1429 c->hdr.size = sizeof(rblk_t) >> 2;
1430 c->size += sizeof(rblk_t);
1431
1432 /* The request information. */
1433 c->req.hdr.next = 0;
1434 c->req.hdr.rcode = 0;
1435 c->req.bp = 0;
1436 c->req.hdr.sg_cnt = 1;
1437 c->req.hdr.reserved = 0;
1438
1439 if (size == 0)
1440 c->req.sg[0].size = 512;
1441 else
1442 c->req.sg[0].size = size;
1443
1444 c->req.hdr.blk = blk;
1445 c->req.hdr.blk_cnt = blkcnt;
1446 c->req.hdr.cmd = (unsigned char) cmd;
1447 c->req.sg[0].addr = (__u32) pci_map_single(info_p->pci_dev,
1448 buff, c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1449 /*
1450 * Disable interrupt
1451 */
1452 info_p->access.set_intr_mask(info_p, 0);
1453 /* Make sure there is room in the command FIFO */
1454 /* Actually it should be completely empty at this time. */
1455 for (i = 200000; i > 0; i--) {
1456 temp = info_p->access.fifo_full(info_p);
1457 if (temp != 0) {
1458 break;
1459 }
1460 udelay(10);
1461DBG(
1462 printk(KERN_WARNING "cpqarray ida%d: idaSendPciCmd FIFO full,"
1463 " waiting!\n", ctlr);
1464);
1465 }
1466 /*
1467 * Send the cmd
1468 */
1469 info_p->access.submit_command(info_p, c);
1470 complete = pollcomplete(ctlr);
1471
1472 pci_unmap_single(info_p->pci_dev, (dma_addr_t) c->req.sg[0].addr,
1473 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1474 if (complete != 1) {
1475 if (complete != c->busaddr) {
1476 printk( KERN_WARNING
1477 "cpqarray ida%d: idaSendPciCmd "
1478 "Invalid command list address returned! (%08lx)\n",
1479 ctlr, (unsigned long)complete);
1480 cmd_free(info_p, c, 1);
1481 return (IO_ERROR);
1482 }
1483 } else {
1484 printk( KERN_WARNING
1485 "cpqarray ida%d: idaSendPciCmd Timeout out, "
1486 "No command list address returned!\n",
1487 ctlr);
1488 cmd_free(info_p, c, 1);
1489 return (IO_ERROR);
1490 }
1491
1492 if (c->req.hdr.rcode & 0x00FE) {
1493 if (!(c->req.hdr.rcode & BIG_PROBLEM)) {
1494 printk( KERN_WARNING
1495 "cpqarray ida%d: idaSendPciCmd, error: "
1496 "Controller failed at init time "
1497 "cmd: 0x%x, return code = 0x%x\n",
1498 ctlr, c->req.hdr.cmd, c->req.hdr.rcode);
1499
1500 cmd_free(info_p, c, 1);
1501 return (IO_ERROR);
1502 }
1503 }
1504 cmd_free(info_p, c, 1);
1505 return (IO_OK);
1506}
1507
1508/*
1509 * revalidate_allvol is for online array config utilities. After a
1510 * utility reconfigures the drives in the array, it can use this function
1511 * (through an ioctl) to make the driver zap any previous disk structs for
1512 * that controller and get new ones.
1513 *
1514 * Right now I'm using the getgeometry() function to do this, but this
1515 * function should probably be finer grained and allow you to revalidate one
1516 * particualar logical volume (instead of all of them on a particular
1517 * controller).
1518 */
1519static int revalidate_allvol(ctlr_info_t *host)
1520{
1521 int ctlr = host->ctlr;
1522 int i;
1523 unsigned long flags;
1524
1525 spin_lock_irqsave(IDA_LOCK(ctlr), flags);
1526 if (host->usage_count > 1) {
1527 spin_unlock_irqrestore(IDA_LOCK(ctlr), flags);
1528 printk(KERN_WARNING "cpqarray: Device busy for volume"
1529 " revalidation (usage=%d)\n", host->usage_count);
1530 return -EBUSY;
1531 }
1532 host->usage_count++;
1533 spin_unlock_irqrestore(IDA_LOCK(ctlr), flags);
1534
1535 /*
1536 * Set the partition and block size structures for all volumes
1537 * on this controller to zero. We will reread all of this data
1538 */
1539 set_capacity(ida_gendisk[ctlr][0], 0);
1540 for (i = 1; i < NWD; i++) {
1541 struct gendisk *disk = ida_gendisk[ctlr][i];
1542 if (disk->flags & GENHD_FL_UP)
1543 del_gendisk(disk);
1544 }
1545 memset(host->drv, 0, sizeof(drv_info_t)*NWD);
1546
1547 /*
1548 * Tell the array controller not to give us any interrupts while
1549 * we check the new geometry. Then turn interrupts back on when
1550 * we're done.
1551 */
1552 host->access.set_intr_mask(host, 0);
1553 getgeometry(ctlr);
1554 host->access.set_intr_mask(host, FIFO_NOT_EMPTY);
1555
1556 for(i=0; i<NWD; i++) {
1557 struct gendisk *disk = ida_gendisk[ctlr][i];
1558 drv_info_t *drv = &host->drv[i];
1559 if (i && !drv->nr_blks)
1560 continue;
1561 blk_queue_hardsect_size(host->queue, drv->blk_size);
1562 set_capacity(disk, drv->nr_blks);
1563 disk->queue = host->queue;
1564 disk->private_data = drv;
1565 if (i)
1566 add_disk(disk);
1567 }
1568
1569 host->usage_count--;
1570 return 0;
1571}
1572
1573static int ida_revalidate(struct gendisk *disk)
1574{
1575 drv_info_t *drv = disk->private_data;
1576 set_capacity(disk, drv->nr_blks);
1577 return 0;
1578}
1579
1580/********************************************************************
1581 name: pollcomplete
1582 Wait polling for a command to complete.
1583 The memory mapped FIFO is polled for the completion.
1584 Used only at init time, interrupts disabled.
1585 ********************************************************************/
1586static int pollcomplete(int ctlr)
1587{
1588 int done;
1589 int i;
1590
1591 /* Wait (up to 2 seconds) for a command to complete */
1592
1593 for (i = 200000; i > 0; i--) {
1594 done = hba[ctlr]->access.command_completed(hba[ctlr]);
1595 if (done == 0) {
1596 udelay(10); /* a short fixed delay */
1597 } else
1598 return (done);
1599 }
1600 /* Invalid address to tell caller we ran out of time */
1601 return 1;
1602}
1603/*****************************************************************
1604 start_fwbk
1605 Starts controller firmwares background processing.
1606 Currently only the Integrated Raid controller needs this done.
1607 If the PCI mem address registers are written to after this,
1608 data corruption may occur
1609*****************************************************************/
1610static void start_fwbk(int ctlr)
1611{
1612 id_ctlr_t *id_ctlr_buf;
1613 int ret_code;
1614
1615 if( (hba[ctlr]->board_id != 0x40400E11)
1616 && (hba[ctlr]->board_id != 0x40480E11) )
1617
1618 /* Not a Integrated Raid, so there is nothing for us to do */
1619 return;
1620 printk(KERN_DEBUG "cpqarray: Starting firmware's background"
1621 " processing\n");
1622 /* Command does not return anything, but idasend command needs a
1623 buffer */
1624 id_ctlr_buf = (id_ctlr_t *)kmalloc(sizeof(id_ctlr_t), GFP_KERNEL);
1625 if(id_ctlr_buf==NULL)
1626 {
1627 printk(KERN_WARNING "cpqarray: Out of memory. "
1628 "Unable to start background processing.\n");
1629 return;
1630 }
1631 ret_code = sendcmd(RESUME_BACKGROUND_ACTIVITY, ctlr,
1632 id_ctlr_buf, 0, 0, 0, 0);
1633 if(ret_code != IO_OK)
1634 printk(KERN_WARNING "cpqarray: Unable to start"
1635 " background processing\n");
1636
1637 kfree(id_ctlr_buf);
1638}
1639/*****************************************************************
1640 getgeometry
1641 Get ida logical volume geometry from the controller
1642 This is a large bit of code which once existed in two flavors,
1643 It is used only at init time.
1644*****************************************************************/
1645static void getgeometry(int ctlr)
1646{
1647 id_log_drv_t *id_ldrive;
1648 id_ctlr_t *id_ctlr_buf;
1649 sense_log_drv_stat_t *id_lstatus_buf;
1650 config_t *sense_config_buf;
1651 unsigned int log_unit, log_index;
1652 int ret_code, size;
1653 drv_info_t *drv;
1654 ctlr_info_t *info_p = hba[ctlr];
1655 int i;
1656
1657 info_p->log_drv_map = 0;
1658
1659 id_ldrive = (id_log_drv_t *)kmalloc(sizeof(id_log_drv_t), GFP_KERNEL);
1660 if(id_ldrive == NULL)
1661 {
1662 printk( KERN_ERR "cpqarray: out of memory.\n");
1663 return;
1664 }
1665
1666 id_ctlr_buf = (id_ctlr_t *)kmalloc(sizeof(id_ctlr_t), GFP_KERNEL);
1667 if(id_ctlr_buf == NULL)
1668 {
1669 kfree(id_ldrive);
1670 printk( KERN_ERR "cpqarray: out of memory.\n");
1671 return;
1672 }
1673
1674 id_lstatus_buf = (sense_log_drv_stat_t *)kmalloc(sizeof(sense_log_drv_stat_t), GFP_KERNEL);
1675 if(id_lstatus_buf == NULL)
1676 {
1677 kfree(id_ctlr_buf);
1678 kfree(id_ldrive);
1679 printk( KERN_ERR "cpqarray: out of memory.\n");
1680 return;
1681 }
1682
1683 sense_config_buf = (config_t *)kmalloc(sizeof(config_t), GFP_KERNEL);
1684 if(sense_config_buf == NULL)
1685 {
1686 kfree(id_lstatus_buf);
1687 kfree(id_ctlr_buf);
1688 kfree(id_ldrive);
1689 printk( KERN_ERR "cpqarray: out of memory.\n");
1690 return;
1691 }
1692
1693 memset(id_ldrive, 0, sizeof(id_log_drv_t));
1694 memset(id_ctlr_buf, 0, sizeof(id_ctlr_t));
1695 memset(id_lstatus_buf, 0, sizeof(sense_log_drv_stat_t));
1696 memset(sense_config_buf, 0, sizeof(config_t));
1697
1698 info_p->phys_drives = 0;
1699 info_p->log_drv_map = 0;
1700 info_p->drv_assign_map = 0;
1701 info_p->drv_spare_map = 0;
1702 info_p->mp_failed_drv_map = 0; /* only initialized here */
1703 /* Get controllers info for this logical drive */
1704 ret_code = sendcmd(ID_CTLR, ctlr, id_ctlr_buf, 0, 0, 0, 0);
1705 if (ret_code == IO_ERROR) {
1706 /*
1707 * If can't get controller info, set the logical drive map to 0,
1708 * so the idastubopen will fail on all logical drives
1709 * on the controller.
1710 */
1711 /* Free all the buffers and return */
1712 printk(KERN_ERR "cpqarray: error sending ID controller\n");
1713 kfree(sense_config_buf);
1714 kfree(id_lstatus_buf);
1715 kfree(id_ctlr_buf);
1716 kfree(id_ldrive);
1717 return;
1718 }
1719
1720 info_p->log_drives = id_ctlr_buf->nr_drvs;
1721 for(i=0;i<4;i++)
1722 info_p->firm_rev[i] = id_ctlr_buf->firm_rev[i];
1723 info_p->ctlr_sig = id_ctlr_buf->cfg_sig;
1724
1725 printk(" (%s)\n", info_p->product_name);
1726 /*
1727 * Initialize logical drive map to zero
1728 */
1729 log_index = 0;
1730 /*
1731 * Get drive geometry for all logical drives
1732 */
1733 if (id_ctlr_buf->nr_drvs > 16)
1734 printk(KERN_WARNING "cpqarray ida%d: This driver supports "
1735 "16 logical drives per controller.\n. "
1736 " Additional drives will not be "
1737 "detected\n", ctlr);
1738
1739 for (log_unit = 0;
1740 (log_index < id_ctlr_buf->nr_drvs)
1741 && (log_unit < NWD);
1742 log_unit++) {
1743 struct gendisk *disk = ida_gendisk[ctlr][log_unit];
1744
1745 size = sizeof(sense_log_drv_stat_t);
1746
1747 /*
1748 Send "Identify logical drive status" cmd
1749 */
1750 ret_code = sendcmd(SENSE_LOG_DRV_STAT,
1751 ctlr, id_lstatus_buf, size, 0, 0, log_unit);
1752 if (ret_code == IO_ERROR) {
1753 /*
1754 If can't get logical drive status, set
1755 the logical drive map to 0, so the
1756 idastubopen will fail for all logical drives
1757 on the controller.
1758 */
1759 info_p->log_drv_map = 0;
1760 printk( KERN_WARNING
1761 "cpqarray ida%d: idaGetGeometry - Controller"
1762 " failed to report status of logical drive %d\n"
1763 "Access to this controller has been disabled\n",
1764 ctlr, log_unit);
1765 /* Free all the buffers and return */
1766 kfree(sense_config_buf);
1767 kfree(id_lstatus_buf);
1768 kfree(id_ctlr_buf);
1769 kfree(id_ldrive);
1770 return;
1771 }
1772 /*
1773 Make sure the logical drive is configured
1774 */
1775 if (id_lstatus_buf->status != LOG_NOT_CONF) {
1776 ret_code = sendcmd(ID_LOG_DRV, ctlr, id_ldrive,
1777 sizeof(id_log_drv_t), 0, 0, log_unit);
1778 /*
1779 If error, the bit for this
1780 logical drive won't be set and
1781 idastubopen will return error.
1782 */
1783 if (ret_code != IO_ERROR) {
1784 drv = &info_p->drv[log_unit];
1785 drv->blk_size = id_ldrive->blk_size;
1786 drv->nr_blks = id_ldrive->nr_blks;
1787 drv->cylinders = id_ldrive->drv.cyl;
1788 drv->heads = id_ldrive->drv.heads;
1789 drv->sectors = id_ldrive->drv.sect_per_track;
1790 info_p->log_drv_map |= (1 << log_unit);
1791
1792 printk(KERN_INFO "cpqarray ida/c%dd%d: blksz=%d nr_blks=%d\n",
1793 ctlr, log_unit, drv->blk_size, drv->nr_blks);
1794 ret_code = sendcmd(SENSE_CONFIG,
1795 ctlr, sense_config_buf,
1796 sizeof(config_t), 0, 0, log_unit);
1797 if (ret_code == IO_ERROR) {
1798 info_p->log_drv_map = 0;
1799 /* Free all the buffers and return */
1800 printk(KERN_ERR "cpqarray: error sending sense config\n");
1801 kfree(sense_config_buf);
1802 kfree(id_lstatus_buf);
1803 kfree(id_ctlr_buf);
1804 kfree(id_ldrive);
1805 return;
1806
1807 }
1808
1809 sprintf(disk->devfs_name, "ida/c%dd%d", ctlr, log_unit);
1810
1811 info_p->phys_drives =
1812 sense_config_buf->ctlr_phys_drv;
1813 info_p->drv_assign_map
1814 |= sense_config_buf->drv_asgn_map;
1815 info_p->drv_assign_map
1816 |= sense_config_buf->spare_asgn_map;
1817 info_p->drv_spare_map
1818 |= sense_config_buf->spare_asgn_map;
1819 } /* end of if no error on id_ldrive */
1820 log_index = log_index + 1;
1821 } /* end of if logical drive configured */
1822 } /* end of for log_unit */
1823 kfree(sense_config_buf);
1824 kfree(id_ldrive);
1825 kfree(id_lstatus_buf);
1826 kfree(id_ctlr_buf);
1827 return;
1828
1829}
1830
1831static void __exit cpqarray_exit(void)
1832{
1833 int i;
1834
1835 pci_unregister_driver(&cpqarray_pci_driver);
1836
1837 /* Double check that all controller entries have been removed */
1838 for(i=0; i<MAX_CTLR; i++) {
1839 if (hba[i] != NULL) {
1840 printk(KERN_WARNING "cpqarray: Removing EISA "
1841 "controller %d\n", i);
1842 cpqarray_remove_one_eisa(i);
1843 }
1844 }
1845
1da177e4
LT		 1846 remove_proc_entry("cpqarray", proc_root_driver);
1847}
1848
1849module_init(cpqarray_init)
1850module_exit(cpqarray_exit)
kernel source for telekom puls (alcatel/mediatek)