[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / sata_vsc.c

/*
 *  sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
 *
 *  Maintained by:  Jeremy Higdon @ SGI
 * 		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2004 SGI
 *
 *  Bits from Jeff Garzik, Copyright RedHat, Inc.
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Vitesse hardware documentation presumably available under NDA.
 *  Intel 31244 (same hardware interface) documentation presumably
 *  available from http://developer.intel.com/
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"sata_vsc"
#define DRV_VERSION	"2.3"

enum {
	VSC_MMIO_BAR			= 0,

	/* Interrupt register offsets (from chip base address) */
	VSC_SATA_INT_STAT_OFFSET	= 0x00,
	VSC_SATA_INT_MASK_OFFSET	= 0x04,

	/* Taskfile registers offsets */
	VSC_SATA_TF_CMD_OFFSET		= 0x00,
	VSC_SATA_TF_DATA_OFFSET		= 0x00,
	VSC_SATA_TF_ERROR_OFFSET	= 0x04,
	VSC_SATA_TF_FEATURE_OFFSET	= 0x06,
	VSC_SATA_TF_NSECT_OFFSET	= 0x08,
	VSC_SATA_TF_LBAL_OFFSET		= 0x0c,
	VSC_SATA_TF_LBAM_OFFSET		= 0x10,
	VSC_SATA_TF_LBAH_OFFSET		= 0x14,
	VSC_SATA_TF_DEVICE_OFFSET	= 0x18,
	VSC_SATA_TF_STATUS_OFFSET	= 0x1c,
	VSC_SATA_TF_COMMAND_OFFSET	= 0x1d,
	VSC_SATA_TF_ALTSTATUS_OFFSET	= 0x28,
	VSC_SATA_TF_CTL_OFFSET		= 0x29,

	/* DMA base */
	VSC_SATA_UP_DESCRIPTOR_OFFSET	= 0x64,
	VSC_SATA_UP_DATA_BUFFER_OFFSET	= 0x6C,
	VSC_SATA_DMA_CMD_OFFSET		= 0x70,

	/* SCRs base */
	VSC_SATA_SCR_STATUS_OFFSET	= 0x100,
	VSC_SATA_SCR_ERROR_OFFSET	= 0x104,
	VSC_SATA_SCR_CONTROL_OFFSET	= 0x108,

	/* Port stride */
	VSC_SATA_PORT_OFFSET		= 0x200,

	/* Error interrupt status bit offsets */
	VSC_SATA_INT_ERROR_CRC		= 0x40,
	VSC_SATA_INT_ERROR_T		= 0x20,
	VSC_SATA_INT_ERROR_P		= 0x10,
	VSC_SATA_INT_ERROR_R		= 0x8,
	VSC_SATA_INT_ERROR_E		= 0x4,
	VSC_SATA_INT_ERROR_M		= 0x2,
	VSC_SATA_INT_PHY_CHANGE		= 0x1,
	VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC  | VSC_SATA_INT_ERROR_T | \
			      VSC_SATA_INT_ERROR_P    | VSC_SATA_INT_ERROR_R | \
			      VSC_SATA_INT_ERROR_E    | VSC_SATA_INT_ERROR_M | \
			      VSC_SATA_INT_PHY_CHANGE),
};

static int vsc_sata_scr_read(struct ata_link *link,
			     unsigned int sc_reg, u32 *val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	*val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
	return 0;
}


static int vsc_sata_scr_write(struct ata_link *link,
			      unsigned int sc_reg, u32 val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
	return 0;
}


static void vsc_freeze(struct ata_port *ap)
{
	void __iomem *mask_addr;

	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
		VSC_SATA_INT_MASK_OFFSET + ap->port_no;

	writeb(0, mask_addr);
}


static void vsc_thaw(struct ata_port *ap)
{
	void __iomem *mask_addr;

	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
		VSC_SATA_INT_MASK_OFFSET + ap->port_no;

	writeb(0xff, mask_addr);
}


static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
{
	void __iomem *mask_addr;
	u8 mask;

	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
		VSC_SATA_INT_MASK_OFFSET + ap->port_no;
	mask = readb(mask_addr);
	if (ctl & ATA_NIEN)
		mask |= 0x80;
	else
		mask &= 0x7F;
	writeb(mask, mask_addr);
}


static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;

	/*
	 * The only thing the ctl register is used for is SRST.
	 * That is not enabled or disabled via tf_load.
	 * However, if ATA_NIEN is changed, then we need to change
	 * the interrupt register.
	 */
	if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
		ap->last_ctl = tf->ctl;
		vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
	}
	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
		writew(tf->feature | (((u16)tf->hob_feature) << 8),
		       ioaddr->feature_addr);
		writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
		       ioaddr->nsect_addr);
		writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
		       ioaddr->lbal_addr);
		writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
		       ioaddr->lbam_addr);
		writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
		       ioaddr->lbah_addr);
	} else if (is_addr) {
		writew(tf->feature, ioaddr->feature_addr);
		writew(tf->nsect, ioaddr->nsect_addr);
		writew(tf->lbal, ioaddr->lbal_addr);
		writew(tf->lbam, ioaddr->lbam_addr);
		writew(tf->lbah, ioaddr->lbah_addr);
	}

	if (tf->flags & ATA_TFLAG_DEVICE)
		writeb(tf->device, ioaddr->device_addr);

	ata_wait_idle(ap);
}


static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	u16 nsect, lbal, lbam, lbah, feature;

	tf->command = ata_sff_check_status(ap);
	tf->device = readw(ioaddr->device_addr);
	feature = readw(ioaddr->error_addr);
	nsect = readw(ioaddr->nsect_addr);
	lbal = readw(ioaddr->lbal_addr);
	lbam = readw(ioaddr->lbam_addr);
	lbah = readw(ioaddr->lbah_addr);

	tf->feature = feature;
	tf->nsect = nsect;
	tf->lbal = lbal;
	tf->lbam = lbam;
	tf->lbah = lbah;

	if (tf->flags & ATA_TFLAG_LBA48) {
		tf->hob_feature = feature >> 8;
		tf->hob_nsect = nsect >> 8;
		tf->hob_lbal = lbal >> 8;
		tf->hob_lbam = lbam >> 8;
		tf->hob_lbah = lbah >> 8;
	}
}

static inline void vsc_error_intr(u8 port_status, struct ata_port *ap)
{
	if (port_status & (VSC_SATA_INT_PHY_CHANGE | VSC_SATA_INT_ERROR_M))
		ata_port_freeze(ap);
	else
		ata_port_abort(ap);
}

static void vsc_port_intr(u8 port_status, struct ata_port *ap)
{
	struct ata_queued_cmd *qc;
	int handled = 0;

	if (unlikely(port_status & VSC_SATA_INT_ERROR)) {
		vsc_error_intr(port_status, ap);
		return;
	}

	qc = ata_qc_from_tag(ap, ap->link.active_tag);
	if (qc && likely(!(qc->tf.flags & ATA_TFLAG_POLLING)))
		handled = ata_bmdma_port_intr(ap, qc);

	/* We received an interrupt during a polled command,
	 * or some other spurious condition.  Interrupt reporting
	 * with this hardware is fairly reliable so it is safe to
	 * simply clear the interrupt
	 */
	if (unlikely(!handled))
		ap->ops->sff_check_status(ap);
}

/*
 * vsc_sata_interrupt
 *
 * Read the interrupt register and process for the devices that have
 * them pending.
 */
static irqreturn_t vsc_sata_interrupt(int irq, void *dev_instance)
{
	struct ata_host *host = dev_instance;
	unsigned int i;
	unsigned int handled = 0;
	u32 status;

	status = readl(host->iomap[VSC_MMIO_BAR] + VSC_SATA_INT_STAT_OFFSET);

	if (unlikely(status == 0xffffffff || status == 0)) {
		if (status)
			dev_err(host->dev,
				": IRQ status == 0xffffffff, PCI fault or device removal?\n");
		goto out;
	}

	spin_lock(&host->lock);

	for (i = 0; i < host->n_ports; i++) {
		u8 port_status = (status >> (8 * i)) & 0xff;
		if (port_status) {
			vsc_port_intr(port_status, host->ports[i]);
			handled++;
		}
	}

	spin_unlock(&host->lock);
out:
	return IRQ_RETVAL(handled);
}


static struct scsi_host_template vsc_sata_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};


static struct ata_port_operations vsc_sata_ops = {
	.inherits		= &ata_bmdma_port_ops,
	/* The IRQ handling is not quite standard SFF behaviour so we
	   cannot use the default lost interrupt handler */
	.lost_interrupt		= ATA_OP_NULL,
	.sff_tf_load		= vsc_sata_tf_load,
	.sff_tf_read		= vsc_sata_tf_read,
	.freeze			= vsc_freeze,
	.thaw			= vsc_thaw,
	.scr_read		= vsc_sata_scr_read,
	.scr_write		= vsc_sata_scr_write,
};

static void vsc_sata_setup_port(struct ata_ioports *port, void __iomem *base)
{
	port->cmd_addr		= base + VSC_SATA_TF_CMD_OFFSET;
	port->data_addr		= base + VSC_SATA_TF_DATA_OFFSET;
	port->error_addr	= base + VSC_SATA_TF_ERROR_OFFSET;
	port->feature_addr	= base + VSC_SATA_TF_FEATURE_OFFSET;
	port->nsect_addr	= base + VSC_SATA_TF_NSECT_OFFSET;
	port->lbal_addr		= base + VSC_SATA_TF_LBAL_OFFSET;
	port->lbam_addr		= base + VSC_SATA_TF_LBAM_OFFSET;
	port->lbah_addr		= base + VSC_SATA_TF_LBAH_OFFSET;
	port->device_addr	= base + VSC_SATA_TF_DEVICE_OFFSET;
	port->status_addr	= base + VSC_SATA_TF_STATUS_OFFSET;
	port->command_addr	= base + VSC_SATA_TF_COMMAND_OFFSET;
	port->altstatus_addr	= base + VSC_SATA_TF_ALTSTATUS_OFFSET;
	port->ctl_addr		= base + VSC_SATA_TF_CTL_OFFSET;
	port->bmdma_addr	= base + VSC_SATA_DMA_CMD_OFFSET;
	port->scr_addr		= base + VSC_SATA_SCR_STATUS_OFFSET;
	writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
	writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
}


static int vsc_sata_init_one(struct pci_dev *pdev,
			     const struct pci_device_id *ent)
{
	static const struct ata_port_info pi = {
		.flags		= ATA_FLAG_SATA,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &vsc_sata_ops,
	};
	const struct ata_port_info *ppi[] = { &pi, NULL };
	struct ata_host *host;
	void __iomem *mmio_base;
	int i, rc;
	u8 cls;

	ata_print_version_once(&pdev->dev, DRV_VERSION);

	/* allocate host */
	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
	if (!host)
		return -ENOMEM;

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/* check if we have needed resource mapped */
	if (pci_resource_len(pdev, 0) == 0)
		return -ENODEV;

	/* map IO regions and initialize host accordingly */
	rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME);
	if (rc == -EBUSY)
		pcim_pin_device(pdev);
	if (rc)
		return rc;
	host->iomap = pcim_iomap_table(pdev);

	mmio_base = host->iomap[VSC_MMIO_BAR];

	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];
		unsigned int offset = (i + 1) * VSC_SATA_PORT_OFFSET;

		vsc_sata_setup_port(&ap->ioaddr, mmio_base + offset);

		ata_port_pbar_desc(ap, VSC_MMIO_BAR, -1, "mmio");
		ata_port_pbar_desc(ap, VSC_MMIO_BAR, offset, "port");
	}

	/*
	 * Use 32 bit DMA mask, because 64 bit address support is poor.
	 */
	rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
	if (rc)
		return rc;
	rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
	if (rc)
		return rc;

	/*
	 * Due to a bug in the chip, the default cache line size can't be
	 * used (unless the default is non-zero).
	 */
	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls);
	if (cls == 0x00)
		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);

	if (pci_enable_msi(pdev) == 0)
		pci_intx(pdev, 0);

	/*
	 * Config offset 0x98 is "Extended Control and Status Register 0"
	 * Default value is (1 << 28).  All bits except bit 28 are reserved in
	 * DPA mode.  If bit 28 is set, LED 0 reflects all ports' activity.
	 * If bit 28 is clear, each port has its own LED.
	 */
	pci_write_config_dword(pdev, 0x98, 0);

	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, vsc_sata_interrupt,
				 IRQF_SHARED, &vsc_sata_sht);
}

static const struct pci_device_id vsc_sata_pci_tbl[] = {
	{ PCI_VENDOR_ID_VITESSE, 0x7174,
	  PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
	{ PCI_VENDOR_ID_INTEL, 0x3200,
	  PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },

	{ }	/* terminate list */
};

static struct pci_driver vsc_sata_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= vsc_sata_pci_tbl,
	.probe			= vsc_sata_init_one,
	.remove			= ata_pci_remove_one,
};

module_pci_driver(vsc_sata_pci_driver);

MODULE_AUTHOR("Jeremy Higdon");
MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
	3	*
	4	* Maintained by: Jeremy Higdon @ SGI
	5	* Please ALWAYS copy linux-ide@vger.kernel.org
	6	* on emails.
	7	*
	8	* Copyright 2004 SGI
	9	*
	10	* Bits from Jeff Garzik, Copyright RedHat, Inc.
	11	*
af36d7f0 JG	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License as published by
	15	* the Free Software Foundation; either version 2, or (at your option)
	16	* any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; see the file COPYING. If not, write to
	25	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	26	*
	27	*
	28	* libata documentation is available via 'make {ps\|pdf}docs',
	29	* as Documentation/DocBook/libata.*
	30	*
	31	* Vitesse hardware documentation presumably available under NDA.
	32	* Intel 31244 (same hardware interface) documentation presumably
	33	* available from http://developer.intel.com/
	34	*
1da177e4 LT	35	*/
	36
	37	#include <linux/kernel.h>
	38	#include <linux/module.h>
	39	#include <linux/pci.h>
	40	#include <linux/init.h>
	41	#include <linux/blkdev.h>
	42	#include <linux/delay.h>
	43	#include <linux/interrupt.h>
7003c05d	44	#include <linux/dma-mapping.h>
a9524a76	45	#include <linux/device.h>
1da177e4 LT	46	#include <scsi/scsi_host.h>
	47	#include <linux/libata.h>
	48
	49	#define DRV_NAME "sata_vsc"
2a3103ce	50	#define DRV_VERSION "2.3"
1da177e4	51
55cca65e	52	enum {
0d5ff566 TH	53	VSC_MMIO_BAR = 0,
0d5ff566 TH	54
55cca65e JG	55	/* Interrupt register offsets (from chip base address) */
	56	VSC_SATA_INT_STAT_OFFSET = 0x00,
	57	VSC_SATA_INT_MASK_OFFSET = 0x04,
1da177e4	58
55cca65e JG	59	/* Taskfile registers offsets */
	60	VSC_SATA_TF_CMD_OFFSET = 0x00,
	61	VSC_SATA_TF_DATA_OFFSET = 0x00,
	62	VSC_SATA_TF_ERROR_OFFSET = 0x04,
	63	VSC_SATA_TF_FEATURE_OFFSET = 0x06,
	64	VSC_SATA_TF_NSECT_OFFSET = 0x08,
	65	VSC_SATA_TF_LBAL_OFFSET = 0x0c,
	66	VSC_SATA_TF_LBAM_OFFSET = 0x10,
	67	VSC_SATA_TF_LBAH_OFFSET = 0x14,
	68	VSC_SATA_TF_DEVICE_OFFSET = 0x18,
	69	VSC_SATA_TF_STATUS_OFFSET = 0x1c,
	70	VSC_SATA_TF_COMMAND_OFFSET = 0x1d,
	71	VSC_SATA_TF_ALTSTATUS_OFFSET = 0x28,
	72	VSC_SATA_TF_CTL_OFFSET = 0x29,
1da177e4	73
55cca65e JG	74	/* DMA base */
	75	VSC_SATA_UP_DESCRIPTOR_OFFSET = 0x64,
	76	VSC_SATA_UP_DATA_BUFFER_OFFSET = 0x6C,
	77	VSC_SATA_DMA_CMD_OFFSET = 0x70,
1da177e4	78
55cca65e JG	79	/* SCRs base */
	80	VSC_SATA_SCR_STATUS_OFFSET = 0x100,
	81	VSC_SATA_SCR_ERROR_OFFSET = 0x104,
	82	VSC_SATA_SCR_CONTROL_OFFSET = 0x108,
1da177e4	83
55cca65e JG	84	/* Port stride */
	85	VSC_SATA_PORT_OFFSET = 0x200,
	86
	87	/* Error interrupt status bit offsets */
	88	VSC_SATA_INT_ERROR_CRC = 0x40,
	89	VSC_SATA_INT_ERROR_T = 0x20,
	90	VSC_SATA_INT_ERROR_P = 0x10,
	91	VSC_SATA_INT_ERROR_R = 0x8,
	92	VSC_SATA_INT_ERROR_E = 0x4,
	93	VSC_SATA_INT_ERROR_M = 0x2,
	94	VSC_SATA_INT_PHY_CHANGE = 0x1,
	95	VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC \| VSC_SATA_INT_ERROR_T \| \
	96	VSC_SATA_INT_ERROR_P \| VSC_SATA_INT_ERROR_R \| \
	97	VSC_SATA_INT_ERROR_E \| VSC_SATA_INT_ERROR_M \| \
	98	VSC_SATA_INT_PHY_CHANGE),
7cbaa86b	99	};
c962990a	100
82ef04fb TH	101	static int vsc_sata_scr_read(struct ata_link *link,
82ef04fb TH	102	unsigned int sc_reg, u32 *val)
1da177e4 LT	103	{
1da177e4 LT	104	if (sc_reg > SCR_CONTROL)
da3dbb17	105	return -EINVAL;
82ef04fb	106	val = readl(link->ap->ioaddr.scr_addr + (sc_reg 4));
da3dbb17	107	return 0;
1da177e4 LT	108	}
	109
	110
82ef04fb TH	111	static int vsc_sata_scr_write(struct ata_link *link,
82ef04fb TH	112	unsigned int sc_reg, u32 val)
1da177e4 LT	113	{
1da177e4 LT	114	if (sc_reg > SCR_CONTROL)
da3dbb17	115	return -EINVAL;
82ef04fb	116	writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
da3dbb17	117	return 0;
1da177e4 LT	118	}
	119
	120
ea34e45a DW	121	static void vsc_freeze(struct ata_port *ap)
	122	{
	123	void __iomem *mask_addr;
	124
	125	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
	126	VSC_SATA_INT_MASK_OFFSET + ap->port_no;
	127
	128	writeb(0, mask_addr);
	129	}
	130
	131
	132	static void vsc_thaw(struct ata_port *ap)
	133	{
	134	void __iomem *mask_addr;
	135
	136	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
	137	VSC_SATA_INT_MASK_OFFSET + ap->port_no;
	138
	139	writeb(0xff, mask_addr);
	140	}
	141
	142
1da177e4 LT	143	static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
1da177e4 LT	144	{
307e4dc2	145	void __iomem *mask_addr;
1da177e4 LT	146	u8 mask;
1da177e4 LT	147
0d5ff566	148	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
1da177e4 LT	149	VSC_SATA_INT_MASK_OFFSET + ap->port_no;
	150	mask = readb(mask_addr);
	151	if (ctl & ATA_NIEN)
	152	mask \|= 0x80;
	153	else
	154	mask &= 0x7F;
	155	writeb(mask, mask_addr);
	156	}
	157
	158
057ace5e	159	static void vsc_sata_tf_load(struct ata_port ap, const struct ata_taskfile tf)
1da177e4 LT	160	{
	161	struct ata_ioports *ioaddr = &ap->ioaddr;
	162	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
	163
	164	/*
	165	* The only thing the ctl register is used for is SRST.
	166	* That is not enabled or disabled via tf_load.
5796d1c4 JG	167	* However, if ATA_NIEN is changed, then we need to change
5796d1c4 JG	168	* the interrupt register.
1da177e4 LT	169	*/
	170	if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
	171	ap->last_ctl = tf->ctl;
	172	vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
	173	}
	174	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
850a9d8a	175	writew(tf->feature \| (((u16)tf->hob_feature) << 8),
0d5ff566	176	ioaddr->feature_addr);
850a9d8a	177	writew(tf->nsect \| (((u16)tf->hob_nsect) << 8),
0d5ff566	178	ioaddr->nsect_addr);
850a9d8a	179	writew(tf->lbal \| (((u16)tf->hob_lbal) << 8),
0d5ff566	180	ioaddr->lbal_addr);
850a9d8a	181	writew(tf->lbam \| (((u16)tf->hob_lbam) << 8),
0d5ff566	182	ioaddr->lbam_addr);
850a9d8a	183	writew(tf->lbah \| (((u16)tf->hob_lbah) << 8),
0d5ff566	184	ioaddr->lbah_addr);
1da177e4	185	} else if (is_addr) {
0d5ff566 TH	186	writew(tf->feature, ioaddr->feature_addr);
	187	writew(tf->nsect, ioaddr->nsect_addr);
	188	writew(tf->lbal, ioaddr->lbal_addr);
	189	writew(tf->lbam, ioaddr->lbam_addr);
	190	writew(tf->lbah, ioaddr->lbah_addr);
1da177e4 LT	191	}
	192
	193	if (tf->flags & ATA_TFLAG_DEVICE)
0d5ff566	194	writeb(tf->device, ioaddr->device_addr);
1da177e4 LT	195
	196	ata_wait_idle(ap);
	197	}
	198
	199
	200	static void vsc_sata_tf_read(struct ata_port ap, struct ata_taskfile tf)
	201	{
	202	struct ata_ioports *ioaddr = &ap->ioaddr;
ac19bff2	203	u16 nsect, lbal, lbam, lbah, feature;
1da177e4	204
9363c382	205	tf->command = ata_sff_check_status(ap);
0d5ff566 TH	206	tf->device = readw(ioaddr->device_addr);
	207	feature = readw(ioaddr->error_addr);
	208	nsect = readw(ioaddr->nsect_addr);
	209	lbal = readw(ioaddr->lbal_addr);
	210	lbam = readw(ioaddr->lbam_addr);
	211	lbah = readw(ioaddr->lbah_addr);
ac19bff2 JG	212
	213	tf->feature = feature;
	214	tf->nsect = nsect;
	215	tf->lbal = lbal;
	216	tf->lbam = lbam;
	217	tf->lbah = lbah;
1da177e4 LT	218
1da177e4 LT	219	if (tf->flags & ATA_TFLAG_LBA48) {
ac19bff2	220	tf->hob_feature = feature >> 8;
1da177e4 LT	221	tf->hob_nsect = nsect >> 8;
	222	tf->hob_lbal = lbal >> 8;
	223	tf->hob_lbam = lbam >> 8;
	224	tf->hob_lbah = lbah >> 8;
5796d1c4	225	}
1da177e4 LT	226	}
1da177e4 LT	227
ea34e45a DW	228	static inline void vsc_error_intr(u8 port_status, struct ata_port *ap)
	229	{
	230	if (port_status & (VSC_SATA_INT_PHY_CHANGE \| VSC_SATA_INT_ERROR_M))
	231	ata_port_freeze(ap);
	232	else
	233	ata_port_abort(ap);
	234	}
	235
	236	static void vsc_port_intr(u8 port_status, struct ata_port *ap)
	237	{
	238	struct ata_queued_cmd *qc;
	239	int handled = 0;
	240
	241	if (unlikely(port_status & VSC_SATA_INT_ERROR)) {
	242	vsc_error_intr(port_status, ap);
	243	return;
	244	}
	245
9af5c9c9	246	qc = ata_qc_from_tag(ap, ap->link.active_tag);
ea34e45a	247	if (qc && likely(!(qc->tf.flags & ATA_TFLAG_POLLING)))
c3b28894	248	handled = ata_bmdma_port_intr(ap, qc);
ea34e45a DW	249
	250	/* We received an interrupt during a polled command,
	251	* or some other spurious condition. Interrupt reporting
	252	* with this hardware is fairly reliable so it is safe to
	253	* simply clear the interrupt
	254	*/
	255	if (unlikely(!handled))
5682ed33	256	ap->ops->sff_check_status(ap);
ea34e45a	257	}
1da177e4 LT	258
	259	/*
	260	* vsc_sata_interrupt
	261	*
5796d1c4 JG	262	* Read the interrupt register and process for the devices that have
5796d1c4 JG	263	* them pending.
1da177e4	264	*/
5796d1c4	265	static irqreturn_t vsc_sata_interrupt(int irq, void *dev_instance)
1da177e4	266	{
cca3974e	267	struct ata_host *host = dev_instance;
1da177e4 LT	268	unsigned int i;
1da177e4 LT	269	unsigned int handled = 0;
ea34e45a	270	u32 status;
1da177e4	271
ea34e45a	272	status = readl(host->iomap[VSC_MMIO_BAR] + VSC_SATA_INT_STAT_OFFSET);
1da177e4	273
ea34e45a DW	274	if (unlikely(status == 0xffffffff \|\| status == 0)) {
ea34e45a DW	275	if (status)
a44fec1f JP	276	dev_err(host->dev,
a44fec1f JP	277	": IRQ status == 0xffffffff, PCI fault or device removal?\n");
ea34e45a DW	278	goto out;
ea34e45a DW	279	}
1da177e4	280
ea34e45a	281	spin_lock(&host->lock);
2ae5b30f	282
ea34e45a DW	283	for (i = 0; i < host->n_ports; i++) {
	284	u8 port_status = (status >> (8 * i)) & 0xff;
	285	if (port_status) {
3e4ec344 TH	286	vsc_port_intr(port_status, host->ports[i]);
3e4ec344 TH	287	handled++;
1da177e4 LT	288	}
	289	}
	290
cca3974e	291	spin_unlock(&host->lock);
ea34e45a	292	out:
1da177e4 LT	293	return IRQ_RETVAL(handled);
	294	}
	295
	296
193515d5	297	static struct scsi_host_template vsc_sata_sht = {
68d1d07b	298	ATA_BMDMA_SHT(DRV_NAME),
1da177e4 LT	299	};
	300
	301
029cfd6b TH	302	static struct ata_port_operations vsc_sata_ops = {
029cfd6b TH	303	.inherits = &ata_bmdma_port_ops,
c96f1732 AC	304	/* The IRQ handling is not quite standard SFF behaviour so we
	305	cannot use the default lost interrupt handler */
	306	.lost_interrupt = ATA_OP_NULL,
5682ed33 TH	307	.sff_tf_load = vsc_sata_tf_load,
5682ed33 TH	308	.sff_tf_read = vsc_sata_tf_read,
ea34e45a DW	309	.freeze = vsc_freeze,
ea34e45a DW	310	.thaw = vsc_thaw,
1da177e4 LT	311	.scr_read = vsc_sata_scr_read,
1da177e4 LT	312	.scr_write = vsc_sata_scr_write,
1da177e4 LT	313	};
1da177e4 LT	314
0ec24914	315	static void vsc_sata_setup_port(struct ata_ioports port, void __iomem base)
1da177e4 LT	316	{
	317	port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET;
	318	port->data_addr = base + VSC_SATA_TF_DATA_OFFSET;
	319	port->error_addr = base + VSC_SATA_TF_ERROR_OFFSET;
	320	port->feature_addr = base + VSC_SATA_TF_FEATURE_OFFSET;
	321	port->nsect_addr = base + VSC_SATA_TF_NSECT_OFFSET;
	322	port->lbal_addr = base + VSC_SATA_TF_LBAL_OFFSET;
	323	port->lbam_addr = base + VSC_SATA_TF_LBAM_OFFSET;
	324	port->lbah_addr = base + VSC_SATA_TF_LBAH_OFFSET;
	325	port->device_addr = base + VSC_SATA_TF_DEVICE_OFFSET;
	326	port->status_addr = base + VSC_SATA_TF_STATUS_OFFSET;
	327	port->command_addr = base + VSC_SATA_TF_COMMAND_OFFSET;
	328	port->altstatus_addr = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
	329	port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET;
	330	port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET;
	331	port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET;
0d5ff566 TH	332	writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
0d5ff566 TH	333	writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
1da177e4 LT	334	}
	335
	336
0ec24914 GKH	337	static int vsc_sata_init_one(struct pci_dev *pdev,
0ec24914 GKH	338	const struct pci_device_id *ent)
1da177e4	339	{
4447d351	340	static const struct ata_port_info pi = {
9cbe056f	341	.flags = ATA_FLAG_SATA,
14bdef98 EIB	342	.pio_mask = ATA_PIO4,
14bdef98 EIB	343	.mwdma_mask = ATA_MWDMA2,
bf6263a8	344	.udma_mask = ATA_UDMA6,
4447d351 TH	345	.port_ops = &vsc_sata_ops,
	346	};
	347	const struct ata_port_info *ppi[] = { &pi, NULL };
4447d351	348	struct ata_host *host;
307e4dc2	349	void __iomem *mmio_base;
4447d351	350	int i, rc;
7de970e1	351	u8 cls;
1da177e4	352
06296a1e	353	ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4	354
4447d351 TH	355	/* allocate host */
	356	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
	357	if (!host)
	358	return -ENOMEM;
	359
24dc5f33	360	rc = pcim_enable_device(pdev);
1da177e4 LT	361	if (rc)
	362	return rc;
	363
4447d351	364	/* check if we have needed resource mapped */
24dc5f33 TH	365	if (pci_resource_len(pdev, 0) == 0)
24dc5f33 TH	366	return -ENODEV;
1da177e4	367
b595076a	368	/* map IO regions and initialize host accordingly */
0d5ff566 TH	369	rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME);
0d5ff566 TH	370	if (rc == -EBUSY)
24dc5f33	371	pcim_pin_device(pdev);
0d5ff566	372	if (rc)
24dc5f33	373	return rc;
4447d351 TH	374	host->iomap = pcim_iomap_table(pdev);
	375
	376	mmio_base = host->iomap[VSC_MMIO_BAR];
	377
cbcdd875 TH	378	for (i = 0; i < host->n_ports; i++) {
	379	struct ata_port *ap = host->ports[i];
	380	unsigned int offset = (i + 1) * VSC_SATA_PORT_OFFSET;
	381
	382	vsc_sata_setup_port(&ap->ioaddr, mmio_base + offset);
	383
	384	ata_port_pbar_desc(ap, VSC_MMIO_BAR, -1, "mmio");
	385	ata_port_pbar_desc(ap, VSC_MMIO_BAR, offset, "port");
	386	}
1da177e4 LT	387
	388	/*
	389	* Use 32 bit DMA mask, because 64 bit address support is poor.
	390	*/
284901a9	391	rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4	392	if (rc)
24dc5f33	393	return rc;
284901a9	394	rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4	395	if (rc)
24dc5f33	396	return rc;
7cbaa86b	397
1da177e4	398	/*
7de970e1 ND	399	* Due to a bug in the chip, the default cache line size can't be
7de970e1 ND	400	* used (unless the default is non-zero).
1da177e4	401	*/
7de970e1 ND	402	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls);
	403	if (cls == 0x00)
	404	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
1da177e4	405
24dc5f33	406	if (pci_enable_msi(pdev) == 0)
7cbaa86b	407	pci_intx(pdev, 0);
1da177e4	408
8a60a071	409	/*
1da177e4 LT	410	* Config offset 0x98 is "Extended Control and Status Register 0"
	411	* Default value is (1 << 28). All bits except bit 28 are reserved in
	412	* DPA mode. If bit 28 is set, LED 0 reflects all ports' activity.
	413	* If bit 28 is clear, each port has its own LED.
	414	*/
	415	pci_write_config_dword(pdev, 0x98, 0);
	416
4447d351 TH	417	pci_set_master(pdev);
	418	return ata_host_activate(host, pdev->irq, vsc_sata_interrupt,
	419	IRQF_SHARED, &vsc_sata_sht);
1da177e4 LT	420	}
1da177e4 LT	421
3b7d697d	422	static const struct pci_device_id vsc_sata_pci_tbl[] = {
438bc9c3	423	{ PCI_VENDOR_ID_VITESSE, 0x7174,
74d0a988	424	PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
438bc9c3	425	{ PCI_VENDOR_ID_INTEL, 0x3200,
74d0a988	426	PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
2d2744fc	427
438bc9c3	428	{ } /* terminate list */
1da177e4 LT	429	};
1da177e4 LT	430
1da177e4 LT	431	static struct pci_driver vsc_sata_pci_driver = {
	432	.name = DRV_NAME,
	433	.id_table = vsc_sata_pci_tbl,
	434	.probe = vsc_sata_init_one,
	435	.remove = ata_pci_remove_one,
	436	};
	437
2fc75da0	438	module_pci_driver(vsc_sata_pci_driver);
1da177e4	439
1da177e4 LT	440	MODULE_AUTHOR("Jeremy Higdon");
	441	MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
	442	MODULE_LICENSE("GPL");
	443	MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
	444	MODULE_VERSION(DRV_VERSION);