[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / pata_serverworks.c

/*
 * pata_serverworks.c 	- Serverworks PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  (C) 2010 Bartlomiej Zolnierkiewicz
 *
 * based upon
 *
 * serverworks.c
 *
 * Copyright (C) 1998-2000 Michel Aubry
 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
 * Portions copyright (c) 2001 Sun Microsystems
 *
 *
 * RCC/ServerWorks IDE driver for Linux
 *
 *   OSB4: `Open South Bridge' IDE Interface (fn 1)
 *         supports UDMA mode 2 (33 MB/s)
 *
 *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
 *         all revisions support UDMA mode 4 (66 MB/s)
 *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
 *
 *         *** The CSB5 does not provide ANY register ***
 *         *** to detect 80-conductor cable presence. ***
 *
 *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
 *
 * Documentation:
 *	Available under NDA only. Errata info very hard to get.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_serverworks"
#define DRV_VERSION "0.4.3"

#define SVWKS_CSB5_REVISION_NEW	0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
#define SVWKS_CSB6_REVISION	0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */

/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
 * can overrun their FIFOs when used with the CSB5 */

static const char *csb_bad_ata100[] = {
	"ST320011A",
	"ST340016A",
	"ST360021A",
	"ST380021A",
	NULL
};

/**
 *	oem_cable	-	Dell/Sun serverworks cable detection
 *	@ap: ATA port to do cable detect
 *
 *	Dell PowerEdge and Sun Cobalt 'Alpine' hide the 40/80 pin select
 *	for their interfaces in the top two bits of the subsystem ID.
 */

static int oem_cable(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
		return ATA_CBL_PATA80;
	return ATA_CBL_PATA40;
}

struct sv_cable_table {
	int device;
	int subvendor;
	int (*cable_detect)(struct ata_port *ap);
};

static struct sv_cable_table cable_detect[] = {
	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE,   PCI_VENDOR_ID_DELL, oem_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE,   PCI_VENDOR_ID_DELL, oem_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE,   PCI_VENDOR_ID_SUN,  oem_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_OSB4IDE,   PCI_ANY_ID, ata_cable_40wire  },
	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE,   PCI_ANY_ID, ata_cable_unknown },
	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE,   PCI_ANY_ID, ata_cable_unknown },
	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2,  PCI_ANY_ID, ata_cable_unknown },
	{ PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, ata_cable_unknown },
	{ }
};

/**
 *	serverworks_cable_detect	-	cable detection
 *	@ap: ATA port
 *
 *	Perform cable detection according to the device and subvendor
 *	identifications
 */

static int serverworks_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	struct sv_cable_table *cb = cable_detect;

	while(cb->device) {
		if (cb->device == pdev->device &&
		    (cb->subvendor == pdev->subsystem_vendor ||
		      cb->subvendor == PCI_ANY_ID)) {
			return cb->cable_detect(ap);
		}
		cb++;
	}

	BUG();
	return -1;	/* kill compiler warning */
}

/**
 *	serverworks_is_csb	-	Check for CSB or OSB
 *	@pdev: PCI device to check
 *
 *	Returns true if the device being checked is known to be a CSB
 *	series device.
 */

static u8 serverworks_is_csb(struct pci_dev *pdev)
{
	switch (pdev->device) {
		case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
		case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
			return 1;
		default:
			break;
	}
	return 0;
}

/**
 *	serverworks_osb4_filter	-	mode selection filter
 *	@adev: ATA device
 *	@mask: Mask of proposed modes
 *
 *	Filter the offered modes for the device to apply controller
 *	specific rules. OSB4 requires no UDMA for disks due to a FIFO
 *	bug we hit.
 */

static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned long mask)
{
	if (adev->class == ATA_DEV_ATA)
		mask &= ~ATA_MASK_UDMA;
	return mask;
}


/**
 *	serverworks_csb_filter	-	mode selection filter
 *	@adev: ATA device
 *	@mask: Mask of proposed modes
 *
 *	Check the blacklist and disable UDMA5 if matched
 */

static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned long mask)
{
	const char *p;
	char model_num[ATA_ID_PROD_LEN + 1];
	int i;

	/* Disk, UDMA */
	if (adev->class != ATA_DEV_ATA)
		return mask;

	/* Actually do need to check */
	ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));

	for (i = 0; (p = csb_bad_ata100[i]) != NULL; i++) {
		if (!strcmp(p, model_num))
			mask &= ~(0xE0 << ATA_SHIFT_UDMA);
	}
	return mask;
}

/**
 *	serverworks_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the OSB4/CSB5 timing registers for PIO. The PIO register
 *	load is done as a simple lookup.
 */
static void serverworks_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	static const u8 pio_mode[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
	int offset = 1 + 2 * ap->port_no - adev->devno;
	int devbits = (2 * ap->port_no + adev->devno) * 4;
	u16 csb5_pio;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int pio = adev->pio_mode - XFER_PIO_0;

	pci_write_config_byte(pdev, 0x40 + offset, pio_mode[pio]);

	/* The OSB4 just requires the timing but the CSB series want the
	   mode number as well */
	if (serverworks_is_csb(pdev)) {
		pci_read_config_word(pdev, 0x4A, &csb5_pio);
		csb5_pio &= ~(0x0F << devbits);
		pci_write_config_word(pdev, 0x4A, csb5_pio | (pio << devbits));
	}
}

/**
 *	serverworks_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5
 *	chipset. The MWDMA mode values are pulled from a lookup table
 *	while the chipset uses mode number for UDMA.
 */

static void serverworks_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	static const u8 dma_mode[] = { 0x77, 0x21, 0x20 };
	int offset = 1 + 2 * ap->port_no - adev->devno;
	int devbits = 2 * ap->port_no + adev->devno;
	u8 ultra;
	u8 ultra_cfg;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	pci_read_config_byte(pdev, 0x54, &ultra_cfg);
	pci_read_config_byte(pdev, 0x56 + ap->port_no, &ultra);
	ultra &= ~(0x0F << (adev->devno * 4));

	if (adev->dma_mode >= XFER_UDMA_0) {
		pci_write_config_byte(pdev, 0x44 + offset,  0x20);

		ultra |= (adev->dma_mode - XFER_UDMA_0)
					<< (adev->devno * 4);
		ultra_cfg |=  (1 << devbits);
	} else {
		pci_write_config_byte(pdev, 0x44 + offset,
			dma_mode[adev->dma_mode - XFER_MW_DMA_0]);
		ultra_cfg &= ~(1 << devbits);
	}
	pci_write_config_byte(pdev, 0x56 + ap->port_no, ultra);
	pci_write_config_byte(pdev, 0x54, ultra_cfg);
}

static struct scsi_host_template serverworks_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations serverworks_osb4_port_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.cable_detect	= serverworks_cable_detect,
	.mode_filter	= serverworks_osb4_filter,
	.set_piomode	= serverworks_set_piomode,
	.set_dmamode	= serverworks_set_dmamode,
};

static struct ata_port_operations serverworks_csb_port_ops = {
	.inherits	= &serverworks_osb4_port_ops,
	.mode_filter	= serverworks_csb_filter,
};

static int serverworks_fixup_osb4(struct pci_dev *pdev)
{
	u32 reg;
	struct pci_dev *isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
		  PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
	if (isa_dev) {
		pci_read_config_dword(isa_dev, 0x64, &reg);
		reg &= ~0x00002000; /* disable 600ns interrupt mask */
		if (!(reg & 0x00004000))
			printk(KERN_DEBUG DRV_NAME ": UDMA not BIOS enabled.\n");
		reg |=  0x00004000; /* enable UDMA/33 support */
		pci_write_config_dword(isa_dev, 0x64, reg);
		pci_dev_put(isa_dev);
		return 0;
	}
	printk(KERN_WARNING DRV_NAME ": Unable to find bridge.\n");
	return -ENODEV;
}

static int serverworks_fixup_csb(struct pci_dev *pdev)
{
	u8 btr;

	/* Third Channel Test */
	if (!(PCI_FUNC(pdev->devfn) & 1)) {
		struct pci_dev * findev = NULL;
		u32 reg4c = 0;
		findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
			PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
		if (findev) {
			pci_read_config_dword(findev, 0x4C, &reg4c);
			reg4c &= ~0x000007FF;
			reg4c |=  0x00000040;
			reg4c |=  0x00000020;
			pci_write_config_dword(findev, 0x4C, reg4c);
			pci_dev_put(findev);
		}
	} else {
		struct pci_dev * findev = NULL;
		u8 reg41 = 0;

		findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
				PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
		if (findev) {
			pci_read_config_byte(findev, 0x41, &reg41);
			reg41 &= ~0x40;
			pci_write_config_byte(findev, 0x41, reg41);
			pci_dev_put(findev);
		}
	}
	/* setup the UDMA Control register
	 *
	 * 1. clear bit 6 to enable DMA
	 * 2. enable DMA modes with bits 0-1
	 * 	00 : legacy
	 * 	01 : udma2
	 * 	10 : udma2/udma4
	 * 	11 : udma2/udma4/udma5
	 */
	pci_read_config_byte(pdev, 0x5A, &btr);
	btr &= ~0x40;
	if (!(PCI_FUNC(pdev->devfn) & 1))
		btr |= 0x2;
	else
		btr |= (pdev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
	pci_write_config_byte(pdev, 0x5A, btr);

	return btr;
}

static void serverworks_fixup_ht1000(struct pci_dev *pdev)
{
	u8 btr;
	/* Setup HT1000 SouthBridge Controller - Single Channel Only */
	pci_read_config_byte(pdev, 0x5A, &btr);
	btr &= ~0x40;
	btr |= 0x3;
	pci_write_config_byte(pdev, 0x5A, btr);
}

static int serverworks_fixup(struct pci_dev *pdev)
{
	int rc = 0;

	/* Force master latency timer to 64 PCI clocks */
	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);

	switch (pdev->device) {
	case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE:
		rc = serverworks_fixup_osb4(pdev);
		break;
	case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
		ata_pci_bmdma_clear_simplex(pdev);
		/* fall through */
	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
		rc = serverworks_fixup_csb(pdev);
		break;
	case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
		serverworks_fixup_ht1000(pdev);
		break;
	}

	return rc;
}

static int serverworks_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const struct ata_port_info info[4] = {
		{ /* OSB4 */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA2,
			.port_ops = &serverworks_osb4_port_ops
		}, { /* OSB4 no UDMA */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			/* No UDMA */
			.port_ops = &serverworks_osb4_port_ops
		}, { /* CSB5 */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA4,
			.port_ops = &serverworks_csb_port_ops
		}, { /* CSB5 - later revisions*/
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA5,
			.port_ops = &serverworks_csb_port_ops
		}
	};
	const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
	int rc;

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	rc = serverworks_fixup(pdev);

	/* OSB4 : South Bridge and IDE */
	if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
		/* Select non UDMA capable OSB4 if we can't do fixups */
		if (rc < 0)
			ppi[0] = &info[1];
	}
	/* setup CSB5/CSB6 : South Bridge and IDE option RAID */
	else if ((pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
		 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
		 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {

		 /* If the returned btr is the newer revision then
		    select the right info block */
		 if (rc == 3)
		 	ppi[0] = &info[3];

		/* Is this the 3rd channel CSB6 IDE ? */
		if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)
			ppi[1] = &ata_dummy_port_info;
	}

	return ata_pci_bmdma_init_one(pdev, ppi, &serverworks_sht, NULL, 0);
}

#ifdef CONFIG_PM
static int serverworks_reinit_one(struct pci_dev *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	int rc;

	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;

	(void)serverworks_fixup(pdev);

	ata_host_resume(host);
	return 0;
}
#endif

static const struct pci_device_id serverworks[] = {
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0},
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 2},
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2},
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 2},
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 2},

	{ },
};

static struct pci_driver serverworks_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= serverworks,
	.probe 		= serverworks_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= serverworks_reinit_one,
#endif
};

module_pci_driver(serverworks_pci_driver);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Serverworks OSB4/CSB5/CSB6");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, serverworks);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
669a5db4	1	/*
a0fcdc02	2	* pata_serverworks.c - Serverworks PATA for new ATA layer
669a5db4	3	* (C) 2005 Red Hat Inc
8490377a	4	* (C) 2010 Bartlomiej Zolnierkiewicz
669a5db4 JG	5	*
	6	* based upon
	7	*
	8	* serverworks.c
85cd7251	9	*
669a5db4 JG	10	* Copyright (C) 1998-2000 Michel Aubry
	11	* Copyright (C) 1998-2000 Andrzej Krzysztofowicz
	12	* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
	13	* Portions copyright (c) 2001 Sun Microsystems
	14	*
	15	*
	16	* RCC/ServerWorks IDE driver for Linux
	17	*
	18	* OSB4: `Open South Bridge' IDE Interface (fn 1)
	19	* supports UDMA mode 2 (33 MB/s)
	20	*
	21	* CSB5: `Champion South Bridge' IDE Interface (fn 1)
	22	* all revisions support UDMA mode 4 (66 MB/s)
	23	* revision A2.0 and up support UDMA mode 5 (100 MB/s)
	24	*
	25	* * The CSB5 does not provide ANY register *
	26	* * to detect 80-conductor cable presence. *
	27	*
	28	* CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
	29	*
	30	* Documentation:
	31	* Available under NDA only. Errata info very hard to get.
	32	*/
	33
	34	#include <linux/kernel.h>
	35	#include <linux/module.h>
	36	#include <linux/pci.h>
	37	#include <linux/init.h>
	38	#include <linux/blkdev.h>
	39	#include <linux/delay.h>
	40	#include <scsi/scsi_host.h>
	41	#include <linux/libata.h>
	42
	43	#define DRV_NAME "pata_serverworks"
0f069788	44	#define DRV_VERSION "0.4.3"
669a5db4 JG	45
	46	#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
	47	#define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
	48
	49	/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
	50	* can overrun their FIFOs when used with the CSB5 */
	51
	52	static const char *csb_bad_ata100[] = {
	53	"ST320011A",
	54	"ST340016A",
	55	"ST360021A",
	56	"ST380021A",
	57	NULL
	58	};
	59
	60	/**
e69a70d9	61	* oem_cable - Dell/Sun serverworks cable detection
669a5db4 JG	62	* @ap: ATA port to do cable detect
669a5db4 JG	63	*
e69a70d9 BZ	64	* Dell PowerEdge and Sun Cobalt 'Alpine' hide the 40/80 pin select
e69a70d9 BZ	65	* for their interfaces in the top two bits of the subsystem ID.
669a5db4	66	*/
85cd7251	67
e69a70d9	68	static int oem_cable(struct ata_port *ap)
5860a554	69	{
669a5db4	70	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
85cd7251	71
669a5db4 JG	72	if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
	73	return ATA_CBL_PATA80;
	74	return ATA_CBL_PATA40;
	75	}
	76
669a5db4 JG	77	struct sv_cable_table {
	78	int device;
	79	int subvendor;
	80	int (cable_detect)(struct ata_port ap);
	81	};
	82
669a5db4	83	static struct sv_cable_table cable_detect[] = {
e69a70d9 BZ	84	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_DELL, oem_cable },
	85	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_VENDOR_ID_DELL, oem_cable },
	86	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_SUN, oem_cable },
5860a554 BZ	87	{ PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, ata_cable_40wire },
	88	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, ata_cable_unknown },
	89	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, ata_cable_unknown },
	90	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, ata_cable_unknown },
	91	{ PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, ata_cable_unknown },
669a5db4 JG	92	{ }
	93	};
	94
	95	/**
a0fcdc02	96	* serverworks_cable_detect - cable detection
669a5db4 JG	97	* @ap: ATA port
669a5db4 JG	98	*
85cd7251	99	* Perform cable detection according to the device and subvendor
669a5db4 JG	100	* identifications
669a5db4 JG	101	*/
85cd7251	102
d4b2bab4 TH	103	static int serverworks_cable_detect(struct ata_port *ap)
d4b2bab4 TH	104	{
669a5db4 JG	105	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	106	struct sv_cable_table *cb = cable_detect;
	107
	108	while(cb->device) {
85cd7251	109	if (cb->device == pdev->device &&
669a5db4 JG	110	(cb->subvendor == pdev->subsystem_vendor \|\|
669a5db4 JG	111	cb->subvendor == PCI_ANY_ID)) {
a0fcdc02	112	return cb->cable_detect(ap);
669a5db4 JG	113	}
	114	cb++;
	115	}
	116
	117	BUG();
	118	return -1; /* kill compiler warning */
	119	}
	120
669a5db4 JG	121	/**
	122	* serverworks_is_csb - Check for CSB or OSB
	123	* @pdev: PCI device to check
	124	*
	125	* Returns true if the device being checked is known to be a CSB
	126	* series device.
	127	*/
85cd7251	128
669a5db4 JG	129	static u8 serverworks_is_csb(struct pci_dev *pdev)
	130	{
	131	switch (pdev->device) {
	132	case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
	133	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
	134	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
	135	case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
	136	return 1;
	137	default:
	138	break;
	139	}
	140	return 0;
	141	}
	142
	143	/**
	144	* serverworks_osb4_filter - mode selection filter
669a5db4	145	* @adev: ATA device
a76b62ca	146	* @mask: Mask of proposed modes
669a5db4 JG	147	*
	148	* Filter the offered modes for the device to apply controller
	149	* specific rules. OSB4 requires no UDMA for disks due to a FIFO
	150	* bug we hit.
	151	*/
85cd7251	152
a76b62ca	153	static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned long mask)
669a5db4 JG	154	{
	155	if (adev->class == ATA_DEV_ATA)
	156	mask &= ~ATA_MASK_UDMA;
c7087652	157	return mask;
669a5db4 JG	158	}
	159
	160
	161	/**
	162	* serverworks_csb_filter - mode selection filter
669a5db4	163	* @adev: ATA device
a76b62ca	164	* @mask: Mask of proposed modes
669a5db4 JG	165	*
	166	* Check the blacklist and disable UDMA5 if matched
	167	*/
	168
a76b62ca	169	static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned long mask)
669a5db4 JG	170	{
669a5db4 JG	171	const char *p;
8bfa79fc TH	172	char model_num[ATA_ID_PROD_LEN + 1];
8bfa79fc TH	173	int i;
669a5db4	174
85cd7251	175	/* Disk, UDMA */
669a5db4	176	if (adev->class != ATA_DEV_ATA)
c7087652	177	return mask;
669a5db4 JG	178
669a5db4 JG	179	/* Actually do need to check */
8bfa79fc	180	ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));
85cd7251	181
8bfa79fc TH	182	for (i = 0; (p = csb_bad_ata100[i]) != NULL; i++) {
8bfa79fc TH	183	if (!strcmp(p, model_num))
6ddd6861	184	mask &= ~(0xE0 << ATA_SHIFT_UDMA);
669a5db4	185	}
c7087652	186	return mask;
669a5db4 JG	187	}
669a5db4 JG	188
669a5db4 JG	189	/**
	190	* serverworks_set_piomode - set initial PIO mode data
	191	* @ap: ATA interface
	192	* @adev: ATA device
	193	*
	194	* Program the OSB4/CSB5 timing registers for PIO. The PIO register
	195	* load is done as a simple lookup.
	196	*/
	197	static void serverworks_set_piomode(struct ata_port ap, struct ata_device adev)
	198	{
	199	static const u8 pio_mode[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
0f069788	200	int offset = 1 + 2 * ap->port_no - adev->devno;
669a5db4 JG	201	int devbits = (2 * ap->port_no + adev->devno) * 4;
	202	u16 csb5_pio;
	203	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	204	int pio = adev->pio_mode - XFER_PIO_0;
	205
	206	pci_write_config_byte(pdev, 0x40 + offset, pio_mode[pio]);
85cd7251	207
669a5db4 JG	208	/* The OSB4 just requires the timing but the CSB series want the
	209	mode number as well */
	210	if (serverworks_is_csb(pdev)) {
	211	pci_read_config_word(pdev, 0x4A, &csb5_pio);
	212	csb5_pio &= ~(0x0F << devbits);
8490377a	213	pci_write_config_word(pdev, 0x4A, csb5_pio \| (pio << devbits));
669a5db4 JG	214	}
	215	}
	216
	217	/**
	218	* serverworks_set_dmamode - set initial DMA mode data
	219	* @ap: ATA interface
	220	* @adev: ATA device
	221	*
	222	* Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5
	223	* chipset. The MWDMA mode values are pulled from a lookup table
	224	* while the chipset uses mode number for UDMA.
	225	*/
	226
	227	static void serverworks_set_dmamode(struct ata_port ap, struct ata_device adev)
	228	{
	229	static const u8 dma_mode[] = { 0x77, 0x21, 0x20 };
	230	int offset = 1 + 2 * ap->port_no - adev->devno;
36beb823	231	int devbits = 2 * ap->port_no + adev->devno;
669a5db4 JG	232	u8 ultra;
	233	u8 ultra_cfg;
	234	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	235
	236	pci_read_config_byte(pdev, 0x54, &ultra_cfg);
36beb823 AC	237	pci_read_config_byte(pdev, 0x56 + ap->port_no, &ultra);
36beb823 AC	238	ultra &= ~(0x0F << (adev->devno * 4));
669a5db4 JG	239
	240	if (adev->dma_mode >= XFER_UDMA_0) {
	241	pci_write_config_byte(pdev, 0x44 + offset, 0x20);
	242
669a5db4	243	ultra \|= (adev->dma_mode - XFER_UDMA_0)
36beb823	244	<< (adev->devno * 4);
669a5db4 JG	245	ultra_cfg \|= (1 << devbits);
669a5db4 JG	246	} else {
85cd7251	247	pci_write_config_byte(pdev, 0x44 + offset,
669a5db4 JG	248	dma_mode[adev->dma_mode - XFER_MW_DMA_0]);
	249	ultra_cfg &= ~(1 << devbits);
	250	}
36beb823	251	pci_write_config_byte(pdev, 0x56 + ap->port_no, ultra);
669a5db4 JG	252	pci_write_config_byte(pdev, 0x54, ultra_cfg);
	253	}
	254
	255	static struct scsi_host_template serverworks_sht = {
68d1d07b	256	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	257	};
	258
	259	static struct ata_port_operations serverworks_osb4_port_ops = {
029cfd6b TH	260	.inherits = &ata_bmdma_port_ops,
	261	.cable_detect = serverworks_cable_detect,
	262	.mode_filter = serverworks_osb4_filter,
669a5db4 JG	263	.set_piomode = serverworks_set_piomode,
669a5db4 JG	264	.set_dmamode = serverworks_set_dmamode,
85cd7251	265	};
669a5db4 JG	266
669a5db4 JG	267	static struct ata_port_operations serverworks_csb_port_ops = {
029cfd6b	268	.inherits = &serverworks_osb4_port_ops,
669a5db4	269	.mode_filter = serverworks_csb_filter,
85cd7251	270	};
669a5db4 JG	271
	272	static int serverworks_fixup_osb4(struct pci_dev *pdev)
	273	{
	274	u32 reg;
	275	struct pci_dev *isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
	276	PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
	277	if (isa_dev) {
	278	pci_read_config_dword(isa_dev, 0x64, &reg);
	279	reg &= ~0x00002000; /* disable 600ns interrupt mask */
	280	if (!(reg & 0x00004000))
	281	printk(KERN_DEBUG DRV_NAME ": UDMA not BIOS enabled.\n");
	282	reg \|= 0x00004000; /* enable UDMA/33 support */
	283	pci_write_config_dword(isa_dev, 0x64, reg);
	284	pci_dev_put(isa_dev);
	285	return 0;
	286	}
cfcf9ee2	287	printk(KERN_WARNING DRV_NAME ": Unable to find bridge.\n");
669a5db4 JG	288	return -ENODEV;
	289	}
	290
	291	static int serverworks_fixup_csb(struct pci_dev *pdev)
	292	{
669a5db4	293	u8 btr;
85cd7251	294
669a5db4 JG	295	/* Third Channel Test */
	296	if (!(PCI_FUNC(pdev->devfn) & 1)) {
	297	struct pci_dev * findev = NULL;
	298	u32 reg4c = 0;
	299	findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
	300	PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
	301	if (findev) {
	302	pci_read_config_dword(findev, 0x4C, &reg4c);
	303	reg4c &= ~0x000007FF;
	304	reg4c \|= 0x00000040;
	305	reg4c \|= 0x00000020;
	306	pci_write_config_dword(findev, 0x4C, reg4c);
	307	pci_dev_put(findev);
	308	}
	309	} else {
	310	struct pci_dev * findev = NULL;
	311	u8 reg41 = 0;
	312
	313	findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
	314	PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
	315	if (findev) {
	316	pci_read_config_byte(findev, 0x41, &reg41);
	317	reg41 &= ~0x40;
	318	pci_write_config_byte(findev, 0x41, reg41);
	319	pci_dev_put(findev);
	320	}
	321	}
	322	/* setup the UDMA Control register
	323	*
	324	* 1. clear bit 6 to enable DMA
	325	* 2. enable DMA modes with bits 0-1
	326	* 00 : legacy
	327	* 01 : udma2
	328	* 10 : udma2/udma4
	329	* 11 : udma2/udma4/udma5
	330	*/
	331	pci_read_config_byte(pdev, 0x5A, &btr);
	332	btr &= ~0x40;
	333	if (!(PCI_FUNC(pdev->devfn) & 1))
	334	btr \|= 0x2;
	335	else
44c10138	336	btr \|= (pdev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
669a5db4	337	pci_write_config_byte(pdev, 0x5A, btr);
85cd7251	338
669a5db4 JG	339	return btr;
	340	}
	341
	342	static void serverworks_fixup_ht1000(struct pci_dev *pdev)
	343	{
	344	u8 btr;
	345	/* Setup HT1000 SouthBridge Controller - Single Channel Only */
	346	pci_read_config_byte(pdev, 0x5A, &btr);
	347	btr &= ~0x40;
	348	btr \|= 0x3;
	349	pci_write_config_byte(pdev, 0x5A, btr);
	350	}
	351
d912be2f BZ	352	static int serverworks_fixup(struct pci_dev *pdev)
	353	{
	354	int rc = 0;
	355
	356	/* Force master latency timer to 64 PCI clocks */
	357	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
	358
	359	switch (pdev->device) {
	360	case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE:
	361	rc = serverworks_fixup_osb4(pdev);
	362	break;
	363	case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
	364	ata_pci_bmdma_clear_simplex(pdev);
	365	/* fall through */
	366	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
	367	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
	368	rc = serverworks_fixup_csb(pdev);
	369	break;
	370	case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
	371	serverworks_fixup_ht1000(pdev);
	372	break;
	373	}
	374
	375	return rc;
	376	}
669a5db4 JG	377
	378	static int serverworks_init_one(struct pci_dev pdev, const struct pci_device_id id)
	379	{
1626aeb8	380	static const struct ata_port_info info[4] = {
669a5db4	381	{ /* OSB4 */
1d2808fd	382	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	383	.pio_mask = ATA_PIO4,
	384	.mwdma_mask = ATA_MWDMA2,
	385	.udma_mask = ATA_UDMA2,
669a5db4 JG	386	.port_ops = &serverworks_osb4_port_ops
669a5db4 JG	387	}, { /* OSB4 no UDMA */
1d2808fd	388	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	389	.pio_mask = ATA_PIO4,
	390	.mwdma_mask = ATA_MWDMA2,
	391	/* No UDMA */
669a5db4 JG	392	.port_ops = &serverworks_osb4_port_ops
669a5db4 JG	393	}, { /* CSB5 */
1d2808fd	394	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	395	.pio_mask = ATA_PIO4,
14bdef98 EIB	396	.mwdma_mask = ATA_MWDMA2,
bf6263a8	397	.udma_mask = ATA_UDMA4,
669a5db4 JG	398	.port_ops = &serverworks_csb_port_ops
669a5db4 JG	399	}, { /* CSB5 - later revisions*/
1d2808fd	400	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	401	.pio_mask = ATA_PIO4,
14bdef98 EIB	402	.mwdma_mask = ATA_MWDMA2,
bf6263a8	403	.udma_mask = ATA_UDMA5,
669a5db4 JG	404	.port_ops = &serverworks_csb_port_ops
	405	}
	406	};
1626aeb8	407	const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
f08048e9 TH	408	int rc;
	409
	410	rc = pcim_enable_device(pdev);
	411	if (rc)
	412	return rc;
85cd7251	413
d912be2f	414	rc = serverworks_fixup(pdev);
669a5db4 JG	415
	416	/* OSB4 : South Bridge and IDE */
	417	if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
	418	/* Select non UDMA capable OSB4 if we can't do fixups */
d912be2f	419	if (rc < 0)
1626aeb8	420	ppi[0] = &info[1];
669a5db4 JG	421	}
	422	/* setup CSB5/CSB6 : South Bridge and IDE option RAID */
	423	else if ((pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) \|\|
	424	(pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) \|\|
	425	(pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
85cd7251	426
669a5db4 JG	427	/* If the returned btr is the newer revision then
669a5db4 JG	428	select the right info block */
d912be2f	429	if (rc == 3)
1626aeb8	430	ppi[0] = &info[3];
85cd7251	431
669a5db4 JG	432	/* Is this the 3rd channel CSB6 IDE ? */
669a5db4 JG	433	if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)
1626aeb8	434	ppi[1] = &ata_dummy_port_info;
669a5db4	435	}
85cd7251	436
1c5afdf7	437	return ata_pci_bmdma_init_one(pdev, ppi, &serverworks_sht, NULL, 0);
669a5db4 JG	438	}
669a5db4 JG	439
438ac6d5	440	#ifdef CONFIG_PM
38e0d56e AC	441	static int serverworks_reinit_one(struct pci_dev *pdev)
38e0d56e AC	442	{
f08048e9 TH	443	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	444	int rc;
	445
	446	rc = ata_pci_device_do_resume(pdev);
	447	if (rc)
	448	return rc;
	449
d912be2f	450	(void)serverworks_fixup(pdev);
f08048e9 TH	451
	452	ata_host_resume(host);
	453	return 0;
38e0d56e	454	}
438ac6d5	455	#endif
38e0d56e	456
2d2744fc JG	457	static const struct pci_device_id serverworks[] = {
	458	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0},
	459	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 2},
	460	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2},
	461	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 2},
	462	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 2},
	463
	464	{ },
669a5db4 JG	465	};
	466
	467	static struct pci_driver serverworks_pci_driver = {
	468	.name = DRV_NAME,
	469	.id_table = serverworks,
	470	.probe = serverworks_init_one,
38e0d56e	471	.remove = ata_pci_remove_one,
438ac6d5	472	#ifdef CONFIG_PM
38e0d56e AC	473	.suspend = ata_pci_device_suspend,
38e0d56e AC	474	.resume = serverworks_reinit_one,
438ac6d5	475	#endif
669a5db4 JG	476	};
669a5db4 JG	477
2fc75da0	478	module_pci_driver(serverworks_pci_driver);
669a5db4	479
669a5db4 JG	480	MODULE_AUTHOR("Alan Cox");
	481	MODULE_DESCRIPTION("low-level driver for Serverworks OSB4/CSB5/CSB6");
	482	MODULE_LICENSE("GPL");
	483	MODULE_DEVICE_TABLE(pci, serverworks);
	484	MODULE_VERSION(DRV_VERSION);