drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / pata_platform.c
CommitLineData
a20c9e82
PM
1/*
2 * Generic platform device PATA driver
3 *
f7fc0ceb 4 * Copyright (C) 2006 - 2007 Paul Mundt
a20c9e82
PM
5 *
6 * Based on pata_pcmcia:
7 *
ab771630 8 * Copyright 2005-2006 Red Hat Inc, all rights reserved.
a20c9e82
PM
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/blkdev.h>
18#include <scsi/scsi_host.h>
19#include <linux/ata.h>
20#include <linux/libata.h>
21#include <linux/platform_device.h>
0a87e3e9 22#include <linux/ata_platform.h>
a20c9e82
PM
23
24#define DRV_NAME "pata_platform"
f7fc0ceb 25#define DRV_VERSION "1.2"
a20c9e82
PM
26
27static int pio_mask = 1;
28
29/*
30 * Provide our own set_mode() as we don't want to change anything that has
31 * already been configured..
32 */
0260731f 33static int pata_platform_set_mode(struct ata_link *link, struct ata_device **unused)
a20c9e82 34{
f58229f8 35 struct ata_device *dev;
a20c9e82 36
1eca4365
TH
37 ata_for_each_dev(dev, link, ENABLED) {
38 /* We don't really care */
39 dev->pio_mode = dev->xfer_mode = XFER_PIO_0;
40 dev->xfer_shift = ATA_SHIFT_PIO;
41 dev->flags |= ATA_DFLAG_PIO;
a9a79dfe 42 ata_dev_info(dev, "configured for PIO\n");
a20c9e82 43 }
161c888b 44 return 0;
a20c9e82
PM
45}
46
a20c9e82 47static struct scsi_host_template pata_platform_sht = {
68d1d07b 48 ATA_PIO_SHT(DRV_NAME),
a20c9e82
PM
49};
50
51static struct ata_port_operations pata_platform_port_ops = {
029cfd6b 52 .inherits = &ata_sff_port_ops,
5682ed33 53 .sff_data_xfer = ata_sff_data_xfer_noirq,
029cfd6b
TH
54 .cable_detect = ata_cable_unknown,
55 .set_mode = pata_platform_set_mode,
a20c9e82
PM
56};
57
58static void pata_platform_setup_port(struct ata_ioports *ioaddr,
cf03613e 59 unsigned int shift)
a20c9e82 60{
a20c9e82 61 /* Fixup the port shift for platforms that need it */
a20c9e82
PM
62 ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << shift);
63 ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << shift);
64 ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << shift);
65 ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << shift);
66 ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << shift);
67 ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << shift);
68 ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << shift);
69 ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << shift);
70 ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << shift);
71 ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << shift);
72}
73
74/**
cf03613e
AV
75 * __pata_platform_probe - attach a platform interface
76 * @dev: device
77 * @io_res: Resource representing I/O base
78 * @ctl_res: Resource representing CTL base
79 * @irq_res: Resource representing IRQ and its flags
80 * @ioport_shift: I/O port shift
81 * @__pio_mask: PIO mask
a20c9e82
PM
82 *
83 * Register a platform bus IDE interface. Such interfaces are PIO and we
84 * assume do not support IRQ sharing.
85 *
f7fc0ceb 86 * Platform devices are expected to contain at least 2 resources per port:
a20c9e82
PM
87 *
88 * - I/O Base (IORESOURCE_IO or IORESOURCE_MEM)
89 * - CTL Base (IORESOURCE_IO or IORESOURCE_MEM)
f7fc0ceb
PM
90 *
91 * and optionally:
92 *
a20c9e82
PM
93 * - IRQ (IORESOURCE_IRQ)
94 *
95 * If the base resources are both mem types, the ioremap() is handled
96 * here. For IORESOURCE_IO, it's assumed that there's no remapping
97 * necessary.
f7fc0ceb
PM
98 *
99 * If no IRQ resource is present, PIO polling mode is used instead.
a20c9e82 100 */
0ec24914
GKH
101int __pata_platform_probe(struct device *dev, struct resource *io_res,
102 struct resource *ctl_res, struct resource *irq_res,
103 unsigned int ioport_shift, int __pio_mask)
a20c9e82 104{
5d728824
TH
105 struct ata_host *host;
106 struct ata_port *ap;
a20c9e82 107 unsigned int mmio;
cf03613e
AV
108 int irq = 0;
109 int irq_flags = 0;
a20c9e82
PM
110
111 /*
112 * Check for MMIO
113 */
114 mmio = (( io_res->flags == IORESOURCE_MEM) &&
115 (ctl_res->flags == IORESOURCE_MEM));
116
f7fc0ceb
PM
117 /*
118 * And the IRQ
119 */
cf03613e
AV
120 if (irq_res && irq_res->start > 0) {
121 irq = irq_res->start;
122 irq_flags = irq_res->flags;
123 }
f7fc0ceb 124
a20c9e82
PM
125 /*
126 * Now that that's out of the way, wire up the port..
127 */
cf03613e 128 host = ata_host_alloc(dev, 1);
5d728824
TH
129 if (!host)
130 return -ENOMEM;
131 ap = host->ports[0];
132
133 ap->ops = &pata_platform_port_ops;
cf03613e 134 ap->pio_mask = __pio_mask;
5d728824 135 ap->flags |= ATA_FLAG_SLAVE_POSS;
a20c9e82 136
f7fc0ceb
PM
137 /*
138 * Use polling mode if there's no IRQ
139 */
140 if (!irq) {
141 ap->flags |= ATA_FLAG_PIO_POLLING;
142 ata_port_desc(ap, "no IRQ, using PIO polling");
143 }
144
a20c9e82
PM
145 /*
146 * Handle the MMIO case
147 */
148 if (mmio) {
cf03613e 149 ap->ioaddr.cmd_addr = devm_ioremap(dev, io_res->start,
041b5eac 150 resource_size(io_res));
cf03613e 151 ap->ioaddr.ctl_addr = devm_ioremap(dev, ctl_res->start,
041b5eac 152 resource_size(ctl_res));
a20c9e82 153 } else {
cf03613e 154 ap->ioaddr.cmd_addr = devm_ioport_map(dev, io_res->start,
041b5eac 155 resource_size(io_res));
cf03613e 156 ap->ioaddr.ctl_addr = devm_ioport_map(dev, ctl_res->start,
041b5eac 157 resource_size(ctl_res));
0d5ff566 158 }
5d728824 159 if (!ap->ioaddr.cmd_addr || !ap->ioaddr.ctl_addr) {
cf03613e 160 dev_err(dev, "failed to map IO/CTL base\n");
0d5ff566 161 return -ENOMEM;
a20c9e82
PM
162 }
163
5d728824 164 ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
a20c9e82 165
cf03613e 166 pata_platform_setup_port(&ap->ioaddr, ioport_shift);
a20c9e82 167
cbcdd875
TH
168 ata_port_desc(ap, "%s cmd 0x%llx ctl 0x%llx", mmio ? "mmio" : "ioport",
169 (unsigned long long)io_res->start,
170 (unsigned long long)ctl_res->start);
171
5d728824 172 /* activate */
9363c382 173 return ata_host_activate(host, irq, irq ? ata_sff_interrupt : NULL,
cf03613e 174 irq_flags, &pata_platform_sht);
a20c9e82 175}
cf03613e 176EXPORT_SYMBOL_GPL(__pata_platform_probe);
a20c9e82 177
0ec24914 178static int pata_platform_probe(struct platform_device *pdev)
cf03613e
AV
179{
180 struct resource *io_res;
181 struct resource *ctl_res;
182 struct resource *irq_res;
183 struct pata_platform_info *pp_info = pdev->dev.platform_data;
184
185 /*
186 * Simple resource validation ..
187 */
188 if ((pdev->num_resources != 3) && (pdev->num_resources != 2)) {
189 dev_err(&pdev->dev, "invalid number of resources\n");
190 return -EINVAL;
191 }
192
193 /*
194 * Get the I/O base first
195 */
196 io_res = platform_get_resource(pdev, IORESOURCE_IO, 0);
197 if (io_res == NULL) {
198 io_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
199 if (unlikely(io_res == NULL))
200 return -EINVAL;
201 }
202
203 /*
204 * Then the CTL base
205 */
206 ctl_res = platform_get_resource(pdev, IORESOURCE_IO, 1);
207 if (ctl_res == NULL) {
208 ctl_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
209 if (unlikely(ctl_res == NULL))
210 return -EINVAL;
211 }
212
213 /*
214 * And the IRQ
215 */
216 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
217 if (irq_res)
218 irq_res->flags = pp_info ? pp_info->irq_flags : 0;
219
220 return __pata_platform_probe(&pdev->dev, io_res, ctl_res, irq_res,
221 pp_info ? pp_info->ioport_shift : 0,
222 pio_mask);
223}
224
a20c9e82
PM
225static struct platform_driver pata_platform_driver = {
226 .probe = pata_platform_probe,
ccd1196a 227 .remove = ata_platform_remove_one,
a20c9e82
PM
228 .driver = {
229 .name = DRV_NAME,
230 .owner = THIS_MODULE,
231 },
232};
233
99c8ea3e 234module_platform_driver(pata_platform_driver);
a20c9e82
PM
235
236module_param(pio_mask, int, 0);
237
238MODULE_AUTHOR("Paul Mundt");
239MODULE_DESCRIPTION("low-level driver for platform device ATA");
240MODULE_LICENSE("GPL");
241MODULE_VERSION(DRV_VERSION);
458622fc 242MODULE_ALIAS("platform:" DRV_NAME);