[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / pata_jmicron.c

/*
 *    pata_jmicron.c - JMicron ATA driver for non AHCI mode. This drives the
 *			PATA port of the controller. The SATA ports are
 *			driven by AHCI in the usual configuration although
 *			this driver can handle other setups if we need it.
 *
 *	(c) 2006 Red Hat
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <linux/ata.h>

#define DRV_NAME	"pata_jmicron"
#define DRV_VERSION	"0.1.5"

typedef enum {
	PORT_PATA0 = 0,
	PORT_PATA1 = 1,
	PORT_SATA = 2,
} port_type;

/**
 *	jmicron_pre_reset	-	check for 40/80 pin
 *	@link: ATA link
 *	@deadline: deadline jiffies for the operation
 *
 *	Perform the PATA port setup we need.
 *
 *	On the Jmicron 361/363 there is a single PATA port that can be mapped
 *	either as primary or secondary (or neither). We don't do any policy
 *	and setup here. We assume that has been done by init_one and the
 *	BIOS.
 */
static int jmicron_pre_reset(struct ata_link *link, unsigned long deadline)
{
	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u32 control;
	u32 control5;
	int port_mask = 1<< (4 * ap->port_no);
	int port = ap->port_no;
	port_type port_map[2];

	/* Check if our port is enabled */
	pci_read_config_dword(pdev, 0x40, &control);
	if ((control & port_mask) == 0)
		return -ENOENT;

	/* There are two basic mappings. One has the two SATA ports merged
	   as master/slave and the secondary as PATA, the other has only the
	   SATA port mapped */
	if (control & (1 << 23)) {
		port_map[0] = PORT_SATA;
		port_map[1] = PORT_PATA0;
	} else {
		port_map[0] = PORT_SATA;
		port_map[1] = PORT_SATA;
	}

	/* The 365/366 may have this bit set to map the second PATA port
	   as the internal primary channel */
	pci_read_config_dword(pdev, 0x80, &control5);
	if (control5 & (1<<24))
		port_map[0] = PORT_PATA1;

	/* The two ports may then be logically swapped by the firmware */
	if (control & (1 << 22))
		port = port ^ 1;

	/*
	 *	Now we know which physical port we are talking about we can
	 *	actually do our cable checking etc. Thankfully we don't need
	 *	to do the plumbing for other cases.
	 */
	switch (port_map[port]) {
	case PORT_PATA0:
		if ((control & (1 << 5)) == 0)
			return -ENOENT;
		if (control & (1 << 3))	/* 40/80 pin primary */
			ap->cbl = ATA_CBL_PATA40;
		else
			ap->cbl = ATA_CBL_PATA80;
		break;
	case PORT_PATA1:
		/* Bit 21 is set if the port is enabled */
		if ((control5 & (1 << 21)) == 0)
			return -ENOENT;
		if (control5 & (1 << 19))	/* 40/80 pin secondary */
			ap->cbl = ATA_CBL_PATA40;
		else
			ap->cbl = ATA_CBL_PATA80;
		break;
	case PORT_SATA:
		ap->cbl = ATA_CBL_SATA;
		break;
	}
	return ata_sff_prereset(link, deadline);
}

/* No PIO or DMA methods needed for this device */

static struct scsi_host_template jmicron_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations jmicron_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.prereset		= jmicron_pre_reset,
};


/**
 *	jmicron_init_one - Register Jmicron ATA PCI device with kernel services
 *	@pdev: PCI device to register
 *	@ent: Entry in jmicron_pci_tbl matching with @pdev
 *
 *	Called from kernel PCI layer.
 *
 *	LOCKING:
 *	Inherited from PCI layer (may sleep).
 *
 *	RETURNS:
 *	Zero on success, or -ERRNO value.
 */

static int jmicron_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const struct ata_port_info info = {
		.flags	= ATA_FLAG_SLAVE_POSS,

		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask 	= ATA_UDMA5,

		.port_ops	= &jmicron_ops,
	};
	const struct ata_port_info *ppi[] = { &info, NULL };

	return ata_pci_bmdma_init_one(pdev, ppi, &jmicron_sht, NULL, 0);
}

static const struct pci_device_id jmicron_pci_tbl[] = {
	{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	  PCI_CLASS_STORAGE_IDE << 8, 0xffff00, 0 },
	{ }	/* terminate list */
};

static struct pci_driver jmicron_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= jmicron_pci_tbl,
	.probe			= jmicron_init_one,
	.remove			= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend		= ata_pci_device_suspend,
	.resume			= ata_pci_device_resume,
#endif
};

module_pci_driver(jmicron_pci_driver);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("SCSI low-level driver for Jmicron PATA ports");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, jmicron_pci_tbl);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_jmicron.c - JMicron ATA driver for non AHCI mode. This drives the
	3	* PATA port of the controller. The SATA ports are
	4	* driven by AHCI in the usual configuration although
	5	* this driver can handle other setups if we need it.
	6	*
ab771630	7	* (c) 2006 Red Hat
669a5db4 JG	8	*/
	9
	10	#include <linux/kernel.h>
	11	#include <linux/module.h>
	12	#include <linux/pci.h>
	13	#include <linux/init.h>
	14	#include <linux/blkdev.h>
	15	#include <linux/delay.h>
	16	#include <linux/device.h>
	17	#include <scsi/scsi_host.h>
	18	#include <linux/libata.h>
	19	#include <linux/ata.h>
	20
	21	#define DRV_NAME "pata_jmicron"
8bc3fc47	22	#define DRV_VERSION "0.1.5"
669a5db4 JG	23
	24	typedef enum {
	25	PORT_PATA0 = 0,
	26	PORT_PATA1 = 1,
	27	PORT_SATA = 2,
	28	} port_type;
	29
	30	/**
	31	* jmicron_pre_reset - check for 40/80 pin
cc0680a5	32	* @link: ATA link
d4b2bab4	33	* @deadline: deadline jiffies for the operation
669a5db4 JG	34	*
669a5db4 JG	35	* Perform the PATA port setup we need.
d4b2bab4	36	*
669a5db4 JG	37	* On the Jmicron 361/363 there is a single PATA port that can be mapped
	38	* either as primary or secondary (or neither). We don't do any policy
	39	* and setup here. We assume that has been done by init_one and the
	40	* BIOS.
	41	*/
cc0680a5	42	static int jmicron_pre_reset(struct ata_link *link, unsigned long deadline)
669a5db4	43	{
cc0680a5	44	struct ata_port *ap = link->ap;
669a5db4 JG	45	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	46	u32 control;
	47	u32 control5;
	48	int port_mask = 1<< (4 * ap->port_no);
	49	int port = ap->port_no;
	50	port_type port_map[2];
	51
	52	/* Check if our port is enabled */
	53	pci_read_config_dword(pdev, 0x40, &control);
	54	if ((control & port_mask) == 0)
c961922b	55	return -ENOENT;
669a5db4 JG	56
	57	/* There are two basic mappings. One has the two SATA ports merged
	58	as master/slave and the secondary as PATA, the other has only the
	59	SATA port mapped */
	60	if (control & (1 << 23)) {
	61	port_map[0] = PORT_SATA;
	62	port_map[1] = PORT_PATA0;
	63	} else {
	64	port_map[0] = PORT_SATA;
	65	port_map[1] = PORT_SATA;
	66	}
	67
	68	/* The 365/366 may have this bit set to map the second PATA port
	69	as the internal primary channel */
	70	pci_read_config_dword(pdev, 0x80, &control5);
	71	if (control5 & (1<<24))
	72	port_map[0] = PORT_PATA1;
	73
	74	/* The two ports may then be logically swapped by the firmware */
	75	if (control & (1 << 22))
	76	port = port ^ 1;
	77
	78	/*
	79	* Now we know which physical port we are talking about we can
	80	* actually do our cable checking etc. Thankfully we don't need
	81	* to do the plumbing for other cases.
	82	*/
0706efd6	83	switch (port_map[port]) {
669a5db4	84	case PORT_PATA0:
0706efd6 TH	85	if ((control & (1 << 5)) == 0)
0706efd6 TH	86	return -ENOENT;
669a5db4 JG	87	if (control & (1 << 3)) /* 40/80 pin primary */
	88	ap->cbl = ATA_CBL_PATA40;
	89	else
	90	ap->cbl = ATA_CBL_PATA80;
	91	break;
	92	case PORT_PATA1:
	93	/* Bit 21 is set if the port is enabled */
	94	if ((control5 & (1 << 21)) == 0)
0706efd6	95	return -ENOENT;
669a5db4 JG	96	if (control5 & (1 << 19)) /* 40/80 pin secondary */
	97	ap->cbl = ATA_CBL_PATA40;
	98	else
	99	ap->cbl = ATA_CBL_PATA80;
	100	break;
	101	case PORT_SATA:
	102	ap->cbl = ATA_CBL_SATA;
	103	break;
	104	}
9363c382	105	return ata_sff_prereset(link, deadline);
669a5db4 JG	106	}
669a5db4 JG	107
669a5db4 JG	108	/* No PIO or DMA methods needed for this device */
	109
	110	static struct scsi_host_template jmicron_sht = {
68d1d07b	111	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	112	};
669a5db4 JG	113
029cfd6b TH	114	static struct ata_port_operations jmicron_ops = {
029cfd6b TH	115	.inherits = &ata_bmdma_port_ops,
887125e3	116	.prereset = jmicron_pre_reset,
669a5db4 JG	117	};
	118
	119
	120	/**
	121	* jmicron_init_one - Register Jmicron ATA PCI device with kernel services
	122	* @pdev: PCI device to register
	123	* @ent: Entry in jmicron_pci_tbl matching with @pdev
	124	*
	125	* Called from kernel PCI layer.
	126	*
	127	* LOCKING:
	128	* Inherited from PCI layer (may sleep).
	129	*
	130	* RETURNS:
	131	* Zero on success, or -ERRNO value.
	132	*/
	133
	134	static int jmicron_init_one (struct pci_dev pdev, const struct pci_device_id id)
	135	{
1626aeb8	136	static const struct ata_port_info info = {
1d2808fd	137	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4	138
14bdef98 EIB	139	.pio_mask = ATA_PIO4,
14bdef98 EIB	140	.mwdma_mask = ATA_MWDMA2,
bf6263a8	141	.udma_mask = ATA_UDMA5,
669a5db4 JG	142
	143	.port_ops = &jmicron_ops,
	144	};
1626aeb8	145	const struct ata_port_info *ppi[] = { &info, NULL };
669a5db4	146
1c5afdf7	147	return ata_pci_bmdma_init_one(pdev, ppi, &jmicron_sht, NULL, 0);
669a5db4 JG	148	}
	149
	150	static const struct pci_device_id jmicron_pci_tbl[] = {
a01f48b8 TH	151	{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
a01f48b8 TH	152	PCI_CLASS_STORAGE_IDE << 8, 0xffff00, 0 },
669a5db4 JG	153	{ } /* terminate list */
	154	};
	155
	156	static struct pci_driver jmicron_pci_driver = {
	157	.name = DRV_NAME,
	158	.id_table = jmicron_pci_tbl,
	159	.probe = jmicron_init_one,
	160	.remove = ata_pci_remove_one,
438ac6d5	161	#ifdef CONFIG_PM
d39ca896	162	.suspend = ata_pci_device_suspend,
960627b7	163	.resume = ata_pci_device_resume,
438ac6d5	164	#endif
669a5db4 JG	165	};
669a5db4 JG	166
2fc75da0	167	module_pci_driver(jmicron_pci_driver);
669a5db4 JG	168
	169	MODULE_AUTHOR("Alan Cox");
	170	MODULE_DESCRIPTION("SCSI low-level driver for Jmicron PATA ports");
	171	MODULE_LICENSE("GPL");
	172	MODULE_DEVICE_TABLE(pci, jmicron_pci_tbl);
	173	MODULE_VERSION(DRV_VERSION);
	174