[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / pata_efar.c

/*
 *    pata_efar.c - EFAR PIIX clone controller driver
 *
 *	(C) 2005 Red Hat
 *	(C) 2009-2010 Bartlomiej Zolnierkiewicz
 *
 *    Some parts based on ata_piix.c by Jeff Garzik and others.
 *
 *    The EFAR is a PIIX4 clone with UDMA66 support. Unlike the later
 *    Intel ICH controllers the EFAR widened the UDMA mode register bits
 *    and doesn't require the funky clock selection.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <linux/ata.h>

#define DRV_NAME	"pata_efar"
#define DRV_VERSION	"0.4.5"

/**
 *	efar_pre_reset	-	Enable bits
 *	@link: ATA link
 *	@deadline: deadline jiffies for the operation
 *
 *	Perform cable detection for the EFAR ATA interface. This is
 *	different to the PIIX arrangement
 */

static int efar_pre_reset(struct ata_link *link, unsigned long deadline)
{
	static const struct pci_bits efar_enable_bits[] = {
		{ 0x41U, 1U, 0x80UL, 0x80UL },	/* port 0 */
		{ 0x43U, 1U, 0x80UL, 0x80UL },	/* port 1 */
	};
	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	if (!pci_test_config_bits(pdev, &efar_enable_bits[ap->port_no]))
		return -ENOENT;

	return ata_sff_prereset(link, deadline);
}

/**
 *	efar_cable_detect	-	check for 40/80 pin
 *	@ap: Port
 *
 *	Perform cable detection for the EFAR ATA interface. This is
 *	different to the PIIX arrangement
 */

static int efar_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 tmp;

	pci_read_config_byte(pdev, 0x47, &tmp);
	if (tmp & (2 >> ap->port_no))
		return ATA_CBL_PATA40;
	return ATA_CBL_PATA80;
}

static DEFINE_SPINLOCK(efar_lock);

/**
 *	efar_set_piomode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device to program
 *
 *	Set PIO mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev)
{
	unsigned int pio	= adev->pio_mode - XFER_PIO_0;
	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
	unsigned int master_port = ap->port_no ? 0x42 : 0x40;
	unsigned long flags;
	u16 master_data;
	u8 udma_enable;
	int control = 0;

	/*
	 *	See Intel Document 298600-004 for the timing programing rules
	 *	for PIIX/ICH. The EFAR is a clone so very similar
	 */

	static const	 /* ISP  RTC */
	u8 timings[][2]	= { { 0, 0 },
			    { 0, 0 },
			    { 1, 0 },
			    { 2, 1 },
			    { 2, 3 }, };

	if (pio > 1)
		control |= 1;	/* TIME */
	if (ata_pio_need_iordy(adev))	/* PIO 3/4 require IORDY */
		control |= 2;	/* IE */
	/* Intel specifies that the prefetch/posting is for disk only */
	if (adev->class == ATA_DEV_ATA)
		control |= 4;	/* PPE */

	spin_lock_irqsave(&efar_lock, flags);

	pci_read_config_word(dev, master_port, &master_data);

	/* Set PPE, IE, and TIME as appropriate */
	if (adev->devno == 0) {
		master_data &= 0xCCF0;
		master_data |= control;
		master_data |= (timings[pio][0] << 12) |
			(timings[pio][1] << 8);
	} else {
		int shift = 4 * ap->port_no;
		u8 slave_data;

		master_data &= 0xFF0F;
		master_data |= (control << 4);

		/* Slave timing in separate register */
		pci_read_config_byte(dev, 0x44, &slave_data);
		slave_data &= ap->port_no ? 0x0F : 0xF0;
		slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << shift;
		pci_write_config_byte(dev, 0x44, slave_data);
	}

	master_data |= 0x4000;	/* Ensure SITRE is set */
	pci_write_config_word(dev, master_port, master_data);

	pci_read_config_byte(dev, 0x48, &udma_enable);
	udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
	pci_write_config_byte(dev, 0x48, udma_enable);
	spin_unlock_irqrestore(&efar_lock, flags);
}

/**
 *	efar_set_dmamode - Initialize host controller PATA DMA timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device to program
 *
 *	Set UDMA/MWDMA mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void efar_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
	u8 master_port		= ap->port_no ? 0x42 : 0x40;
	u16 master_data;
	u8 speed		= adev->dma_mode;
	int devid		= adev->devno + 2 * ap->port_no;
	unsigned long flags;
	u8 udma_enable;

	static const	 /* ISP  RTC */
	u8 timings[][2]	= { { 0, 0 },
			    { 0, 0 },
			    { 1, 0 },
			    { 2, 1 },
			    { 2, 3 }, };

	spin_lock_irqsave(&efar_lock, flags);

	pci_read_config_word(dev, master_port, &master_data);
	pci_read_config_byte(dev, 0x48, &udma_enable);

	if (speed >= XFER_UDMA_0) {
		unsigned int udma	= adev->dma_mode - XFER_UDMA_0;
		u16 udma_timing;

		udma_enable |= (1 << devid);

		/* Load the UDMA mode number */
		pci_read_config_word(dev, 0x4A, &udma_timing);
		udma_timing &= ~(7 << (4 * devid));
		udma_timing |= udma << (4 * devid);
		pci_write_config_word(dev, 0x4A, udma_timing);
	} else {
		/*
		 * MWDMA is driven by the PIO timings. We must also enable
		 * IORDY unconditionally along with TIME1. PPE has already
		 * been set when the PIO timing was set.
		 */
		unsigned int mwdma	= adev->dma_mode - XFER_MW_DMA_0;
		unsigned int control;
		u8 slave_data;
		const unsigned int needed_pio[3] = {
			XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
		};
		int pio = needed_pio[mwdma] - XFER_PIO_0;

		control = 3;	/* IORDY|TIME1 */

		/* If the drive MWDMA is faster than it can do PIO then
		   we must force PIO into PIO0 */

		if (adev->pio_mode < needed_pio[mwdma])
			/* Enable DMA timing only */
			control |= 8;	/* PIO cycles in PIO0 */

		if (adev->devno) {	/* Slave */
			master_data &= 0xFF4F;  /* Mask out IORDY|TIME1|DMAONLY */
			master_data |= control << 4;
			pci_read_config_byte(dev, 0x44, &slave_data);
			slave_data &= ap->port_no ? 0x0F : 0xF0;
			/* Load the matching timing */
			slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
			pci_write_config_byte(dev, 0x44, slave_data);
		} else { 	/* Master */
			master_data &= 0xCCF4;	/* Mask out IORDY|TIME1|DMAONLY
						   and master timing bits */
			master_data |= control;
			master_data |=
				(timings[pio][0] << 12) |
				(timings[pio][1] << 8);
		}
		udma_enable &= ~(1 << devid);
		pci_write_config_word(dev, master_port, master_data);
	}
	pci_write_config_byte(dev, 0x48, udma_enable);
	spin_unlock_irqrestore(&efar_lock, flags);
}

static struct scsi_host_template efar_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations efar_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.cable_detect		= efar_cable_detect,
	.set_piomode		= efar_set_piomode,
	.set_dmamode		= efar_set_dmamode,
	.prereset		= efar_pre_reset,
};


/**
 *	efar_init_one - Register EFAR ATA PCI device with kernel services
 *	@pdev: PCI device to register
 *	@ent: Entry in efar_pci_tbl matching with @pdev
 *
 *	Called from kernel PCI layer.
 *
 *	LOCKING:
 *	Inherited from PCI layer (may sleep).
 *
 *	RETURNS:
 *	Zero on success, or -ERRNO value.
 */

static int efar_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static const struct ata_port_info info = {
		.flags		= ATA_FLAG_SLAVE_POSS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA12_ONLY,
		.udma_mask 	= ATA_UDMA4,
		.port_ops	= &efar_ops,
	};
	const struct ata_port_info *ppi[] = { &info, &info };

	ata_print_version_once(&pdev->dev, DRV_VERSION);

	return ata_pci_bmdma_init_one(pdev, ppi, &efar_sht, NULL,
				      ATA_HOST_PARALLEL_SCAN);
}

static const struct pci_device_id efar_pci_tbl[] = {
	{ PCI_VDEVICE(EFAR, 0x9130), },

	{ }	/* terminate list */
};

static struct pci_driver efar_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= efar_pci_tbl,
	.probe			= efar_init_one,
	.remove			= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend		= ata_pci_device_suspend,
	.resume			= ata_pci_device_resume,
#endif
};

module_pci_driver(efar_pci_driver);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("SCSI low-level driver for EFAR PIIX clones");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, efar_pci_tbl);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_efar.c - EFAR PIIX clone controller driver
	3	*
ab771630	4	* (C) 2005 Red Hat
73e2e3d0	5	* (C) 2009-2010 Bartlomiej Zolnierkiewicz
669a5db4 JG	6	*
	7	* Some parts based on ata_piix.c by Jeff Garzik and others.
	8	*
	9	* The EFAR is a PIIX4 clone with UDMA66 support. Unlike the later
	10	* Intel ICH controllers the EFAR widened the UDMA mode register bits
	11	* and doesn't require the funky clock selection.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/module.h>
	16	#include <linux/pci.h>
	17	#include <linux/init.h>
	18	#include <linux/blkdev.h>
	19	#include <linux/delay.h>
	20	#include <linux/device.h>
	21	#include <scsi/scsi_host.h>
	22	#include <linux/libata.h>
	23	#include <linux/ata.h>
	24
	25	#define DRV_NAME "pata_efar"
5f33b3bc	26	#define DRV_VERSION "0.4.5"
669a5db4 JG	27
669a5db4 JG	28	/**
6bfed3fb	29	* efar_pre_reset - Enable bits
cc0680a5	30	* @link: ATA link
d4b2bab4	31	* @deadline: deadline jiffies for the operation
669a5db4 JG	32	*
	33	* Perform cable detection for the EFAR ATA interface. This is
	34	* different to the PIIX arrangement
	35	*/
	36
cc0680a5	37	static int efar_pre_reset(struct ata_link *link, unsigned long deadline)
669a5db4 JG	38	{
	39	static const struct pci_bits efar_enable_bits[] = {
	40	{ 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
	41	{ 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
	42	};
cc0680a5	43	struct ata_port *ap = link->ap;
669a5db4	44	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
669a5db4	45
c961922b AC	46	if (!pci_test_config_bits(pdev, &efar_enable_bits[ap->port_no]))
	47	return -ENOENT;
	48
9363c382	49	return ata_sff_prereset(link, deadline);
669a5db4 JG	50	}
669a5db4 JG	51
6bfed3fb AC	52	/**
	53	* efar_cable_detect - check for 40/80 pin
	54	* @ap: Port
	55	*
	56	* Perform cable detection for the EFAR ATA interface. This is
	57	* different to the PIIX arrangement
	58	*/
	59
	60	static int efar_cable_detect(struct ata_port *ap)
	61	{
	62	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	63	u8 tmp;
	64
	65	pci_read_config_byte(pdev, 0x47, &tmp);
	66	if (tmp & (2 >> ap->port_no))
	67	return ATA_CBL_PATA40;
	68	return ATA_CBL_PATA80;
	69	}
	70
303f1a76 BZ	71	static DEFINE_SPINLOCK(efar_lock);
303f1a76 BZ	72
669a5db4 JG	73	/**
	74	* efar_set_piomode - Initialize host controller PATA PIO timings
	75	* @ap: Port whose timings we are configuring
a0da1914	76	* @adev: Device to program
669a5db4 JG	77	*
	78	* Set PIO mode for device, in host controller PCI config space.
	79	*
	80	* LOCKING:
	81	* None (inherited from caller).
	82	*/
	83
	84	static void efar_set_piomode (struct ata_port ap, struct ata_device adev)
	85	{
	86	unsigned int pio = adev->pio_mode - XFER_PIO_0;
	87	struct pci_dev *dev = to_pci_dev(ap->host->dev);
a0da1914	88	unsigned int master_port = ap->port_no ? 0x42 : 0x40;
303f1a76	89	unsigned long flags;
a0da1914	90	u16 master_data;
303f1a76	91	u8 udma_enable;
669a5db4 JG	92	int control = 0;
	93
	94	/*
	95	* See Intel Document 298600-004 for the timing programing rules
	96	* for PIIX/ICH. The EFAR is a clone so very similar
	97	*/
	98
	99	static const /* ISP RTC */
	100	u8 timings[][2] = { { 0, 0 },
	101	{ 0, 0 },
	102	{ 1, 0 },
	103	{ 2, 1 },
	104	{ 2, 3 }, };
	105
5f33b3bc SS	106	if (pio > 1)
5f33b3bc SS	107	control \|= 1; /* TIME */
669a5db4	108	if (ata_pio_need_iordy(adev)) /* PIO 3/4 require IORDY */
5f33b3bc SS	109	control \|= 2; /* IE */
5f33b3bc SS	110	/* Intel specifies that the prefetch/posting is for disk only */
669a5db4	111	if (adev->class == ATA_DEV_ATA)
5f33b3bc	112	control \|= 4; /* PPE */
669a5db4	113
303f1a76 BZ	114	spin_lock_irqsave(&efar_lock, flags);
303f1a76 BZ	115
a0da1914	116	pci_read_config_word(dev, master_port, &master_data);
669a5db4	117
5f33b3bc	118	/* Set PPE, IE, and TIME as appropriate */
669a5db4	119	if (adev->devno == 0) {
a0da1914 BZ	120	master_data &= 0xCCF0;
	121	master_data \|= control;
	122	master_data \|= (timings[pio][0] << 12) \|
669a5db4 JG	123	(timings[pio][1] << 8);
	124	} else {
	125	int shift = 4 * ap->port_no;
	126	u8 slave_data;
	127
a0da1914 BZ	128	master_data &= 0xFF0F;
a0da1914 BZ	129	master_data \|= (control << 4);
669a5db4	130
1967b7ff	131	/* Slave timing in separate register */
669a5db4	132	pci_read_config_byte(dev, 0x44, &slave_data);
f79ff926	133	slave_data &= ap->port_no ? 0x0F : 0xF0;
669a5db4 JG	134	slave_data \|= ((timings[pio][0] << 2) \| timings[pio][1]) << shift;
	135	pci_write_config_byte(dev, 0x44, slave_data);
	136	}
	137
a0da1914 BZ	138	master_data \|= 0x4000; /* Ensure SITRE is set */
a0da1914 BZ	139	pci_write_config_word(dev, master_port, master_data);
303f1a76 BZ	140
	141	pci_read_config_byte(dev, 0x48, &udma_enable);
	142	udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
	143	pci_write_config_byte(dev, 0x48, udma_enable);
	144	spin_unlock_irqrestore(&efar_lock, flags);
669a5db4 JG	145	}
	146
	147	/**
	148	* efar_set_dmamode - Initialize host controller PATA DMA timings
	149	* @ap: Port whose timings we are configuring
	150	* @adev: Device to program
	151	*
	152	* Set UDMA/MWDMA mode for device, in host controller PCI config space.
	153	*
	154	* LOCKING:
	155	* None (inherited from caller).
	156	*/
	157
	158	static void efar_set_dmamode (struct ata_port ap, struct ata_device adev)
	159	{
	160	struct pci_dev *dev = to_pci_dev(ap->host->dev);
	161	u8 master_port = ap->port_no ? 0x42 : 0x40;
	162	u16 master_data;
	163	u8 speed = adev->dma_mode;
	164	int devid = adev->devno + 2 * ap->port_no;
303f1a76	165	unsigned long flags;
669a5db4 JG	166	u8 udma_enable;
	167
	168	static const /* ISP RTC */
	169	u8 timings[][2] = { { 0, 0 },
	170	{ 0, 0 },
	171	{ 1, 0 },
	172	{ 2, 1 },
	173	{ 2, 3 }, };
	174
303f1a76 BZ	175	spin_lock_irqsave(&efar_lock, flags);
303f1a76 BZ	176
669a5db4 JG	177	pci_read_config_word(dev, master_port, &master_data);
	178	pci_read_config_byte(dev, 0x48, &udma_enable);
	179
	180	if (speed >= XFER_UDMA_0) {
	181	unsigned int udma = adev->dma_mode - XFER_UDMA_0;
	182	u16 udma_timing;
	183
	184	udma_enable \|= (1 << devid);
	185
	186	/* Load the UDMA mode number */
	187	pci_read_config_word(dev, 0x4A, &udma_timing);
	188	udma_timing &= ~(7 << (4 * devid));
	189	udma_timing \|= udma << (4 * devid);
	190	pci_write_config_word(dev, 0x4A, udma_timing);
	191	} else {
	192	/*
	193	* MWDMA is driven by the PIO timings. We must also enable
	194	* IORDY unconditionally along with TIME1. PPE has already
	195	* been set when the PIO timing was set.
	196	*/
	197	unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
	198	unsigned int control;
	199	u8 slave_data;
	200	const unsigned int needed_pio[3] = {
	201	XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
	202	};
	203	int pio = needed_pio[mwdma] - XFER_PIO_0;
	204
	205	control = 3; /* IORDY\|TIME1 */
	206
	207	/* If the drive MWDMA is faster than it can do PIO then
	208	we must force PIO into PIO0 */
	209
	210	if (adev->pio_mode < needed_pio[mwdma])
	211	/* Enable DMA timing only */
	212	control \|= 8; /* PIO cycles in PIO0 */
	213
	214	if (adev->devno) { /* Slave */
	215	master_data &= 0xFF4F; /* Mask out IORDY\|TIME1\|DMAONLY */
	216	master_data \|= control << 4;
	217	pci_read_config_byte(dev, 0x44, &slave_data);
dd221f9c	218	slave_data &= ap->port_no ? 0x0F : 0xF0;
669a5db4 JG	219	/* Load the matching timing */
	220	slave_data \|= ((timings[pio][0] << 2) \| timings[pio][1]) << (ap->port_no ? 4 : 0);
	221	pci_write_config_byte(dev, 0x44, slave_data);
	222	} else { /* Master */
	223	master_data &= 0xCCF4; /* Mask out IORDY\|TIME1\|DMAONLY
	224	and master timing bits */
	225	master_data \|= control;
	226	master_data \|=
	227	(timings[pio][0] << 12) \|
	228	(timings[pio][1] << 8);
	229	}
	230	udma_enable &= ~(1 << devid);
	231	pci_write_config_word(dev, master_port, master_data);
	232	}
	233	pci_write_config_byte(dev, 0x48, udma_enable);
303f1a76	234	spin_unlock_irqrestore(&efar_lock, flags);
669a5db4 JG	235	}
	236
	237	static struct scsi_host_template efar_sht = {
68d1d07b	238	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	239	};
669a5db4 JG	240
029cfd6b TH	241	static struct ata_port_operations efar_ops = {
	242	.inherits = &ata_bmdma_port_ops,
	243	.cable_detect = efar_cable_detect,
669a5db4 JG	244	.set_piomode = efar_set_piomode,
669a5db4 JG	245	.set_dmamode = efar_set_dmamode,
a1efdaba	246	.prereset = efar_pre_reset,
669a5db4 JG	247	};
	248
	249
	250	/**
	251	* efar_init_one - Register EFAR ATA PCI device with kernel services
	252	* @pdev: PCI device to register
	253	* @ent: Entry in efar_pci_tbl matching with @pdev
	254	*
	255	* Called from kernel PCI layer.
	256	*
	257	* LOCKING:
	258	* Inherited from PCI layer (may sleep).
	259	*
	260	* RETURNS:
	261	* Zero on success, or -ERRNO value.
	262	*/
	263
	264	static int efar_init_one (struct pci_dev pdev, const struct pci_device_id ent)
	265	{
1626aeb8	266	static const struct ata_port_info info = {
1d2808fd	267	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98	268	.pio_mask = ATA_PIO4,
82563232	269	.mwdma_mask = ATA_MWDMA12_ONLY,
b2a034cf	270	.udma_mask = ATA_UDMA4,
669a5db4 JG	271	.port_ops = &efar_ops,
669a5db4 JG	272	};
73e2e3d0	273	const struct ata_port_info *ppi[] = { &info, &info };
669a5db4	274
06296a1e	275	ata_print_version_once(&pdev->dev, DRV_VERSION);
669a5db4	276
1c5afdf7 TH	277	return ata_pci_bmdma_init_one(pdev, ppi, &efar_sht, NULL,
1c5afdf7 TH	278	ATA_HOST_PARALLEL_SCAN);
669a5db4 JG	279	}
	280
	281	static const struct pci_device_id efar_pci_tbl[] = {
2d2744fc JG	282	{ PCI_VDEVICE(EFAR, 0x9130), },
2d2744fc JG	283
669a5db4 JG	284	{ } /* terminate list */
	285	};
	286
	287	static struct pci_driver efar_pci_driver = {
	288	.name = DRV_NAME,
	289	.id_table = efar_pci_tbl,
	290	.probe = efar_init_one,
	291	.remove = ata_pci_remove_one,
438ac6d5	292	#ifdef CONFIG_PM
30ced0f0 AC	293	.suspend = ata_pci_device_suspend,
30ced0f0 AC	294	.resume = ata_pci_device_resume,
438ac6d5	295	#endif
669a5db4 JG	296	};
669a5db4 JG	297
2fc75da0	298	module_pci_driver(efar_pci_driver);
669a5db4 JG	299
	300	MODULE_AUTHOR("Alan Cox");
	301	MODULE_DESCRIPTION("SCSI low-level driver for EFAR PIIX clones");
	302	MODULE_LICENSE("GPL");
	303	MODULE_DEVICE_TABLE(pci, efar_pci_tbl);
	304	MODULE_VERSION(DRV_VERSION);