[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / pata_cs5535.c

/*
 * pata-cs5535.c 	- CS5535 PATA for new ATA layer
 *			  (C) 2005-2006 Red Hat Inc
 *			  Alan Cox <alan@lxorguk.ukuu.org.uk>
 *
 * based upon cs5535.c from AMD <Jens.Altmann@amd.com> as cleaned up and
 * made readable and Linux style by Wolfgang Zuleger <wolfgang.zuleger@gmx.de>
 * and Alexander Kiausch <alex.kiausch@t-online.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 * Loosely based on the piix & svwks drivers.
 *
 * Documentation:
 *	Available from AMD web site.
 * TODO
 *	Review errata to see if serializing is necessary
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <asm/msr.h>

#define DRV_NAME	"pata_cs5535"
#define DRV_VERSION	"0.2.12"

/*
 *	The Geode (Aka Athlon GX now) uses an internal MSR based
 *	bus system for control. Demented but there you go.
 */

#define MSR_ATAC_BASE    	0x51300000
#define ATAC_GLD_MSR_CAP 	(MSR_ATAC_BASE+0)
#define ATAC_GLD_MSR_CONFIG    (MSR_ATAC_BASE+0x01)
#define ATAC_GLD_MSR_SMI       (MSR_ATAC_BASE+0x02)
#define ATAC_GLD_MSR_ERROR     (MSR_ATAC_BASE+0x03)
#define ATAC_GLD_MSR_PM        (MSR_ATAC_BASE+0x04)
#define ATAC_GLD_MSR_DIAG      (MSR_ATAC_BASE+0x05)
#define ATAC_IO_BAR            (MSR_ATAC_BASE+0x08)
#define ATAC_RESET             (MSR_ATAC_BASE+0x10)
#define ATAC_CH0D0_PIO         (MSR_ATAC_BASE+0x20)
#define ATAC_CH0D0_DMA         (MSR_ATAC_BASE+0x21)
#define ATAC_CH0D1_PIO         (MSR_ATAC_BASE+0x22)
#define ATAC_CH0D1_DMA         (MSR_ATAC_BASE+0x23)
#define ATAC_PCI_ABRTERR       (MSR_ATAC_BASE+0x24)

#define ATAC_BM0_CMD_PRIM      0x00
#define ATAC_BM0_STS_PRIM      0x02
#define ATAC_BM0_PRD           0x04

#define CS5535_CABLE_DETECT    0x48

/**
 *	cs5535_cable_detect	-	detect cable type
 *	@ap: Port to detect on
 *
 *	Perform cable detection for ATA66 capable cable. Return a libata
 *	cable type.
 */

static int cs5535_cable_detect(struct ata_port *ap)
{
	u8 cable;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	pci_read_config_byte(pdev, CS5535_CABLE_DETECT, &cable);
	if (cable & 1)
		return ATA_CBL_PATA80;
	else
		return ATA_CBL_PATA40;
}

/**
 *	cs5535_set_piomode		-	PIO setup
 *	@ap: ATA interface
 *	@adev: device on the interface
 *
 *	Set our PIO requirements. The CS5535 is pretty clean about all this
 */

static void cs5535_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	static const u16 pio_timings[5] = {
		0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131
	};
	static const u16 pio_cmd_timings[5] = {
		0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131
	};
	u32 reg, dummy;
	struct ata_device *pair = ata_dev_pair(adev);

	int mode = adev->pio_mode - XFER_PIO_0;
	int cmdmode = mode;

	/* Command timing has to be for the lowest of the pair of devices */
	if (pair) {
		int pairmode = pair->pio_mode - XFER_PIO_0;
		cmdmode = min(mode, pairmode);
		/* Write the other drive timing register if it changed */
		if (cmdmode < pairmode)
			wrmsr(ATAC_CH0D0_PIO + 2 * pair->devno,
				pio_cmd_timings[cmdmode] << 16 | pio_timings[pairmode], 0);
	}
	/* Write the drive timing register */
	wrmsr(ATAC_CH0D0_PIO + 2 * adev->devno,
		pio_cmd_timings[cmdmode] << 16 | pio_timings[mode], 0);

	/* Set the PIO "format 1" bit in the DMA timing register */
	rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
	wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg | 0x80000000UL, 0);
}

/**
 *	cs5535_set_dmamode		-	DMA timing setup
 *	@ap: ATA interface
 *	@adev: Device being configured
 *
 */

static void cs5535_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	static const u32 udma_timings[5] = {
		0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061
	};
	static const u32 mwdma_timings[3] = {
		0x7F0FFFF3, 0x7F035352, 0x7F024241
	};
	u32 reg, dummy;
	int mode = adev->dma_mode;

	rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
	reg &= 0x80000000UL;
	if (mode >= XFER_UDMA_0)
		reg |= udma_timings[mode - XFER_UDMA_0];
	else
		reg |= mwdma_timings[mode - XFER_MW_DMA_0];
	wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, 0);
}

static struct scsi_host_template cs5535_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations cs5535_port_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.cable_detect	= cs5535_cable_detect,
	.set_piomode	= cs5535_set_piomode,
	.set_dmamode	= cs5535_set_dmamode,
};

/**
 *	cs5535_init_one		-	Initialise a CS5530
 *	@dev: PCI device
 *	@id: Entry in match table
 *
 *	Install a driver for the newly found CS5530 companion chip. Most of
 *	this is just housekeeping. We have to set the chip up correctly and
 *	turn off various bits of emulation magic.
 */

static int cs5535_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	static const struct ata_port_info info = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = ATA_PIO4,
		.mwdma_mask = ATA_MWDMA2,
		.udma_mask = ATA_UDMA4,
		.port_ops = &cs5535_port_ops
	};
	const struct ata_port_info *ppi[] = { &info, &ata_dummy_port_info };

	return ata_pci_bmdma_init_one(dev, ppi, &cs5535_sht, NULL, 0);
}

static const struct pci_device_id cs5535[] = {
	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_CS5535_IDE), },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5535_IDE), },

	{ },
};

static struct pci_driver cs5535_pci_driver = {
	.name		= DRV_NAME,
	.id_table	= cs5535,
	.probe 		= cs5535_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= ata_pci_device_resume,
#endif
};

module_pci_driver(cs5535_pci_driver);

MODULE_AUTHOR("Alan Cox, Jens Altmann, Wolfgan Zuleger, Alexander Kiausch");
MODULE_DESCRIPTION("low-level driver for the NS/AMD 5535");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, cs5535);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata-cs5535.c - CS5535 PATA for new ATA layer
	3	* (C) 2005-2006 Red Hat Inc
ab771630	4	* Alan Cox <alan@lxorguk.ukuu.org.uk>
669a5db4 JG	5	*
669a5db4 JG	6	* based upon cs5535.c from AMD <Jens.Altmann@amd.com> as cleaned up and
d914e5b7	7	* made readable and Linux style by Wolfgang Zuleger <wolfgang.zuleger@gmx.de>
669a5db4 JG	8	* and Alexander Kiausch <alex.kiausch@t-online.de>
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* Loosely based on the piix & svwks drivers.
	24	*
	25	* Documentation:
	26	* Available from AMD web site.
	27	* TODO
3a4fa0a2	28	* Review errata to see if serializing is necessary
669a5db4 JG	29	*/
	30
	31	#include <linux/kernel.h>
	32	#include <linux/module.h>
	33	#include <linux/pci.h>
	34	#include <linux/init.h>
	35	#include <linux/blkdev.h>
	36	#include <linux/delay.h>
	37	#include <scsi/scsi_host.h>
	38	#include <linux/libata.h>
	39	#include <asm/msr.h>
	40
e9f7cd51	41	#define DRV_NAME "pata_cs5535"
8bc3fc47	42	#define DRV_VERSION "0.2.12"
669a5db4 JG	43
	44	/*
	45	* The Geode (Aka Athlon GX now) uses an internal MSR based
	46	* bus system for control. Demented but there you go.
	47	*/
	48
	49	#define MSR_ATAC_BASE 0x51300000
	50	#define ATAC_GLD_MSR_CAP (MSR_ATAC_BASE+0)
	51	#define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01)
	52	#define ATAC_GLD_MSR_SMI (MSR_ATAC_BASE+0x02)
	53	#define ATAC_GLD_MSR_ERROR (MSR_ATAC_BASE+0x03)
	54	#define ATAC_GLD_MSR_PM (MSR_ATAC_BASE+0x04)
	55	#define ATAC_GLD_MSR_DIAG (MSR_ATAC_BASE+0x05)
	56	#define ATAC_IO_BAR (MSR_ATAC_BASE+0x08)
	57	#define ATAC_RESET (MSR_ATAC_BASE+0x10)
	58	#define ATAC_CH0D0_PIO (MSR_ATAC_BASE+0x20)
	59	#define ATAC_CH0D0_DMA (MSR_ATAC_BASE+0x21)
	60	#define ATAC_CH0D1_PIO (MSR_ATAC_BASE+0x22)
	61	#define ATAC_CH0D1_DMA (MSR_ATAC_BASE+0x23)
	62	#define ATAC_PCI_ABRTERR (MSR_ATAC_BASE+0x24)
	63
	64	#define ATAC_BM0_CMD_PRIM 0x00
	65	#define ATAC_BM0_STS_PRIM 0x02
	66	#define ATAC_BM0_PRD 0x04
	67
	68	#define CS5535_CABLE_DETECT 0x48
	69
669a5db4	70	/**
eb4a2c7f	71	* cs5535_cable_detect - detect cable type
669a5db4 JG	72	* @ap: Port to detect on
	73	*
	74	* Perform cable detection for ATA66 capable cable. Return a libata
	75	* cable type.
	76	*/
	77
eb4a2c7f	78	static int cs5535_cable_detect(struct ata_port *ap)
669a5db4 JG	79	{
	80	u8 cable;
	81	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	82
	83	pci_read_config_byte(pdev, CS5535_CABLE_DETECT, &cable);
	84	if (cable & 1)
eb4a2c7f	85	return ATA_CBL_PATA80;
669a5db4	86	else
eb4a2c7f	87	return ATA_CBL_PATA40;
669a5db4 JG	88	}
	89
	90	/**
	91	* cs5535_set_piomode - PIO setup
	92	* @ap: ATA interface
	93	* @adev: device on the interface
	94	*
	95	* Set our PIO requirements. The CS5535 is pretty clean about all this
	96	*/
	97
	98	static void cs5535_set_piomode(struct ata_port ap, struct ata_device adev)
	99	{
	100	static const u16 pio_timings[5] = {
8ebf4738	101	0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131
669a5db4 JG	102	};
	103	static const u16 pio_cmd_timings[5] = {
	104	0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131
	105	};
	106	u32 reg, dummy;
	107	struct ata_device *pair = ata_dev_pair(adev);
	108
	109	int mode = adev->pio_mode - XFER_PIO_0;
	110	int cmdmode = mode;
	111
	112	/* Command timing has to be for the lowest of the pair of devices */
	113	if (pair) {
	114	int pairmode = pair->pio_mode - XFER_PIO_0;
	115	cmdmode = min(mode, pairmode);
	116	/* Write the other drive timing register if it changed */
	117	if (cmdmode < pairmode)
	118	wrmsr(ATAC_CH0D0_PIO + 2 * pair->devno,
	119	pio_cmd_timings[cmdmode] << 16 \| pio_timings[pairmode], 0);
	120	}
	121	/* Write the drive timing register */
	122	wrmsr(ATAC_CH0D0_PIO + 2 * adev->devno,
	123	pio_cmd_timings[cmdmode] << 16 \| pio_timings[mode], 0);
	124
	125	/* Set the PIO "format 1" bit in the DMA timing register */
	126	rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
	127	wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg \| 0x80000000UL, 0);
	128	}
	129
	130	/**
	131	* cs5535_set_dmamode - DMA timing setup
	132	* @ap: ATA interface
	133	* @adev: Device being configured
	134	*
	135	*/
	136
	137	static void cs5535_set_dmamode(struct ata_port ap, struct ata_device adev)
	138	{
	139	static const u32 udma_timings[5] = {
	140	0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061
	141	};
	142	static const u32 mwdma_timings[3] = {
	143	0x7F0FFFF3, 0x7F035352, 0x7F024241
	144	};
	145	u32 reg, dummy;
	146	int mode = adev->dma_mode;
	147
	148	rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
	149	reg &= 0x80000000UL;
	150	if (mode >= XFER_UDMA_0)
	151	reg \|= udma_timings[mode - XFER_UDMA_0];
	152	else
	153	reg \|= mwdma_timings[mode - XFER_MW_DMA_0];
	154	wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, 0);
	155	}
	156
	157	static struct scsi_host_template cs5535_sht = {
68d1d07b	158	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	159	};
	160
	161	static struct ata_port_operations cs5535_port_ops = {
029cfd6b TH	162	.inherits = &ata_bmdma_port_ops,
029cfd6b TH	163	.cable_detect = cs5535_cable_detect,
669a5db4 JG	164	.set_piomode = cs5535_set_piomode,
669a5db4 JG	165	.set_dmamode = cs5535_set_dmamode,
669a5db4 JG	166	};
	167
	168	/**
	169	* cs5535_init_one - Initialise a CS5530
	170	* @dev: PCI device
	171	* @id: Entry in match table
	172	*
	173	* Install a driver for the newly found CS5530 companion chip. Most of
	174	* this is just housekeeping. We have to set the chip up correctly and
	175	* turn off various bits of emulation magic.
	176	*/
	177
	178	static int cs5535_init_one(struct pci_dev dev, const struct pci_device_id id)
	179	{
1626aeb8	180	static const struct ata_port_info info = {
1d2808fd	181	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	182	.pio_mask = ATA_PIO4,
14bdef98 EIB	183	.mwdma_mask = ATA_MWDMA2,
bf6263a8	184	.udma_mask = ATA_UDMA4,
669a5db4 JG	185	.port_ops = &cs5535_port_ops
669a5db4 JG	186	};
1626aeb8	187	const struct ata_port_info *ppi[] = { &info, &ata_dummy_port_info };
669a5db4	188
1c5afdf7	189	return ata_pci_bmdma_init_one(dev, ppi, &cs5535_sht, NULL, 0);
669a5db4 JG	190	}
669a5db4 JG	191
2d2744fc	192	static const struct pci_device_id cs5535[] = {
02cb009b OS	193	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_CS5535_IDE), },
02cb009b OS	194	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5535_IDE), },
2d2744fc JG	195
2d2744fc JG	196	{ },
669a5db4 JG	197	};
	198
	199	static struct pci_driver cs5535_pci_driver = {
	200	.name = DRV_NAME,
	201	.id_table = cs5535,
	202	.probe = cs5535_init_one,
3ac551a6	203	.remove = ata_pci_remove_one,
438ac6d5	204	#ifdef CONFIG_PM
30ced0f0 AC	205	.suspend = ata_pci_device_suspend,
30ced0f0 AC	206	.resume = ata_pci_device_resume,
438ac6d5	207	#endif
669a5db4 JG	208	};
669a5db4 JG	209
2fc75da0	210	module_pci_driver(cs5535_pci_driver);
669a5db4	211
669a5db4	212	MODULE_AUTHOR("Alan Cox, Jens Altmann, Wolfgan Zuleger, Alexander Kiausch");
e9f7cd51	213	MODULE_DESCRIPTION("low-level driver for the NS/AMD 5535");
669a5db4 JG	214	MODULE_LICENSE("GPL");
	215	MODULE_DEVICE_TABLE(pci, cs5535);
	216	MODULE_VERSION(DRV_VERSION);