[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / pata_cs5530.c

/*
 * pata-cs5530.c 	- CS5530 PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *
 * based upon cs5530.c by Mark Lord.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 * Loosely based on the piix & svwks drivers.
 *
 * Documentation:
 *	Available from AMD web site.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <linux/dmi.h>

#define DRV_NAME	"pata_cs5530"
#define DRV_VERSION	"0.7.4"

static void __iomem *cs5530_port_base(struct ata_port *ap)
{
	unsigned long bmdma = (unsigned long)ap->ioaddr.bmdma_addr;

	return (void __iomem *)((bmdma & ~0x0F) + 0x20 + 0x10 * ap->port_no);
}

/**
 *	cs5530_set_piomode		-	PIO setup
 *	@ap: ATA interface
 *	@adev: device on the interface
 *
 *	Set our PIO requirements. This is fairly simple on the CS5530
 *	chips.
 */

static void cs5530_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	static const unsigned int cs5530_pio_timings[2][5] = {
		{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
		{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
	};
	void __iomem *base = cs5530_port_base(ap);
	u32 tuning;
	int format;

	/* Find out which table to use */
	tuning = ioread32(base + 0x04);
	format = (tuning & 0x80000000UL) ? 1 : 0;

	/* Now load the right timing register */
	if (adev->devno)
		base += 0x08;

	iowrite32(cs5530_pio_timings[format][adev->pio_mode - XFER_PIO_0], base);
}

/**
 *	cs5530_set_dmamode		-	DMA timing setup
 *	@ap: ATA interface
 *	@adev: Device being configured
 *
 *	We cannot mix MWDMA and UDMA without reloading timings each switch
 *	master to slave. We track the last DMA setup in order to minimise
 *	reloads.
 */

static void cs5530_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	void __iomem *base = cs5530_port_base(ap);
	u32 tuning, timing = 0;
	u8 reg;

	/* Find out which table to use */
	tuning = ioread32(base + 0x04);

	switch(adev->dma_mode) {
		case XFER_UDMA_0:
			timing  = 0x00921250;break;
		case XFER_UDMA_1:
			timing  = 0x00911140;break;
		case XFER_UDMA_2:
			timing  = 0x00911030;break;
		case XFER_MW_DMA_0:
			timing  = 0x00077771;break;
		case XFER_MW_DMA_1:
			timing  = 0x00012121;break;
		case XFER_MW_DMA_2:
			timing  = 0x00002020;break;
		default:
			BUG();
	}
	/* Merge in the PIO format bit */
	timing |= (tuning & 0x80000000UL);
	if (adev->devno == 0) /* Master */
		iowrite32(timing, base + 0x04);
	else {
		if (timing & 0x00100000)
			tuning |= 0x00100000;	/* UDMA for both */
		else
			tuning &= ~0x00100000;	/* MWDMA for both */
		iowrite32(tuning, base + 0x04);
		iowrite32(timing, base + 0x0C);
	}

	/* Set the DMA capable bit in the BMDMA area */
	reg = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
	reg |= (1 << (5 + adev->devno));
	iowrite8(reg, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);

	/* Remember the last DMA setup we did */

	ap->private_data = adev;
}

/**
 *	cs5530_qc_issue		-	command issue
 *	@qc: command pending
 *
 *	Called when the libata layer is about to issue a command. We wrap
 *	this interface so that we can load the correct ATA timings if
 *	necessary.  Specifically we have a problem that there is only
 *	one MWDMA/UDMA bit.
 */

static unsigned int cs5530_qc_issue(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct ata_device *adev = qc->dev;
	struct ata_device *prev = ap->private_data;

	/* See if the DMA settings could be wrong */
	if (ata_dma_enabled(adev) && adev != prev && prev != NULL) {
		/* Maybe, but do the channels match MWDMA/UDMA ? */
		if ((ata_using_udma(adev) && !ata_using_udma(prev)) ||
		    (ata_using_udma(prev) && !ata_using_udma(adev)))
		    	/* Switch the mode bits */
		    	cs5530_set_dmamode(ap, adev);
	}

	return ata_bmdma_qc_issue(qc);
}

static struct scsi_host_template cs5530_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
	.sg_tablesize	= LIBATA_DUMB_MAX_PRD,
};

static struct ata_port_operations cs5530_port_ops = {
	.inherits	= &ata_bmdma_port_ops,

	.qc_prep 	= ata_bmdma_dumb_qc_prep,
	.qc_issue	= cs5530_qc_issue,

	.cable_detect	= ata_cable_40wire,
	.set_piomode	= cs5530_set_piomode,
	.set_dmamode	= cs5530_set_dmamode,
};

static const struct dmi_system_id palmax_dmi_table[] = {
	{
		.ident = "Palmax PD1100",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Cyrix"),
			DMI_MATCH(DMI_PRODUCT_NAME, "Caddis"),
		},
	},
	{ }
};

static int cs5530_is_palmax(void)
{
	if (dmi_check_system(palmax_dmi_table)) {
		printk(KERN_INFO "Palmax PD1100: Disabling DMA on docking port.\n");
		return 1;
	}
	return 0;
}


/**
 *	cs5530_init_chip	-	Chipset init
 *
 *	Perform the chip initialisation work that is shared between both
 *	setup and resume paths
 */

static int cs5530_init_chip(void)
{
	struct pci_dev *master_0 = NULL, *cs5530_0 = NULL, *dev = NULL;

	while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
		switch (dev->device) {
			case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
				master_0 = pci_dev_get(dev);
				break;
			case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
				cs5530_0 = pci_dev_get(dev);
				break;
		}
	}
	if (!master_0) {
		printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n");
		goto fail_put;
	}
	if (!cs5530_0) {
		printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n");
		goto fail_put;
	}

	pci_set_master(cs5530_0);
	pci_try_set_mwi(cs5530_0);

	/*
	 * Set PCI CacheLineSize to 16-bytes:
	 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
	 *
	 * Note: This value is constant because the 5530 is only a Geode companion
	 */

	pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);

	/*
	 * Disable trapping of UDMA register accesses (Win98 hack):
	 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
	 */

	pci_write_config_word(cs5530_0, 0xd0, 0x5006);

	/*
	 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
	 * The other settings are what is necessary to get the register
	 * into a sane state for IDE DMA operation.
	 */

	pci_write_config_byte(master_0, 0x40, 0x1e);

	/*
	 * Set max PCI burst size (16-bytes seems to work best):
	 *	   16bytes: set bit-1 at 0x41 (reg value of 0x16)
	 *	all others: clear bit-1 at 0x41, and do:
	 *	  128bytes: OR 0x00 at 0x41
	 *	  256bytes: OR 0x04 at 0x41
	 *	  512bytes: OR 0x08 at 0x41
	 *	 1024bytes: OR 0x0c at 0x41
	 */

	pci_write_config_byte(master_0, 0x41, 0x14);

	/*
	 * These settings are necessary to get the chip
	 * into a sane state for IDE DMA operation.
	 */

	pci_write_config_byte(master_0, 0x42, 0x00);
	pci_write_config_byte(master_0, 0x43, 0xc1);

	pci_dev_put(master_0);
	pci_dev_put(cs5530_0);
	return 0;
fail_put:
	if (master_0)
		pci_dev_put(master_0);
	if (cs5530_0)
		pci_dev_put(cs5530_0);
	return -ENODEV;
}

/**
 *	cs5530_init_one		-	Initialise a CS5530
 *	@dev: PCI device
 *	@id: Entry in match table
 *
 *	Install a driver for the newly found CS5530 companion chip. Most of
 *	this is just housekeeping. We have to set the chip up correctly and
 *	turn off various bits of emulation magic.
 */

static int cs5530_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const struct ata_port_info info = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = ATA_PIO4,
		.mwdma_mask = ATA_MWDMA2,
		.udma_mask = ATA_UDMA2,
		.port_ops = &cs5530_port_ops
	};
	/* The docking connector doesn't do UDMA, and it seems not MWDMA */
	static const struct ata_port_info info_palmax_secondary = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = ATA_PIO4,
		.port_ops = &cs5530_port_ops
	};
	const struct ata_port_info *ppi[] = { &info, NULL };
	int rc;

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/* Chip initialisation */
	if (cs5530_init_chip())
		return -ENODEV;

	if (cs5530_is_palmax())
		ppi[1] = &info_palmax_secondary;

	/* Now kick off ATA set up */
	return ata_pci_bmdma_init_one(pdev, ppi, &cs5530_sht, NULL, 0);
}

#ifdef CONFIG_PM
static int cs5530_reinit_one(struct pci_dev *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	int rc;

	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;

	/* If we fail on resume we are doomed */
	if (cs5530_init_chip())
		return -EIO;

	ata_host_resume(host);
	return 0;
}
#endif /* CONFIG_PM */

static const struct pci_device_id cs5530[] = {
	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), },

	{ },
};

static struct pci_driver cs5530_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= cs5530,
	.probe 		= cs5530_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= cs5530_reinit_one,
#endif
};

module_pci_driver(cs5530_pci_driver);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for the Cyrix/NS/AMD 5530");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, cs5530);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata-cs5530.c - CS5530 PATA for new ATA layer
	3	* (C) 2005 Red Hat Inc
669a5db4 JG	4	*
	5	* based upon cs5530.c by Mark Lord.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*
	20	* Loosely based on the piix & svwks drivers.
	21	*
	22	* Documentation:
	23	* Available from AMD web site.
	24	*/
	25
	26	#include <linux/kernel.h>
	27	#include <linux/module.h>
	28	#include <linux/pci.h>
	29	#include <linux/init.h>
	30	#include <linux/blkdev.h>
	31	#include <linux/delay.h>
	32	#include <scsi/scsi_host.h>
	33	#include <linux/libata.h>
	34	#include <linux/dmi.h>
	35
	36	#define DRV_NAME "pata_cs5530"
2a3103ce	37	#define DRV_VERSION "0.7.4"
669a5db4	38
0d5ff566 TH	39	static void __iomem cs5530_port_base(struct ata_port ap)
	40	{
	41	unsigned long bmdma = (unsigned long)ap->ioaddr.bmdma_addr;
	42
	43	return (void __iomem )((bmdma & ~0x0F) + 0x20 + 0x10 ap->port_no);
	44	}
	45
669a5db4 JG	46	/**
	47	* cs5530_set_piomode - PIO setup
	48	* @ap: ATA interface
	49	* @adev: device on the interface
	50	*
	51	* Set our PIO requirements. This is fairly simple on the CS5530
	52	* chips.
	53	*/
	54
	55	static void cs5530_set_piomode(struct ata_port ap, struct ata_device adev)
	56	{
	57	static const unsigned int cs5530_pio_timings[2][5] = {
	58	{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
	59	{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
	60	};
0d5ff566	61	void __iomem *base = cs5530_port_base(ap);
669a5db4 JG	62	u32 tuning;
	63	int format;
	64
	65	/* Find out which table to use */
0d5ff566	66	tuning = ioread32(base + 0x04);
669a5db4 JG	67	format = (tuning & 0x80000000UL) ? 1 : 0;
	68
	69	/* Now load the right timing register */
	70	if (adev->devno)
	71	base += 0x08;
	72
0d5ff566	73	iowrite32(cs5530_pio_timings[format][adev->pio_mode - XFER_PIO_0], base);
669a5db4 JG	74	}
	75
	76	/**
	77	* cs5530_set_dmamode - DMA timing setup
	78	* @ap: ATA interface
	79	* @adev: Device being configured
	80	*
	81	* We cannot mix MWDMA and UDMA without reloading timings each switch
	82	* master to slave. We track the last DMA setup in order to minimise
	83	* reloads.
	84	*/
	85
	86	static void cs5530_set_dmamode(struct ata_port ap, struct ata_device adev)
	87	{
0d5ff566	88	void __iomem *base = cs5530_port_base(ap);
669a5db4 JG	89	u32 tuning, timing = 0;
	90	u8 reg;
	91
	92	/* Find out which table to use */
0d5ff566	93	tuning = ioread32(base + 0x04);
669a5db4 JG	94
	95	switch(adev->dma_mode) {
	96	case XFER_UDMA_0:
	97	timing = 0x00921250;break;
	98	case XFER_UDMA_1:
	99	timing = 0x00911140;break;
	100	case XFER_UDMA_2:
	101	timing = 0x00911030;break;
	102	case XFER_MW_DMA_0:
	103	timing = 0x00077771;break;
	104	case XFER_MW_DMA_1:
	105	timing = 0x00012121;break;
	106	case XFER_MW_DMA_2:
	107	timing = 0x00002020;break;
	108	default:
	109	BUG();
	110	}
	111	/* Merge in the PIO format bit */
	112	timing \|= (tuning & 0x80000000UL);
	113	if (adev->devno == 0) /* Master */
0d5ff566	114	iowrite32(timing, base + 0x04);
669a5db4 JG	115	else {
	116	if (timing & 0x00100000)
	117	tuning \|= 0x00100000; /* UDMA for both */
	118	else
	119	tuning &= ~0x00100000; /* MWDMA for both */
0d5ff566 TH	120	iowrite32(tuning, base + 0x04);
0d5ff566 TH	121	iowrite32(timing, base + 0x0C);
669a5db4 JG	122	}
	123
	124	/* Set the DMA capable bit in the BMDMA area */
0d5ff566	125	reg = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
669a5db4	126	reg \|= (1 << (5 + adev->devno));
0d5ff566	127	iowrite8(reg, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
669a5db4 JG	128
	129	/* Remember the last DMA setup we did */
	130
	131	ap->private_data = adev;
	132	}
	133
	134	/**
9363c382	135	* cs5530_qc_issue - command issue
669a5db4 JG	136	* @qc: command pending
	137	*
	138	* Called when the libata layer is about to issue a command. We wrap
	139	* this interface so that we can load the correct ATA timings if
3a4fa0a2	140	* necessary. Specifically we have a problem that there is only
669a5db4 JG	141	* one MWDMA/UDMA bit.
	142	*/
	143
9363c382	144	static unsigned int cs5530_qc_issue(struct ata_queued_cmd *qc)
669a5db4 JG	145	{
	146	struct ata_port *ap = qc->ap;
	147	struct ata_device *adev = qc->dev;
	148	struct ata_device *prev = ap->private_data;
	149
	150	/* See if the DMA settings could be wrong */
b15b3eba	151	if (ata_dma_enabled(adev) && adev != prev && prev != NULL) {
669a5db4	152	/* Maybe, but do the channels match MWDMA/UDMA ? */
b15b3eba AC	153	if ((ata_using_udma(adev) && !ata_using_udma(prev)) \|\|
b15b3eba AC	154	(ata_using_udma(prev) && !ata_using_udma(adev)))
669a5db4 JG	155	/* Switch the mode bits */
	156	cs5530_set_dmamode(ap, adev);
	157	}
	158
360ff783	159	return ata_bmdma_qc_issue(qc);
669a5db4 JG	160	}
669a5db4 JG	161
669a5db4	162	static struct scsi_host_template cs5530_sht = {
68d1d07b TH	163	ATA_BMDMA_SHT(DRV_NAME),
68d1d07b TH	164	.sg_tablesize = LIBATA_DUMB_MAX_PRD,
669a5db4 JG	165	};
	166
	167	static struct ata_port_operations cs5530_port_ops = {
029cfd6b	168	.inherits = &ata_bmdma_port_ops,
669a5db4	169
f47451c4	170	.qc_prep = ata_bmdma_dumb_qc_prep,
9363c382	171	.qc_issue = cs5530_qc_issue,
bda30288	172
029cfd6b TH	173	.cable_detect = ata_cable_40wire,
	174	.set_piomode = cs5530_set_piomode,
	175	.set_dmamode = cs5530_set_dmamode,
669a5db4 JG	176	};
669a5db4 JG	177
1855256c	178	static const struct dmi_system_id palmax_dmi_table[] = {
669a5db4 JG	179	{
	180	.ident = "Palmax PD1100",
	181	.matches = {
	182	DMI_MATCH(DMI_SYS_VENDOR, "Cyrix"),
	183	DMI_MATCH(DMI_PRODUCT_NAME, "Caddis"),
	184	},
	185	},
	186	{ }
	187	};
	188
	189	static int cs5530_is_palmax(void)
	190	{
	191	if (dmi_check_system(palmax_dmi_table)) {
	192	printk(KERN_INFO "Palmax PD1100: Disabling DMA on docking port.\n");
	193	return 1;
	194	}
	195	return 0;
	196	}
	197
f7e37ba8	198
669a5db4	199	/**
f7e37ba8	200	* cs5530_init_chip - Chipset init
669a5db4	201	*
f7e37ba8 AC	202	* Perform the chip initialisation work that is shared between both
f7e37ba8 AC	203	* setup and resume paths
669a5db4	204	*/
f20b16ff	205
f7e37ba8	206	static int cs5530_init_chip(void)
669a5db4	207	{
f7e37ba8	208	struct pci_dev master_0 = NULL, cs5530_0 = NULL, *dev = NULL;
669a5db4	209
669a5db4 JG	210	while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
	211	switch (dev->device) {
	212	case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
	213	master_0 = pci_dev_get(dev);
	214	break;
	215	case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
	216	cs5530_0 = pci_dev_get(dev);
	217	break;
	218	}
	219	}
	220	if (!master_0) {
	221	printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n");
	222	goto fail_put;
	223	}
	224	if (!cs5530_0) {
	225	printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n");
	226	goto fail_put;
	227	}
	228
	229	pci_set_master(cs5530_0);
694625c0	230	pci_try_set_mwi(cs5530_0);
669a5db4 JG	231
	232	/*
	233	* Set PCI CacheLineSize to 16-bytes:
	234	* --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
	235	*
	236	* Note: This value is constant because the 5530 is only a Geode companion
	237	*/
	238
	239	pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
	240
	241	/*
	242	* Disable trapping of UDMA register accesses (Win98 hack):
	243	* --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
	244	*/
	245
	246	pci_write_config_word(cs5530_0, 0xd0, 0x5006);
	247
	248	/*
	249	* Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
	250	* The other settings are what is necessary to get the register
	251	* into a sane state for IDE DMA operation.
	252	*/
	253
	254	pci_write_config_byte(master_0, 0x40, 0x1e);
	255
	256	/*
	257	* Set max PCI burst size (16-bytes seems to work best):
	258	* 16bytes: set bit-1 at 0x41 (reg value of 0x16)
	259	* all others: clear bit-1 at 0x41, and do:
	260	* 128bytes: OR 0x00 at 0x41
	261	* 256bytes: OR 0x04 at 0x41
	262	* 512bytes: OR 0x08 at 0x41
	263	* 1024bytes: OR 0x0c at 0x41
	264	*/
	265
	266	pci_write_config_byte(master_0, 0x41, 0x14);
	267
	268	/*
	269	* These settings are necessary to get the chip
	270	* into a sane state for IDE DMA operation.
	271	*/
	272
	273	pci_write_config_byte(master_0, 0x42, 0x00);
	274	pci_write_config_byte(master_0, 0x43, 0xc1);
	275
	276	pci_dev_put(master_0);
	277	pci_dev_put(cs5530_0);
f7e37ba8	278	return 0;
669a5db4 JG	279	fail_put:
	280	if (master_0)
	281	pci_dev_put(master_0);
	282	if (cs5530_0)
	283	pci_dev_put(cs5530_0);
	284	return -ENODEV;
	285	}
	286
f7e37ba8 AC	287	/**
	288	* cs5530_init_one - Initialise a CS5530
	289	* @dev: PCI device
	290	* @id: Entry in match table
	291	*
	292	* Install a driver for the newly found CS5530 companion chip. Most of
	293	* this is just housekeeping. We have to set the chip up correctly and
	294	* turn off various bits of emulation magic.
	295	*/
	296
	297	static int cs5530_init_one(struct pci_dev pdev, const struct pci_device_id id)
	298	{
1626aeb8	299	static const struct ata_port_info info = {
1d2808fd	300	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	301	.pio_mask = ATA_PIO4,
	302	.mwdma_mask = ATA_MWDMA2,
	303	.udma_mask = ATA_UDMA2,
f7e37ba8 AC	304	.port_ops = &cs5530_port_ops
	305	};
	306	/* The docking connector doesn't do UDMA, and it seems not MWDMA */
1626aeb8	307	static const struct ata_port_info info_palmax_secondary = {
1d2808fd	308	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98	309	.pio_mask = ATA_PIO4,
f7e37ba8 AC	310	.port_ops = &cs5530_port_ops
f7e37ba8 AC	311	};
1626aeb8	312	const struct ata_port_info *ppi[] = { &info, NULL };
f08048e9 TH	313	int rc;
	314
	315	rc = pcim_enable_device(pdev);
	316	if (rc)
	317	return rc;
f20b16ff	318
f7e37ba8 AC	319	/* Chip initialisation */
	320	if (cs5530_init_chip())
	321	return -ENODEV;
f20b16ff	322
f7e37ba8	323	if (cs5530_is_palmax())
1626aeb8	324	ppi[1] = &info_palmax_secondary;
f7e37ba8 AC	325
f7e37ba8 AC	326	/* Now kick off ATA set up */
1c5afdf7	327	return ata_pci_bmdma_init_one(pdev, ppi, &cs5530_sht, NULL, 0);
f7e37ba8 AC	328	}
f7e37ba8 AC	329
438ac6d5	330	#ifdef CONFIG_PM
f7e37ba8 AC	331	static int cs5530_reinit_one(struct pci_dev *pdev)
f7e37ba8 AC	332	{
f08048e9 TH	333	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	334	int rc;
	335
	336	rc = ata_pci_device_do_resume(pdev);
	337	if (rc)
	338	return rc;
	339
f7e37ba8	340	/* If we fail on resume we are doomed */
0153260a	341	if (cs5530_init_chip())
f08048e9 TH	342	return -EIO;
	343
	344	ata_host_resume(host);
	345	return 0;
f7e37ba8	346	}
438ac6d5	347	#endif /* CONFIG_PM */
f20b16ff	348
2d2744fc JG	349	static const struct pci_device_id cs5530[] = {
	350	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), },
	351
	352	{ },
669a5db4 JG	353	};
	354
	355	static struct pci_driver cs5530_pci_driver = {
2d2744fc	356	.name = DRV_NAME,
669a5db4 JG	357	.id_table = cs5530,
669a5db4 JG	358	.probe = cs5530_init_one,
f7e37ba8	359	.remove = ata_pci_remove_one,
438ac6d5	360	#ifdef CONFIG_PM
f7e37ba8 AC	361	.suspend = ata_pci_device_suspend,
f7e37ba8 AC	362	.resume = cs5530_reinit_one,
438ac6d5	363	#endif
669a5db4 JG	364	};
669a5db4 JG	365
2fc75da0	366	module_pci_driver(cs5530_pci_driver);
669a5db4	367
669a5db4 JG	368	MODULE_AUTHOR("Alan Cox");
	369	MODULE_DESCRIPTION("low-level driver for the Cyrix/NS/AMD 5530");
	370	MODULE_LICENSE("GPL");
	371	MODULE_DEVICE_TABLE(pci, cs5530);
	372	MODULE_VERSION(DRV_VERSION);