[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / pata_at91.c

/*
 * PATA driver for AT91SAM9260 Static Memory Controller
 * with CompactFlash interface in True IDE mode
 *
 * Copyright (C) 2009 Matyukevich Sergey
 *               2011 Igor Plyatov
 *
 * Based on:
 *      * generic platform driver by Paul Mundt: drivers/ata/pata_platform.c
 *      * pata_at32 driver by Kristoffer Nyborg Gregertsen
 *      * at91_ide driver by Stanislaw Gruszka
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2
 * as published by the Free Software Foundation.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/gfp.h>
#include <scsi/scsi_host.h>
#include <linux/ata.h>
#include <linux/clk.h>
#include <linux/libata.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <linux/platform_data/atmel.h>

#include <mach/at91sam9_smc.h>
#include <asm/gpio.h>

#define DRV_NAME		"pata_at91"
#define DRV_VERSION		"0.3"

#define CF_IDE_OFFSET		0x00c00000
#define CF_ALT_IDE_OFFSET	0x00e00000
#define CF_IDE_RES_SIZE		0x08
#define CS_PULSE_MAXIMUM	319
#define ER_SMC_CALC		1
#define ER_SMC_RECALC		2

struct at91_ide_info {
	unsigned long mode;
	unsigned int cs;
	struct clk *mck;
	void __iomem *ide_addr;
	void __iomem *alt_addr;
};

/**
 * struct smc_range - range of valid values for SMC register.
 */
struct smc_range {
	int min;
	int max;
};

/**
 * adjust_smc_value - adjust value for one of SMC registers.
 * @value: adjusted value
 * @range: array of SMC ranges with valid values
 * @size: SMC ranges array size
 *
 * This returns the difference between input and output value or negative
 * in case of invalid input value.
 * If negative returned, then output value = maximal possible from ranges.
 */
static int adjust_smc_value(int *value, struct smc_range *range, int size)
{
	int maximum = (range + size - 1)->max;
	int remainder;

	do {
		if (*value < range->min) {
			remainder = range->min - *value;
			*value = range->min; /* nearest valid value */
			return remainder;
		} else if ((range->min <= *value) && (*value <= range->max))
			return 0;

		range++;
	} while (--size);
	*value = maximum;

	return -1; /* invalid value */
}

/**
 * calc_smc_vals - calculate SMC register values
 * @dev: ATA device
 * @setup: SMC_SETUP register value
 * @pulse: SMC_PULSE register value
 * @cycle: SMC_CYCLE register value
 *
 * This returns negative in case of invalid values for SMC registers:
 * -ER_SMC_RECALC - recalculation required for SMC values,
 * -ER_SMC_CALC - calculation failed (invalid input values).
 *
 * SMC use special coding scheme, see "Coding and Range of Timing
 * Parameters" table from AT91SAM9 datasheets.
 *
 *	SMC_SETUP = 128*setup[5] + setup[4:0]
 *	SMC_PULSE = 256*pulse[6] + pulse[5:0]
 *	SMC_CYCLE = 256*cycle[8:7] + cycle[6:0]
 */
static int calc_smc_vals(struct device *dev,
		int *setup, int *pulse, int *cycle, int *cs_pulse)
{
	int ret_val;
	int err = 0;
	struct smc_range range_setup[] = {	/* SMC_SETUP valid values */
		{.min = 0,	.max = 31},	/* first  range */
		{.min = 128,	.max = 159}	/* second range */
	};
	struct smc_range range_pulse[] = {	/* SMC_PULSE valid values */
		{.min = 0,	.max = 63},	/* first  range */
		{.min = 256,	.max = 319}	/* second range */
	};
	struct smc_range range_cycle[] = {	/* SMC_CYCLE valid values */
		{.min = 0,	.max = 127},	/* first  range */
		{.min = 256,	.max = 383},	/* second range */
		{.min = 512,	.max = 639},	/* third  range */
		{.min = 768,	.max = 895}	/* fourth range */
	};

	ret_val = adjust_smc_value(setup, range_setup, ARRAY_SIZE(range_setup));
	if (ret_val < 0)
		dev_warn(dev, "maximal SMC Setup value\n");
	else
		*cycle += ret_val;

	ret_val = adjust_smc_value(pulse, range_pulse, ARRAY_SIZE(range_pulse));
	if (ret_val < 0)
		dev_warn(dev, "maximal SMC Pulse value\n");
	else
		*cycle += ret_val;

	ret_val = adjust_smc_value(cycle, range_cycle, ARRAY_SIZE(range_cycle));
	if (ret_val < 0)
		dev_warn(dev, "maximal SMC Cycle value\n");

	*cs_pulse = *cycle;
	if (*cs_pulse > CS_PULSE_MAXIMUM) {
		dev_err(dev, "unable to calculate valid SMC settings\n");
		return -ER_SMC_CALC;
	}

	ret_val = adjust_smc_value(cs_pulse, range_pulse,
					ARRAY_SIZE(range_pulse));
	if (ret_val < 0) {
		dev_warn(dev, "maximal SMC CS Pulse value\n");
	} else if (ret_val != 0) {
		*cycle = *cs_pulse;
		dev_warn(dev, "SMC Cycle extended\n");
		err = -ER_SMC_RECALC;
	}

	return err;
}

/**
 * to_smc_format - convert values into SMC format
 * @setup: SETUP value of SMC Setup Register
 * @pulse: PULSE value of SMC Pulse Register
 * @cycle: CYCLE value of SMC Cycle Register
 * @cs_pulse: NCS_PULSE value of SMC Pulse Register
 */
static void to_smc_format(int *setup, int *pulse, int *cycle, int *cs_pulse)
{
	*setup = (*setup & 0x1f) | ((*setup & 0x80) >> 2);
	*pulse = (*pulse & 0x3f) | ((*pulse & 0x100) >> 2);
	*cycle = (*cycle & 0x7f) | ((*cycle & 0x300) >> 1);
	*cs_pulse = (*cs_pulse & 0x3f) | ((*cs_pulse & 0x100) >> 2);
}

static unsigned long calc_mck_cycles(unsigned long ns, unsigned long mck_hz)
{
	unsigned long mul;

	/*
	* cycles = x [nsec] * f [Hz] / 10^9 [ns in sec] =
	*     x * (f / 1_000_000_000) =
	*     x * ((f * 65536) / 1_000_000_000) / 65536 =
	*     x * (((f / 10_000) * 65536) / 100_000) / 65536 =
	*/

	mul = (mck_hz / 10000) << 16;
	mul /= 100000;

	return (ns * mul + 65536) >> 16;    /* rounding */
}

/**
 * set_smc_timing - SMC timings setup.
 * @dev: device
 * @info: AT91 IDE info
 * @ata: ATA timings
 *
 * Its assumed that write timings are same as read timings,
 * cs_setup = 0 and cs_pulse = cycle.
 */
static void set_smc_timing(struct device *dev, struct ata_device *adev,
		struct at91_ide_info *info, const struct ata_timing *ata)
{
	int ret = 0;
	int use_iordy;
	struct sam9_smc_config smc;
	unsigned int t6z;         /* data tristate time in ns */
	unsigned int cycle;       /* SMC Cycle width in MCK ticks */
	unsigned int setup;       /* SMC Setup width in MCK ticks */
	unsigned int pulse;       /* CFIOR and CFIOW pulse width in MCK ticks */
	unsigned int cs_pulse;    /* CS4 or CS5 pulse width in MCK ticks*/
	unsigned int tdf_cycles;  /* SMC TDF MCK ticks */
	unsigned long mck_hz;     /* MCK frequency in Hz */

	t6z = (ata->mode < XFER_PIO_5) ? 30 : 20;
	mck_hz = clk_get_rate(info->mck);
	cycle = calc_mck_cycles(ata->cyc8b, mck_hz);
	setup = calc_mck_cycles(ata->setup, mck_hz);
	pulse = calc_mck_cycles(ata->act8b, mck_hz);
	tdf_cycles = calc_mck_cycles(t6z, mck_hz);

	do {
		ret = calc_smc_vals(dev, &setup, &pulse, &cycle, &cs_pulse);
	} while (ret == -ER_SMC_RECALC);

	if (ret == -ER_SMC_CALC)
		dev_err(dev, "Interface may not operate correctly\n");

	dev_dbg(dev, "SMC Setup=%u, Pulse=%u, Cycle=%u, CS Pulse=%u\n",
		setup, pulse, cycle, cs_pulse);
	to_smc_format(&setup, &pulse, &cycle, &cs_pulse);
	/* disable or enable waiting for IORDY signal */
	use_iordy = ata_pio_need_iordy(adev);
	if (use_iordy)
		info->mode |= AT91_SMC_EXNWMODE_READY;

	if (tdf_cycles > 15) {
		tdf_cycles = 15;
		dev_warn(dev, "maximal SMC TDF Cycles value\n");
	}

	dev_dbg(dev, "Use IORDY=%u, TDF Cycles=%u\n", use_iordy, tdf_cycles);

	/* SMC Setup Register */
	smc.nwe_setup = smc.nrd_setup = setup;
	smc.ncs_write_setup = smc.ncs_read_setup = 0;
	/* SMC Pulse Register */
	smc.nwe_pulse = smc.nrd_pulse = pulse;
	smc.ncs_write_pulse = smc.ncs_read_pulse = cs_pulse;
	/* SMC Cycle Register */
	smc.write_cycle = smc.read_cycle = cycle;
	/* SMC Mode Register*/
	smc.tdf_cycles = tdf_cycles;
	smc.mode = info->mode;

	sam9_smc_configure(0, info->cs, &smc);
}

static void pata_at91_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	struct at91_ide_info *info = ap->host->private_data;
	struct ata_timing timing;
	int ret;

	/* Compute ATA timing and set it to SMC */
	ret = ata_timing_compute(adev, adev->pio_mode, &timing, 1000, 0);
	if (ret) {
		dev_warn(ap->dev, "Failed to compute ATA timing %d, "
			 "set PIO_0 timing\n", ret);
		timing = *ata_timing_find_mode(XFER_PIO_0);
	}
	set_smc_timing(ap->dev, adev, info, &timing);
}

static unsigned int pata_at91_data_xfer_noirq(struct ata_device *dev,
		unsigned char *buf, unsigned int buflen, int rw)
{
	struct at91_ide_info *info = dev->link->ap->host->private_data;
	unsigned int consumed;
	unsigned long flags;
	struct sam9_smc_config smc;

	local_irq_save(flags);
	sam9_smc_read_mode(0, info->cs, &smc);

	/* set 16bit mode before writing data */
	smc.mode = (smc.mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_16;
	sam9_smc_write_mode(0, info->cs, &smc);

	consumed = ata_sff_data_xfer(dev, buf, buflen, rw);

	/* restore 8bit mode after data is written */
	smc.mode = (smc.mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_8;
	sam9_smc_write_mode(0, info->cs, &smc);

	local_irq_restore(flags);
	return consumed;
}

static struct scsi_host_template pata_at91_sht = {
	ATA_PIO_SHT(DRV_NAME),
};

static struct ata_port_operations pata_at91_port_ops = {
	.inherits	= &ata_sff_port_ops,

	.sff_data_xfer	= pata_at91_data_xfer_noirq,
	.set_piomode	= pata_at91_set_piomode,
	.cable_detect	= ata_cable_40wire,
};

static int pata_at91_probe(struct platform_device *pdev)
{
	struct at91_cf_data *board = pdev->dev.platform_data;
	struct device *dev = &pdev->dev;
	struct at91_ide_info *info;
	struct resource *mem_res;
	struct ata_host *host;
	struct ata_port *ap;

	int irq_flags = 0;
	int irq = 0;
	int ret;

	/*  get platform resources: IO/CTL memories and irq/rst pins */

	if (pdev->num_resources != 1) {
		dev_err(&pdev->dev, "invalid number of resources\n");
		return -EINVAL;
	}

	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	if (!mem_res) {
		dev_err(dev, "failed to get mem resource\n");
		return -EINVAL;
	}

	irq = board->irq_pin;

	/* init ata host */

	host = ata_host_alloc(dev, 1);

	if (!host)
		return -ENOMEM;

	ap = host->ports[0];
	ap->ops = &pata_at91_port_ops;
	ap->flags |= ATA_FLAG_SLAVE_POSS;
	ap->pio_mask = ATA_PIO4;

	if (!gpio_is_valid(irq)) {
		ap->flags |= ATA_FLAG_PIO_POLLING;
		ata_port_desc(ap, "no IRQ, using PIO polling");
	}

	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);

	if (!info) {
		dev_err(dev, "failed to allocate memory for private data\n");
		return -ENOMEM;
	}

	info->mck = clk_get(NULL, "mck");

	if (IS_ERR(info->mck)) {
		dev_err(dev, "failed to get access to mck clock\n");
		return -ENODEV;
	}

	info->cs    = board->chipselect;
	info->mode  = AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
		AT91_SMC_EXNWMODE_READY | AT91_SMC_BAT_SELECT |
		AT91_SMC_DBW_8 | AT91_SMC_TDF_(0);

	info->ide_addr = devm_ioremap(dev,
			mem_res->start + CF_IDE_OFFSET, CF_IDE_RES_SIZE);

	if (!info->ide_addr) {
		dev_err(dev, "failed to map IO base\n");
		ret = -ENOMEM;
		goto err_put;
	}

	info->alt_addr = devm_ioremap(dev,
			mem_res->start + CF_ALT_IDE_OFFSET, CF_IDE_RES_SIZE);

	if (!info->alt_addr) {
		dev_err(dev, "failed to map CTL base\n");
		ret = -ENOMEM;
		goto err_put;
	}

	ap->ioaddr.cmd_addr = info->ide_addr;
	ap->ioaddr.ctl_addr = info->alt_addr + 0x06;
	ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;

	ata_sff_std_ports(&ap->ioaddr);

	ata_port_desc(ap, "mmio cmd 0x%llx ctl 0x%llx",
			(unsigned long long)mem_res->start + CF_IDE_OFFSET,
			(unsigned long long)mem_res->start + CF_ALT_IDE_OFFSET);

	host->private_data = info;

	ret = ata_host_activate(host, gpio_is_valid(irq) ? gpio_to_irq(irq) : 0,
				gpio_is_valid(irq) ? ata_sff_interrupt : NULL,
				irq_flags, &pata_at91_sht);
	if (ret)
		goto err_put;

	return 0;

err_put:
	clk_put(info->mck);
	return ret;
}

static int pata_at91_remove(struct platform_device *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	struct at91_ide_info *info;

	if (!host)
		return 0;
	info = host->private_data;

	ata_host_detach(host);

	if (!info)
		return 0;

	clk_put(info->mck);

	return 0;
}

static struct platform_driver pata_at91_driver = {
	.probe		= pata_at91_probe,
	.remove		= pata_at91_remove,
	.driver		= {
		.name		= DRV_NAME,
		.owner		= THIS_MODULE,
	},
};

module_platform_driver(pata_at91_driver);

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Driver for CF in True IDE mode on AT91SAM9260 SoC");
MODULE_AUTHOR("Matyukevich Sergey");
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
918d7b7c SM	1	/*
	2	* PATA driver for AT91SAM9260 Static Memory Controller
	3	* with CompactFlash interface in True IDE mode
	4	*
	5	* Copyright (C) 2009 Matyukevich Sergey
0144261f	6	* 2011 Igor Plyatov
918d7b7c SM	7	*
	8	* Based on:
	9	* * generic platform driver by Paul Mundt: drivers/ata/pata_platform.c
	10	* * pata_at32 driver by Kristoffer Nyborg Gregertsen
	11	* * at91_ide driver by Stanislaw Gruszka
	12	*
	13	* This program is free software; you can redistribute it and/or modify it
	14	* under the terms of the GNU General Public License version 2
	15	* as published by the Free Software Foundation.
	16	*
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/init.h>
	22	#include <linux/blkdev.h>
5a0e3ad6	23	#include <linux/gfp.h>
918d7b7c SM	24	#include <scsi/scsi_host.h>
	25	#include <linux/ata.h>
	26	#include <linux/clk.h>
	27	#include <linux/libata.h>
	28	#include <linux/platform_device.h>
	29	#include <linux/ata_platform.h>
bcd2360c	30	#include <linux/platform_data/atmel.h>
918d7b7c	31
918d7b7c	32	#include <mach/at91sam9_smc.h>
60e8972d	33	#include <asm/gpio.h>
918d7b7c	34
0144261f IP	35	#define DRV_NAME "pata_at91"
0144261f IP	36	#define DRV_VERSION "0.3"
918d7b7c	37
0144261f IP	38	#define CF_IDE_OFFSET 0x00c00000
	39	#define CF_ALT_IDE_OFFSET 0x00e00000
	40	#define CF_IDE_RES_SIZE 0x08
	41	#define CS_PULSE_MAXIMUM 319
	42	#define ER_SMC_CALC 1
	43	#define ER_SMC_RECALC 2
918d7b7c SM	44
	45	struct at91_ide_info {
	46	unsigned long mode;
	47	unsigned int cs;
7d084d96	48	struct clk *mck;
918d7b7c SM	49	void __iomem *ide_addr;
	50	void __iomem *alt_addr;
	51	};
	52
0144261f IP	53	/**
	54	* struct smc_range - range of valid values for SMC register.
	55	*/
	56	struct smc_range {
	57	int min;
	58	int max;
792d37af	59	};
918d7b7c	60
0144261f IP	61	/**
	62	* adjust_smc_value - adjust value for one of SMC registers.
	63	* @value: adjusted value
	64	* @range: array of SMC ranges with valid values
	65	* @size: SMC ranges array size
	66	*
	67	* This returns the difference between input and output value or negative
	68	* in case of invalid input value.
	69	* If negative returned, then output value = maximal possible from ranges.
	70	*/
	71	static int adjust_smc_value(int value, struct smc_range range, int size)
	72	{
	73	int maximum = (range + size - 1)->max;
	74	int remainder;
	75
	76	do {
	77	if (*value < range->min) {
	78	remainder = range->min - *value;
	79	value = range->min; / nearest valid value */
	80	return remainder;
	81	} else if ((range->min <= value) && (value <= range->max))
	82	return 0;
	83
	84	range++;
	85	} while (--size);
	86	*value = maximum;
	87
	88	return -1; /* invalid value */
	89	}
	90
	91	/**
	92	* calc_smc_vals - calculate SMC register values
	93	* @dev: ATA device
	94	* @setup: SMC_SETUP register value
	95	* @pulse: SMC_PULSE register value
	96	* @cycle: SMC_CYCLE register value
	97	*
	98	* This returns negative in case of invalid values for SMC registers:
	99	* -ER_SMC_RECALC - recalculation required for SMC values,
	100	* -ER_SMC_CALC - calculation failed (invalid input values).
	101	*
	102	* SMC use special coding scheme, see "Coding and Range of Timing
	103	* Parameters" table from AT91SAM9 datasheets.
	104	*
	105	* SMC_SETUP = 128*setup[5] + setup[4:0]
	106	* SMC_PULSE = 256*pulse[6] + pulse[5:0]
	107	* SMC_CYCLE = 256*cycle[8:7] + cycle[6:0]
	108	*/
	109	static int calc_smc_vals(struct device *dev,
	110	int setup, int pulse, int cycle, int cs_pulse)
	111	{
	112	int ret_val;
	113	int err = 0;
	114	struct smc_range range_setup[] = { /* SMC_SETUP valid values */
	115	{.min = 0, .max = 31}, /* first range */
	116	{.min = 128, .max = 159} /* second range */
	117	};
	118	struct smc_range range_pulse[] = { /* SMC_PULSE valid values */
	119	{.min = 0, .max = 63}, /* first range */
	120	{.min = 256, .max = 319} /* second range */
	121	};
	122	struct smc_range range_cycle[] = { /* SMC_CYCLE valid values */
	123	{.min = 0, .max = 127}, /* first range */
	124	{.min = 256, .max = 383}, /* second range */
125	{.min = 512, .max = 639}, /* third range */
126	{.min = 768, .max = 895} /* fourth range */
127	};
128
129	ret_val = adjust_smc_value(setup, range_setup, ARRAY_SIZE(range_setup));
130	if (ret_val < 0)
131	dev_warn(dev, "maximal SMC Setup value\n");
132	else
133	*cycle += ret_val;
134
135	ret_val = adjust_smc_value(pulse, range_pulse, ARRAY_SIZE(range_pulse));
136	if (ret_val < 0)
137	dev_warn(dev, "maximal SMC Pulse value\n");
138	else
139	*cycle += ret_val;
140
141	ret_val = adjust_smc_value(cycle, range_cycle, ARRAY_SIZE(range_cycle));
142	if (ret_val < 0)
143	dev_warn(dev, "maximal SMC Cycle value\n");
144
145	cs_pulse = cycle;
146	if (*cs_pulse > CS_PULSE_MAXIMUM) {
147	dev_err(dev, "unable to calculate valid SMC settings\n");
148	return -ER_SMC_CALC;
149	}
150
151	ret_val = adjust_smc_value(cs_pulse, range_pulse,
152	ARRAY_SIZE(range_pulse));
153	if (ret_val < 0) {
154	dev_warn(dev, "maximal SMC CS Pulse value\n");
155	} else if (ret_val != 0) {
156	cycle = cs_pulse;
157	dev_warn(dev, "SMC Cycle extended\n");
158	err = -ER_SMC_RECALC;
159	}
160
161	return err;
162	}
163
164	/**
165	* to_smc_format - convert values into SMC format
166	* @setup: SETUP value of SMC Setup Register
167	* @pulse: PULSE value of SMC Pulse Register
168	* @cycle: CYCLE value of SMC Cycle Register
169	* @cs_pulse: NCS_PULSE value of SMC Pulse Register
170	*/
171	static void to_smc_format(int setup, int pulse, int cycle, int cs_pulse)
172	{
173	setup = (setup & 0x1f) \| ((*setup & 0x80) >> 2);
174	pulse = (pulse & 0x3f) \| ((*pulse & 0x100) >> 2);
175	cycle = (cycle & 0x7f) \| ((*cycle & 0x300) >> 1);
176	cs_pulse = (cs_pulse & 0x3f) \| ((*cs_pulse & 0x100) >> 2);
177	}
178
7d084d96	179	static unsigned long calc_mck_cycles(unsigned long ns, unsigned long mck_hz)
918d7b7c SM	180	{
	181	unsigned long mul;
	182
7d084d96 SM	183	/*
	184	* cycles = x [nsec] * f [Hz] / 10^9 [ns in sec] =
	185	* x * (f / 1_000_000_000) =
	186	* x * ((f * 65536) / 1_000_000_000) / 65536 =
	187	* x * (((f / 10_000) * 65536) / 100_000) / 65536 =
	188	*/
918d7b7c	189
7d084d96 SM	190	mul = (mck_hz / 10000) << 16;
7d084d96 SM	191	mul /= 100000;
918d7b7c	192
7d084d96	193	return (ns * mul + 65536) >> 16; /* rounding */
918d7b7c SM	194	}
918d7b7c SM	195
0144261f IP	196	/**
	197	* set_smc_timing - SMC timings setup.
	198	* @dev: device
	199	* @info: AT91 IDE info
	200	* @ata: ATA timings
	201	*
	202	* Its assumed that write timings are same as read timings,
	203	* cs_setup = 0 and cs_pulse = cycle.
	204	*/
	205	static void set_smc_timing(struct device dev, struct ata_device adev,
918d7b7c SM	206	struct at91_ide_info info, const struct ata_timing ata)
918d7b7c SM	207	{
0144261f IP	208	int ret = 0;
0144261f IP	209	int use_iordy;
88dcde98	210	struct sam9_smc_config smc;
0144261f IP	211	unsigned int t6z; /* data tristate time in ns */
	212	unsigned int cycle; /* SMC Cycle width in MCK ticks */
	213	unsigned int setup; /* SMC Setup width in MCK ticks */
	214	unsigned int pulse; /* CFIOR and CFIOW pulse width in MCK ticks */
0144261f IP	215	unsigned int cs_pulse; /* CS4 or CS5 pulse width in MCK ticks*/
	216	unsigned int tdf_cycles; /* SMC TDF MCK ticks */
	217	unsigned long mck_hz; /* MCK frequency in Hz */
	218
	219	t6z = (ata->mode < XFER_PIO_5) ? 30 : 20;
7d084d96	220	mck_hz = clk_get_rate(info->mck);
0144261f IP	221	cycle = calc_mck_cycles(ata->cyc8b, mck_hz);
	222	setup = calc_mck_cycles(ata->setup, mck_hz);
	223	pulse = calc_mck_cycles(ata->act8b, mck_hz);
	224	tdf_cycles = calc_mck_cycles(t6z, mck_hz);
	225
	226	do {
	227	ret = calc_smc_vals(dev, &setup, &pulse, &cycle, &cs_pulse);
	228	} while (ret == -ER_SMC_RECALC);
	229
	230	if (ret == -ER_SMC_CALC)
	231	dev_err(dev, "Interface may not operate correctly\n");
	232
	233	dev_dbg(dev, "SMC Setup=%u, Pulse=%u, Cycle=%u, CS Pulse=%u\n",
	234	setup, pulse, cycle, cs_pulse);
	235	to_smc_format(&setup, &pulse, &cycle, &cs_pulse);
	236	/* disable or enable waiting for IORDY signal */
	237	use_iordy = ata_pio_need_iordy(adev);
	238	if (use_iordy)
	239	info->mode \|= AT91_SMC_EXNWMODE_READY;
	240
	241	if (tdf_cycles > 15) {
	242	tdf_cycles = 15;
	243	dev_warn(dev, "maximal SMC TDF Cycles value\n");
9719b8f5	244	}
918d7b7c	245
0144261f	246	dev_dbg(dev, "Use IORDY=%u, TDF Cycles=%u\n", use_iordy, tdf_cycles);
88dcde98 JCPV	247
	248	/* SMC Setup Register */
	249	smc.nwe_setup = smc.nrd_setup = setup;
	250	smc.ncs_write_setup = smc.ncs_read_setup = 0;
	251	/* SMC Pulse Register */
	252	smc.nwe_pulse = smc.nrd_pulse = pulse;
	253	smc.ncs_write_pulse = smc.ncs_read_pulse = cs_pulse;
	254	/* SMC Cycle Register */
	255	smc.write_cycle = smc.read_cycle = cycle;
	256	/* SMC Mode Register*/
	257	smc.tdf_cycles = tdf_cycles;
	258	smc.mode = info->mode;
	259
	260	sam9_smc_configure(0, info->cs, &smc);
918d7b7c SM	261	}
	262
	263	static void pata_at91_set_piomode(struct ata_port ap, struct ata_device adev)
	264	{
	265	struct at91_ide_info *info = ap->host->private_data;
	266	struct ata_timing timing;
	267	int ret;
	268
	269	/* Compute ATA timing and set it to SMC */
	270	ret = ata_timing_compute(adev, adev->pio_mode, &timing, 1000, 0);
	271	if (ret) {
429e3861 JG	272	dev_warn(ap->dev, "Failed to compute ATA timing %d, "
429e3861 JG	273	"set PIO_0 timing\n", ret);
0144261f	274	timing = *ata_timing_find_mode(XFER_PIO_0);
918d7b7c	275	}
0144261f	276	set_smc_timing(ap->dev, adev, info, &timing);
918d7b7c SM	277	}
	278
	279	static unsigned int pata_at91_data_xfer_noirq(struct ata_device *dev,
	280	unsigned char *buf, unsigned int buflen, int rw)
	281	{
	282	struct at91_ide_info *info = dev->link->ap->host->private_data;
	283	unsigned int consumed;
	284	unsigned long flags;
88dcde98	285	struct sam9_smc_config smc;
918d7b7c SM	286
918d7b7c SM	287	local_irq_save(flags);
88dcde98	288	sam9_smc_read_mode(0, info->cs, &smc);
918d7b7c SM	289
918d7b7c SM	290	/* set 16bit mode before writing data */
88dcde98 JCPV	291	smc.mode = (smc.mode & ~AT91_SMC_DBW) \| AT91_SMC_DBW_16;
88dcde98 JCPV	292	sam9_smc_write_mode(0, info->cs, &smc);
918d7b7c SM	293
	294	consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
	295
	296	/* restore 8bit mode after data is written */
88dcde98 JCPV	297	smc.mode = (smc.mode & ~AT91_SMC_DBW) \| AT91_SMC_DBW_8;
88dcde98 JCPV	298	sam9_smc_write_mode(0, info->cs, &smc);
918d7b7c SM	299
	300	local_irq_restore(flags);
	301	return consumed;
	302	}
	303
	304	static struct scsi_host_template pata_at91_sht = {
	305	ATA_PIO_SHT(DRV_NAME),
	306	};
	307
	308	static struct ata_port_operations pata_at91_port_ops = {
	309	.inherits = &ata_sff_port_ops,
	310
	311	.sff_data_xfer = pata_at91_data_xfer_noirq,
	312	.set_piomode = pata_at91_set_piomode,
	313	.cable_detect = ata_cable_40wire,
918d7b7c SM	314	};
918d7b7c SM	315
0ec24914	316	static int pata_at91_probe(struct platform_device *pdev)
918d7b7c SM	317	{
	318	struct at91_cf_data *board = pdev->dev.platform_data;
	319	struct device *dev = &pdev->dev;
	320	struct at91_ide_info *info;
	321	struct resource *mem_res;
	322	struct ata_host *host;
	323	struct ata_port *ap;
7d084d96	324
918d7b7c SM	325	int irq_flags = 0;
	326	int irq = 0;
	327	int ret;
	328
	329	/* get platform resources: IO/CTL memories and irq/rst pins */
	330
	331	if (pdev->num_resources != 1) {
	332	dev_err(&pdev->dev, "invalid number of resources\n");
	333	return -EINVAL;
	334	}
	335
	336	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	337
	338	if (!mem_res) {
	339	dev_err(dev, "failed to get mem resource\n");
	340	return -EINVAL;
	341	}
	342
	343	irq = board->irq_pin;
	344
	345	/* init ata host */
	346
	347	host = ata_host_alloc(dev, 1);
	348
	349	if (!host)
	350	return -ENOMEM;
	351
	352	ap = host->ports[0];
	353	ap->ops = &pata_at91_port_ops;
	354	ap->flags \|= ATA_FLAG_SLAVE_POSS;
	355	ap->pio_mask = ATA_PIO4;
	356
477c87e9	357	if (!gpio_is_valid(irq)) {
918d7b7c SM	358	ap->flags \|= ATA_FLAG_PIO_POLLING;
	359	ata_port_desc(ap, "no IRQ, using PIO polling");
	360	}
	361
df9eba8c	362	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
918d7b7c SM	363
	364	if (!info) {
	365	dev_err(dev, "failed to allocate memory for private data\n");
	366	return -ENOMEM;
	367	}
	368
7d084d96 SM	369	info->mck = clk_get(NULL, "mck");
	370
	371	if (IS_ERR(info->mck)) {
	372	dev_err(dev, "failed to get access to mck clock\n");
	373	return -ENODEV;
	374	}
	375
918d7b7c SM	376	info->cs = board->chipselect;
	377	info->mode = AT91_SMC_READMODE \| AT91_SMC_WRITEMODE \|
	378	AT91_SMC_EXNWMODE_READY \| AT91_SMC_BAT_SELECT \|
	379	AT91_SMC_DBW_8 \| AT91_SMC_TDF_(0);
	380
	381	info->ide_addr = devm_ioremap(dev,
	382	mem_res->start + CF_IDE_OFFSET, CF_IDE_RES_SIZE);
	383
	384	if (!info->ide_addr) {
	385	dev_err(dev, "failed to map IO base\n");
	386	ret = -ENOMEM;
df9eba8c	387	goto err_put;
918d7b7c SM	388	}
	389
	390	info->alt_addr = devm_ioremap(dev,
	391	mem_res->start + CF_ALT_IDE_OFFSET, CF_IDE_RES_SIZE);
	392
	393	if (!info->alt_addr) {
	394	dev_err(dev, "failed to map CTL base\n");
	395	ret = -ENOMEM;
df9eba8c	396	goto err_put;
918d7b7c SM	397	}
	398
	399	ap->ioaddr.cmd_addr = info->ide_addr;
	400	ap->ioaddr.ctl_addr = info->alt_addr + 0x06;
	401	ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
	402
	403	ata_sff_std_ports(&ap->ioaddr);
	404
	405	ata_port_desc(ap, "mmio cmd 0x%llx ctl 0x%llx",
	406	(unsigned long long)mem_res->start + CF_IDE_OFFSET,
	407	(unsigned long long)mem_res->start + CF_ALT_IDE_OFFSET);
	408
	409	host->private_data = info;
	410
2ec453bf BZ	411	ret = ata_host_activate(host, gpio_is_valid(irq) ? gpio_to_irq(irq) : 0,
	412	gpio_is_valid(irq) ? ata_sff_interrupt : NULL,
	413	irq_flags, &pata_at91_sht);
	414	if (ret)
	415	goto err_put;
918d7b7c	416
2ec453bf	417	return 0;
8e3bfdb9	418
df9eba8c	419	err_put:
7d084d96	420	clk_put(info->mck);
918d7b7c SM	421	return ret;
	422	}
	423
0ec24914	424	static int pata_at91_remove(struct platform_device *pdev)
918d7b7c SM	425	{
918d7b7c SM	426	struct ata_host *host = dev_get_drvdata(&pdev->dev);
1e1f421a	427	struct at91_ide_info *info;
918d7b7c SM	428
	429	if (!host)
	430	return 0;
1e1f421a	431	info = host->private_data;
918d7b7c SM	432
	433	ata_host_detach(host);
	434
	435	if (!info)
	436	return 0;
	437
7d084d96	438	clk_put(info->mck);
918d7b7c	439
918d7b7c SM	440	return 0;
	441	}
	442
	443	static struct platform_driver pata_at91_driver = {
	444	.probe = pata_at91_probe,
0ec24914	445	.remove = pata_at91_remove,
0144261f	446	.driver = {
918d7b7c SM	447	.name = DRV_NAME,
	448	.owner = THIS_MODULE,
	449	},
	450	};
	451
99c8ea3e	452	module_platform_driver(pata_at91_driver);
918d7b7c SM	453
	454	MODULE_LICENSE("GPL");
	455	MODULE_DESCRIPTION("Driver for CF in True IDE mode on AT91SAM9260 SoC");
	456	MODULE_AUTHOR("Matyukevich Sergey");
	457	MODULE_VERSION(DRV_VERSION);
	458