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Merge tag 'v3.10.108' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / pata_amd.c
CommitLineData
669a5db4
JG		 1/*
2 * pata_amd.c - AMD PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
669a5db4
JG		 4 *
5 * Based on pata-sil680. Errata information is taken from data sheets
6 * and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
7 * claimed by sata-nv.c.
8 *
9 * TODO:
10 * Variable system clock when/if it makes sense
11 * Power management on ports
12 *
13 *
25985edc 14 * Documentation publicly available.
669a5db4
JG		 15 */
16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/pci.h>
20#include <linux/init.h>
21#include <linux/blkdev.h>
22#include <linux/delay.h>
23#include <scsi/scsi_host.h>
24#include <linux/libata.h>
25
26#define DRV_NAME "pata_amd"
c48052cc 27#define DRV_VERSION "0.4.1"
669a5db4
JG		 28
29/**
30 * timing_setup - shared timing computation and load
31 * @ap: ATA port being set up
32 * @adev: drive being configured
33 * @offset: port offset
34 * @speed: target speed
35 * @clock: clock multiplier (number of times 33MHz for this part)
36 *
37 * Perform the actual timing set up for Nvidia or AMD PATA devices.
38 * The actual devices vary so they all call into this helper function
39 * providing the clock multipler and offset (because AMD and Nvidia put
40 * the ports at different locations).
41 */
42
43static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock)
44{
45 static const unsigned char amd_cyc2udma[] = {
46 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
47 };
48
49 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
50 struct ata_device *peer = ata_dev_pair(adev);
51 int dn = ap->port_no * 2 + adev->devno;
52 struct ata_timing at, apeer;
53 int T, UT;
54 const int amd_clock = 33333; /* KHz. */
55 u8 t;
56
57 T = 1000000000 / amd_clock;
d9c74fbe
HH		 58 UT = T;
59 if (clock >= 2)
60 UT = T / 2;
669a5db4
JG		 61
62 if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
a44fec1f 63 dev_err(&pdev->dev, "unknown mode %d\n", speed);
669a5db4
JG		 64 return;
65 }
66
67 if (peer) {
68 /* This may be over conservative */
69 if (peer->dma_mode) {
70 ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
71 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
72 }
73 ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
74 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
75 }
76
77 if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
78 if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;
79
80 /*
81 * Now do the setup work
82 */
83
84 /* Configure the address set up timing */
85 pci_read_config_byte(pdev, offset + 0x0C, &t);
07633b5d 86 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
669a5db4
JG		 87 pci_write_config_byte(pdev, offset + 0x0C , t);
88
89 /* Configure the 8bit I/O timing */
90 pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
07633b5d 91 ((clamp_val(at.act8b, 1, 16) - 1) << 4) | (clamp_val(at.rec8b, 1, 16) - 1));
669a5db4
JG		 92
93 /* Drive timing */
94 pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
07633b5d 95 ((clamp_val(at.active, 1, 16) - 1) << 4) | (clamp_val(at.recover, 1, 16) - 1));
669a5db4
JG		 96
97 switch (clock) {
98 case 1:
07633b5d 99 t = at.udma ? (0xc0 | (clamp_val(at.udma, 2, 5) - 2)) : 0x03;
669a5db4
JG		 100 break;
101
102 case 2:
07633b5d 103 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 2, 10)]) : 0x03;
669a5db4
JG		 104 break;
105
106 case 3:
07633b5d 107 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 10)]) : 0x03;
669a5db4
JG		 108 break;
109
110 case 4:
07633b5d 111 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 15)]) : 0x03;
669a5db4
JG		 112 break;
113
114 default:
115 return;
116 }
117
118 /* UDMA timing */
943547ab
BZ		 119 if (at.udma)
120 pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
669a5db4
JG		 121}
122
123/**
cc0680a5
TH		 124 * amd_pre_reset - perform reset handling
125 * @link: ATA link
d4b2bab4 126 * @deadline: deadline jiffies for the operation
669a5db4 127 *
eb4a2c7f
AC		 128 * Reset sequence checking enable bits to see which ports are
129 * active.
669a5db4
JG		 130 */
131
cc0680a5 132static int amd_pre_reset(struct ata_link *link, unsigned long deadline)
669a5db4 133{
669a5db4
JG		 134 static const struct pci_bits amd_enable_bits[] = {
135 { 0x40, 1, 0x02, 0x02 },
136 { 0x40, 1, 0x01, 0x01 }
137 };
138
cc0680a5 139 struct ata_port *ap = link->ap;
669a5db4 140 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
85cd7251 141
c961922b
AC		 142 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
143 return -ENOENT;
669a5db4 144
9363c382 145 return ata_sff_prereset(link, deadline);
669a5db4
JG		 146}
147
c48052cc
AC		 148/**
149 * amd_cable_detect - report cable type
150 * @ap: port
151 *
152 * AMD controller/BIOS setups record the cable type in word 0x42
153 */
154
eb4a2c7f 155static int amd_cable_detect(struct ata_port *ap)
669a5db4 156{
eb4a2c7f 157 static const u32 bitmask[2] = {0x03, 0x0C};
669a5db4 158 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
eb4a2c7f 159 u8 ata66;
669a5db4 160
eb4a2c7f
AC		 161 pci_read_config_byte(pdev, 0x42, &ata66);
162 if (ata66 & bitmask[ap->port_no])
163 return ATA_CBL_PATA80;
164 return ATA_CBL_PATA40;
669a5db4
JG		 165}
166
c48052cc
AC		 167/**
168 * amd_fifo_setup - set the PIO FIFO for ATA/ATAPI
169 * @ap: ATA interface
170 * @adev: ATA device
171 *
172 * Set the PCI fifo for this device according to the devices present
173 * on the bus at this point in time. We need to turn the post write buffer
174 * off for ATAPI devices as we may need to issue a word sized write to the
175 * device as the final I/O
176 */
177
178static void amd_fifo_setup(struct ata_port *ap)
179{
180 struct ata_device *adev;
181 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
182 static const u8 fifobit[2] = { 0xC0, 0x30};
183 u8 fifo = fifobit[ap->port_no];
184 u8 r;
185
186
187 ata_for_each_dev(adev, &ap->link, ENABLED) {
188 if (adev->class == ATA_DEV_ATAPI)
189 fifo = 0;
190 }
191 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411) /* FIFO is broken */
192 fifo = 0;
193
194 /* On the later chips the read prefetch bits become no-op bits */
195 pci_read_config_byte(pdev, 0x41, &r);
196 r &= ~fifobit[ap->port_no];
197 r |= fifo;
198 pci_write_config_byte(pdev, 0x41, r);
199}
200
669a5db4
JG		 201/**
202 * amd33_set_piomode - set initial PIO mode data
203 * @ap: ATA interface
204 * @adev: ATA device
205 *
206 * Program the AMD registers for PIO mode.
207 */
208
209static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev)
210{
c48052cc 211 amd_fifo_setup(ap);
669a5db4
JG		 212 timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
213}
214
215static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev)
216{
c48052cc 217 amd_fifo_setup(ap);
669a5db4
JG		 218 timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
219}
220
221static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev)
222{
c48052cc 223 amd_fifo_setup(ap);
669a5db4
JG		 224 timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
225}
226
227static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev)
228{
c48052cc 229 amd_fifo_setup(ap);
669a5db4
JG		 230 timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
231}
232
233/**
234 * amd33_set_dmamode - set initial DMA mode data
235 * @ap: ATA interface
236 * @adev: ATA device
237 *
238 * Program the MWDMA/UDMA modes for the AMD and Nvidia
239 * chipset.
240 */
241
242static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev)
243{
244 timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
245}
246
247static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev)
248{
249 timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
250}
251
252static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
253{
254 timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
255}
256
257static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
258{
259 timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
260}
261
ce54d161
TH		 262/* Both host-side and drive-side detection results are worthless on NV
263 * PATAs. Ignore them and just follow what BIOS configured. Both the
264 * current configuration in PCI config reg and ACPI GTM result are
265 * cached during driver attach and are consulted to select transfer
266 * mode.
267 */
268static unsigned long nv_mode_filter(struct ata_device *dev,
269 unsigned long xfer_mask)
270{
271 static const unsigned int udma_mask_map[] =
272 { ATA_UDMA2, ATA_UDMA1, ATA_UDMA0, 0,
273 ATA_UDMA3, ATA_UDMA4, ATA_UDMA5, ATA_UDMA6 };
274 struct ata_port *ap = dev->link->ap;
275 char acpi_str[32] = "";
276 u32 saved_udma, udma;
277 const struct ata_acpi_gtm *gtm;
278 unsigned long bios_limit = 0, acpi_limit = 0, limit;
279
280 /* find out what BIOS configured */
281 udma = saved_udma = (unsigned long)ap->host->private_data;
282
283 if (ap->port_no == 0)
284 udma >>= 16;
285 if (dev->devno == 0)
286 udma >>= 8;
287
288 if ((udma & 0xc0) == 0xc0)
289 bios_limit = ata_pack_xfermask(0, 0, udma_mask_map[udma & 0x7]);
290
291 /* consult ACPI GTM too */
292 gtm = ata_acpi_init_gtm(ap);
293 if (gtm) {
294 acpi_limit = ata_acpi_gtm_xfermask(dev, gtm);
295
296 snprintf(acpi_str, sizeof(acpi_str), " (%u:%u:0x%x)",
297 gtm->drive[0].dma, gtm->drive[1].dma, gtm->flags);
298 }
299
300 /* be optimistic, EH can take care of things if something goes wrong */
301 limit = bios_limit | acpi_limit;
302
303 /* If PIO or DMA isn't configured at all, don't limit. Let EH
304 * handle it.
305 */
306 if (!(limit & ATA_MASK_PIO))
307 limit |= ATA_MASK_PIO;
308 if (!(limit & (ATA_MASK_MWDMA | ATA_MASK_UDMA)))
309 limit |= ATA_MASK_MWDMA | ATA_MASK_UDMA;
90950a25
RH		 310 /* PIO4, MWDMA2, UDMA2 should always be supported regardless of
311 cable detection result */
312 limit |= ata_pack_xfermask(ATA_PIO4, ATA_MWDMA2, ATA_UDMA2);
ce54d161 313
a9a79dfe 314 ata_port_dbg(ap, "nv_mode_filter: 0x%lx&0x%lx->0x%lx, "
ce54d161
TH		 315 "BIOS=0x%lx (0x%x) ACPI=0x%lx%s\n",
316 xfer_mask, limit, xfer_mask & limit, bios_limit,
317 saved_udma, acpi_limit, acpi_str);
318
319 return xfer_mask & limit;
320}
669a5db4
JG		 321
322/**
323 * nv_probe_init - cable detection
cc0680a5 324 * @lin: ATA link
669a5db4
JG		 325 *
326 * Perform cable detection. The BIOS stores this in PCI config
327 * space for us.
328 */
329
cc0680a5 330static int nv_pre_reset(struct ata_link *link, unsigned long deadline)
d4b2bab4 331{
76ff3c6e
AC		 332 static const struct pci_bits nv_enable_bits[] = {
333 { 0x50, 1, 0x02, 0x02 },
334 { 0x50, 1, 0x01, 0x01 }
335 };
669a5db4 336
cc0680a5 337 struct ata_port *ap = link->ap;
669a5db4 338 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
669a5db4 339
c961922b
AC		 340 if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no]))
341 return -ENOENT;
76ff3c6e 342
9363c382 343 return ata_sff_prereset(link, deadline);
669a5db4
JG		 344}
345
669a5db4
JG		 346/**
347 * nv100_set_piomode - set initial PIO mode data
348 * @ap: ATA interface
349 * @adev: ATA device
350 *
351 * Program the AMD registers for PIO mode.
352 */
353
354static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev)
355{
356 timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
357}
358
359static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev)
360{
361 timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
362}
363
364/**
365 * nv100_set_dmamode - set initial DMA mode data
366 * @ap: ATA interface
367 * @adev: ATA device
368 *
369 * Program the MWDMA/UDMA modes for the AMD and Nvidia
370 * chipset.
371 */
372
373static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
374{
375 timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
376}
377
378static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
379{
380 timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
381}
382
ce54d161
TH		 383static void nv_host_stop(struct ata_host *host)
384{
385 u32 udma = (unsigned long)host->private_data;
386
387 /* restore PCI config register 0x60 */
388 pci_write_config_dword(to_pci_dev(host->dev), 0x60, udma);
389}
390
669a5db4 391static struct scsi_host_template amd_sht = {
68d1d07b 392 ATA_BMDMA_SHT(DRV_NAME),
669a5db4
JG		 393};
394
029cfd6b 395static const struct ata_port_operations amd_base_port_ops = {
871af121 396 .inherits = &ata_bmdma32_port_ops,
887125e3 397 .prereset = amd_pre_reset,
029cfd6b
TH		 398};
399
669a5db4 400static struct ata_port_operations amd33_port_ops = {
029cfd6b
TH		 401 .inherits = &amd_base_port_ops,
402 .cable_detect = ata_cable_40wire,
669a5db4
JG		 403 .set_piomode = amd33_set_piomode,
404 .set_dmamode = amd33_set_dmamode,
669a5db4
JG		 405};
406
407static struct ata_port_operations amd66_port_ops = {
029cfd6b
TH		 408 .inherits = &amd_base_port_ops,
409 .cable_detect = ata_cable_unknown,
669a5db4
JG		 410 .set_piomode = amd66_set_piomode,
411 .set_dmamode = amd66_set_dmamode,
669a5db4
JG		 412};
413
414static struct ata_port_operations amd100_port_ops = {
029cfd6b
TH		 415 .inherits = &amd_base_port_ops,
416 .cable_detect = ata_cable_unknown,
669a5db4
JG		 417 .set_piomode = amd100_set_piomode,
418 .set_dmamode = amd100_set_dmamode,
669a5db4
JG		 419};
420
421static struct ata_port_operations amd133_port_ops = {
029cfd6b
TH		 422 .inherits = &amd_base_port_ops,
423 .cable_detect = amd_cable_detect,
669a5db4
JG		 424 .set_piomode = amd133_set_piomode,
425 .set_dmamode = amd133_set_dmamode,
029cfd6b 426};
669a5db4 427
029cfd6b
TH		 428static const struct ata_port_operations nv_base_port_ops = {
429 .inherits = &ata_bmdma_port_ops,
430 .cable_detect = ata_cable_ignore,
431 .mode_filter = nv_mode_filter,
887125e3 432 .prereset = nv_pre_reset,
029cfd6b 433 .host_stop = nv_host_stop,
669a5db4
JG		 434};
435
436static struct ata_port_operations nv100_port_ops = {
029cfd6b 437 .inherits = &nv_base_port_ops,
669a5db4
JG		 438 .set_piomode = nv100_set_piomode,
439 .set_dmamode = nv100_set_dmamode,
669a5db4
JG		 440};
441
442static struct ata_port_operations nv133_port_ops = {
029cfd6b 443 .inherits = &nv_base_port_ops,
669a5db4
JG		 444 .set_piomode = nv133_set_piomode,
445 .set_dmamode = nv133_set_dmamode,
669a5db4
JG		 446};
447
c48052cc
AC		 448static void amd_clear_fifo(struct pci_dev *pdev)
449{
450 u8 fifo;
451 /* Disable the FIFO, the FIFO logic will re-enable it as
452 appropriate */
453 pci_read_config_byte(pdev, 0x41, &fifo);
454 fifo &= 0x0F;
455 pci_write_config_byte(pdev, 0x41, fifo);
456}
457
669a5db4
JG		 458static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
459{
1626aeb8 460 static const struct ata_port_info info[10] = {
14bdef98 461 { /* 0: AMD 7401 - no swdma */
1d2808fd 462 .flags = ATA_FLAG_SLAVE_POSS,
14bdef98
EIB		 463 .pio_mask = ATA_PIO4,
464 .mwdma_mask = ATA_MWDMA2,
465 .udma_mask = ATA_UDMA2,
669a5db4
JG		 466 .port_ops = &amd33_port_ops
467 },
468 { /* 1: Early AMD7409 - no swdma */
1d2808fd 469 .flags = ATA_FLAG_SLAVE_POSS,
14bdef98
EIB		 470 .pio_mask = ATA_PIO4,
471 .mwdma_mask = ATA_MWDMA2,
472 .udma_mask = ATA_UDMA4,
669a5db4
JG		 473 .port_ops = &amd66_port_ops
474 },
14bdef98 475 { /* 2: AMD 7409 */
1d2808fd 476 .flags = ATA_FLAG_SLAVE_POSS,
14bdef98
EIB		 477 .pio_mask = ATA_PIO4,
478 .mwdma_mask = ATA_MWDMA2,
479 .udma_mask = ATA_UDMA4,
669a5db4
JG		 480 .port_ops = &amd66_port_ops
481 },
482 { /* 3: AMD 7411 */
1d2808fd 483 .flags = ATA_FLAG_SLAVE_POSS,
14bdef98
EIB		 484 .pio_mask = ATA_PIO4,
485 .mwdma_mask = ATA_MWDMA2,
486 .udma_mask = ATA_UDMA5,
669a5db4
JG		 487 .port_ops = &amd100_port_ops
488 },
489 { /* 4: AMD 7441 */
1d2808fd 490 .flags = ATA_FLAG_SLAVE_POSS,
14bdef98
EIB		 491 .pio_mask = ATA_PIO4,
492 .mwdma_mask = ATA_MWDMA2,
493 .udma_mask = ATA_UDMA5,
669a5db4
JG		 494 .port_ops = &amd100_port_ops
495 },
14bdef98 496 { /* 5: AMD 8111 - no swdma */
1d2808fd 497 .flags = ATA_FLAG_SLAVE_POSS,
14bdef98
EIB		 498 .pio_mask = ATA_PIO4,
499 .mwdma_mask = ATA_MWDMA2,
500 .udma_mask = ATA_UDMA6,
669a5db4
JG		 501 .port_ops = &amd133_port_ops
502 },
14bdef98 503 { /* 6: AMD 8111 UDMA 100 (Serenade) - no swdma */
1d2808fd 504 .flags = ATA_FLAG_SLAVE_POSS,
14bdef98
EIB		 505 .pio_mask = ATA_PIO4,
506 .mwdma_mask = ATA_MWDMA2,
507 .udma_mask = ATA_UDMA5,
669a5db4
JG		 508 .port_ops = &amd133_port_ops
509 },
510 { /* 7: Nvidia Nforce */
1d2808fd 511 .flags = ATA_FLAG_SLAVE_POSS,
14bdef98
EIB		 512 .pio_mask = ATA_PIO4,
513 .mwdma_mask = ATA_MWDMA2,
514 .udma_mask = ATA_UDMA5,
669a5db4
JG		 515 .port_ops = &nv100_port_ops
516 },
14bdef98 517 { /* 8: Nvidia Nforce2 and later - no swdma */
1d2808fd 518 .flags = ATA_FLAG_SLAVE_POSS,
14bdef98
EIB		 519 .pio_mask = ATA_PIO4,
520 .mwdma_mask = ATA_MWDMA2,
521 .udma_mask = ATA_UDMA6,
669a5db4
JG		 522 .port_ops = &nv133_port_ops
523 },
524 { /* 9: AMD CS5536 (Geode companion) */
1d2808fd 525 .flags = ATA_FLAG_SLAVE_POSS,
14bdef98
EIB		 526 .pio_mask = ATA_PIO4,
527 .mwdma_mask = ATA_MWDMA2,
528 .udma_mask = ATA_UDMA5,
669a5db4
JG		 529 .port_ops = &amd100_port_ops
530 }
531 };
887125e3 532 const struct ata_port_info *ppi[] = { NULL, NULL };
669a5db4 533 int type = id->driver_data;
887125e3 534 void *hpriv = NULL;
669a5db4 535 u8 fifo;
f08048e9 536 int rc;
669a5db4 537
06296a1e 538 ata_print_version_once(&pdev->dev, DRV_VERSION);
669a5db4 539
f08048e9
TH		 540 rc = pcim_enable_device(pdev);
541 if (rc)
542 return rc;
543
669a5db4
JG		 544 pci_read_config_byte(pdev, 0x41, &fifo);
545
546 /* Check for AMD7409 without swdma errata and if found adjust type */
44c10138 547 if (type == 1 && pdev->revision > 0x7)
669a5db4
JG		 548 type = 2;
549
ce54d161
TH		 550 /* Serenade ? */
551 if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
552 pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
553 type = 6; /* UDMA 100 only */
554
555 /*
556 * Okay, type is determined now. Apply type-specific workarounds.
557 */
887125e3 558 ppi[0] = &info[type];
ce54d161
TH		 559
560 if (type < 3)
9363c382 561 ata_pci_bmdma_clear_simplex(pdev);
c48052cc
AC		 562 if (pdev->vendor == PCI_VENDOR_ID_AMD)
563 amd_clear_fifo(pdev);
ce54d161
TH		 564 /* Cable detection on Nvidia chips doesn't work too well,
565 * cache BIOS programmed UDMA mode.
566 */
567 if (type == 7 || type == 8) {
568 u32 udma;
669a5db4 569
ce54d161 570 pci_read_config_dword(pdev, 0x60, &udma);
887125e3 571 hpriv = (void *)(unsigned long)udma;
ce54d161 572 }
669a5db4
JG		 573
574 /* And fire it up */
1c5afdf7 575 return ata_pci_bmdma_init_one(pdev, ppi, &amd_sht, hpriv, 0);
669a5db4
JG		 576}
577
438ac6d5 578#ifdef CONFIG_PM
c304193a
AC		 579static int amd_reinit_one(struct pci_dev *pdev)
580{
f08048e9
TH		 581 struct ata_host *host = dev_get_drvdata(&pdev->dev);
582 int rc;
583
584 rc = ata_pci_device_do_resume(pdev);
585 if (rc)
586 return rc;
587
c304193a 588 if (pdev->vendor == PCI_VENDOR_ID_AMD) {
c48052cc 589 amd_clear_fifo(pdev);
c304193a
AC		 590 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 ||
591 pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
9363c382 592 ata_pci_bmdma_clear_simplex(pdev);
c304193a 593 }
f08048e9
TH		 594 ata_host_resume(host);
595 return 0;
c304193a 596}
438ac6d5 597#endif
c304193a 598
669a5db4 599static const struct pci_device_id amd[] = {
2d2744fc
JG		 600 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
601 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
602 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 3 },
603 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 4 },
604 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 5 },
605 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 7 },
606 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 8 },
607 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 8 },
608 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 8 },
609 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 8 },
610 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 8 },
611 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 8 },
612 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 8 },
613 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 8 },
614 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 8 },
05e2867a
PC		 615 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 8 },
616 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 8 },
9f789755
PC		 617 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 8 },
618 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 8 },
2d2744fc
JG		 619 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 9 },
620
621 { },
669a5db4
JG		 622};
623
624static struct pci_driver amd_pci_driver = {
2d2744fc 625 .name = DRV_NAME,
669a5db4
JG		 626 .id_table = amd,
627 .probe = amd_init_one,
c304193a 628 .remove = ata_pci_remove_one,
438ac6d5 629#ifdef CONFIG_PM
c304193a
AC		 630 .suspend = ata_pci_device_suspend,
631 .resume = amd_reinit_one,
438ac6d5 632#endif
669a5db4
JG		 633};
634
2fc75da0 635module_pci_driver(amd_pci_driver);
669a5db4 636
669a5db4 637MODULE_AUTHOR("Alan Cox");
c9544bcb 638MODULE_DESCRIPTION("low-level driver for AMD and Nvidia PATA IDE");
669a5db4
JG		 639MODULE_LICENSE("GPL");
640MODULE_DEVICE_TABLE(pci, amd);
641MODULE_VERSION(DRV_VERSION);
kernel source for telekom puls (alcatel/mediatek)