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[PATCH] jiffies_64 cleanup
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86_64 / kernel / time.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/arch/x86-64/kernel/time.c
3 *
4 * "High Precision Event Timer" based timekeeping.
5 *
6 * Copyright (c) 1991,1992,1995 Linus Torvalds
7 * Copyright (c) 1994 Alan Modra
8 * Copyright (c) 1995 Markus Kuhn
9 * Copyright (c) 1996 Ingo Molnar
10 * Copyright (c) 1998 Andrea Arcangeli
11 * Copyright (c) 2002 Vojtech Pavlik
12 * Copyright (c) 2003 Andi Kleen
13 * RTC support code taken from arch/i386/kernel/timers/time_hpet.c
14 */
15
16#include <linux/kernel.h>
17#include <linux/sched.h>
18#include <linux/interrupt.h>
19#include <linux/init.h>
20#include <linux/mc146818rtc.h>
1da177e4
LT		 21#include <linux/time.h>
22#include <linux/ioport.h>
23#include <linux/module.h>
24#include <linux/device.h>
25#include <linux/sysdev.h>
26#include <linux/bcd.h>
27#include <linux/kallsyms.h>
312df5f1 28#include <linux/acpi.h>
8d916406 29#ifdef CONFIG_ACPI
312df5f1 30#include <acpi/achware.h> /* for PM timer frequency */
8d916406 31#endif
1da177e4
LT		 32#include <asm/8253pit.h>
33#include <asm/pgtable.h>
34#include <asm/vsyscall.h>
35#include <asm/timex.h>
36#include <asm/proto.h>
37#include <asm/hpet.h>
38#include <asm/sections.h>
39#include <linux/cpufreq.h>
40#include <linux/hpet.h>
41#ifdef CONFIG_X86_LOCAL_APIC
42#include <asm/apic.h>
43#endif
44
1da177e4
LT		 45#ifdef CONFIG_CPU_FREQ
46static void cpufreq_delayed_get(void);
47#endif
48extern void i8254_timer_resume(void);
49extern int using_apic_timer;
50
51DEFINE_SPINLOCK(rtc_lock);
52DEFINE_SPINLOCK(i8253_lock);
53
54static int nohpet __initdata = 0;
55static int notsc __initdata = 0;
56
57#undef HPET_HACK_ENABLE_DANGEROUS
58
59unsigned int cpu_khz; /* TSC clocks / usec, not used here */
60static unsigned long hpet_period; /* fsecs / HPET clock */
61unsigned long hpet_tick; /* HPET clocks / interrupt */
a3a00751 62static int hpet_use_timer;
1da177e4
LT		 63unsigned long vxtime_hz = PIT_TICK_RATE;
64int report_lost_ticks; /* command line option */
65unsigned long long monotonic_base;
66
67struct vxtime_data __vxtime __section_vxtime; /* for vsyscalls */
68
69volatile unsigned long __jiffies __section_jiffies = INITIAL_JIFFIES;
70unsigned long __wall_jiffies __section_wall_jiffies = INITIAL_JIFFIES;
71struct timespec __xtime __section_xtime;
72struct timezone __sys_tz __section_sys_tz;
73
74static inline void rdtscll_sync(unsigned long *tsc)
75{
76#ifdef CONFIG_SMP
77 sync_core();
78#endif
79 rdtscll(*tsc);
80}
81
82/*
83 * do_gettimeoffset() returns microseconds since last timer interrupt was
84 * triggered by hardware. A memory read of HPET is slower than a register read
85 * of TSC, but much more reliable. It's also synchronized to the timer
86 * interrupt. Note that do_gettimeoffset() may return more than hpet_tick, if a
87 * timer interrupt has happened already, but vxtime.trigger wasn't updated yet.
88 * This is not a problem, because jiffies hasn't updated either. They are bound
89 * together by xtime_lock.
90 */
91
92static inline unsigned int do_gettimeoffset_tsc(void)
93{
94 unsigned long t;
95 unsigned long x;
96 rdtscll_sync(&t);
97 if (t < vxtime.last_tsc) t = vxtime.last_tsc; /* hack */
98 x = ((t - vxtime.last_tsc) * vxtime.tsc_quot) >> 32;
99 return x;
100}
101
102static inline unsigned int do_gettimeoffset_hpet(void)
103{
a3a00751
JS		 104 /* cap counter read to one tick to avoid inconsistencies */
105 unsigned long counter = hpet_readl(HPET_COUNTER) - vxtime.last;
106 return (min(counter,hpet_tick) * vxtime.quot) >> 32;
1da177e4
LT		 107}
108
109unsigned int (*do_gettimeoffset)(void) = do_gettimeoffset_tsc;
110
111/*
112 * This version of gettimeofday() has microsecond resolution and better than
113 * microsecond precision, as we're using at least a 10 MHz (usually 14.31818
114 * MHz) HPET timer.
115 */
116
117void do_gettimeofday(struct timeval *tv)
118{
119 unsigned long seq, t;
120 unsigned int sec, usec;
121
122 do {
123 seq = read_seqbegin(&xtime_lock);
124
125 sec = xtime.tv_sec;
126 usec = xtime.tv_nsec / 1000;
127
128 /* i386 does some correction here to keep the clock
129 monotonous even when ntpd is fixing drift.
130 But they didn't work for me, there is a non monotonic
131 clock anyways with ntp.
132 I dropped all corrections now until a real solution can
133 be found. Note when you fix it here you need to do the same
134 in arch/x86_64/kernel/vsyscall.c and export all needed
135 variables in vmlinux.lds. -AK */
136
137 t = (jiffies - wall_jiffies) * (1000000L / HZ) +
138 do_gettimeoffset();
139 usec += t;
140
141 } while (read_seqretry(&xtime_lock, seq));
142
143 tv->tv_sec = sec + usec / 1000000;
144 tv->tv_usec = usec % 1000000;
145}
146
147EXPORT_SYMBOL(do_gettimeofday);
148
149/*
150 * settimeofday() first undoes the correction that gettimeofday would do
151 * on the time, and then saves it. This is ugly, but has been like this for
152 * ages already.
153 */
154
155int do_settimeofday(struct timespec *tv)
156{
157 time_t wtm_sec, sec = tv->tv_sec;
158 long wtm_nsec, nsec = tv->tv_nsec;
159
160 if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC)
161 return -EINVAL;
162
163 write_seqlock_irq(&xtime_lock);
164
165 nsec -= do_gettimeoffset() * 1000 +
166 (jiffies - wall_jiffies) * (NSEC_PER_SEC/HZ);
167
168 wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec);
169 wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec);
170
171 set_normalized_timespec(&xtime, sec, nsec);
172 set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec);
173
b149ee22 174 ntp_clear();
1da177e4
LT		 175
176 write_sequnlock_irq(&xtime_lock);
177 clock_was_set();
178 return 0;
179}
180
181EXPORT_SYMBOL(do_settimeofday);
182
183unsigned long profile_pc(struct pt_regs *regs)
184{
185 unsigned long pc = instruction_pointer(regs);
186
187 /* Assume the lock function has either no stack frame or only a single word.
188 This checks if the address on the stack looks like a kernel text address.
189 There is a small window for false hits, but in that case the tick
190 is just accounted to the spinlock function.
191 Better would be to write these functions in assembler again
192 and check exactly. */
193 if (in_lock_functions(pc)) {
194 char *v = *(char **)regs->rsp;
195 if ((v >= _stext && v <= _etext) ||
196 (v >= _sinittext && v <= _einittext) ||
197 (v >= (char *)MODULES_VADDR && v <= (char *)MODULES_END))
198 return (unsigned long)v;
199 return ((unsigned long *)regs->rsp)[1];
200 }
201 return pc;
202}
203EXPORT_SYMBOL(profile_pc);
204
205/*
206 * In order to set the CMOS clock precisely, set_rtc_mmss has to be called 500
207 * ms after the second nowtime has started, because when nowtime is written
208 * into the registers of the CMOS clock, it will jump to the next second
209 * precisely 500 ms later. Check the Motorola MC146818A or Dallas DS12887 data
210 * sheet for details.
211 */
212
213static void set_rtc_mmss(unsigned long nowtime)
214{
215 int real_seconds, real_minutes, cmos_minutes;
216 unsigned char control, freq_select;
217
218/*
219 * IRQs are disabled when we're called from the timer interrupt,
220 * no need for spin_lock_irqsave()
221 */
222
223 spin_lock(&rtc_lock);
224
225/*
226 * Tell the clock it's being set and stop it.
227 */
228
229 control = CMOS_READ(RTC_CONTROL);
230 CMOS_WRITE(control | RTC_SET, RTC_CONTROL);
231
232 freq_select = CMOS_READ(RTC_FREQ_SELECT);
233 CMOS_WRITE(freq_select | RTC_DIV_RESET2, RTC_FREQ_SELECT);
234
235 cmos_minutes = CMOS_READ(RTC_MINUTES);
236 BCD_TO_BIN(cmos_minutes);
237
238/*
239 * since we're only adjusting minutes and seconds, don't interfere with hour
240 * overflow. This avoids messing with unknown time zones but requires your RTC
241 * not to be off by more than 15 minutes. Since we're calling it only when
242 * our clock is externally synchronized using NTP, this shouldn't be a problem.
243 */
244
245 real_seconds = nowtime % 60;
246 real_minutes = nowtime / 60;
247 if (((abs(real_minutes - cmos_minutes) + 15) / 30) & 1)
248 real_minutes += 30; /* correct for half hour time zone */
249 real_minutes %= 60;
250
251#if 0
252 /* AMD 8111 is a really bad time keeper and hits this regularly.
253 It probably was an attempt to avoid screwing up DST, but ignore
254 that for now. */
255 if (abs(real_minutes - cmos_minutes) >= 30) {
256 printk(KERN_WARNING "time.c: can't update CMOS clock "
257 "from %d to %d\n", cmos_minutes, real_minutes);
258 } else
259#endif
260
261 {
262 BIN_TO_BCD(real_seconds);
263 BIN_TO_BCD(real_minutes);
264 CMOS_WRITE(real_seconds, RTC_SECONDS);
265 CMOS_WRITE(real_minutes, RTC_MINUTES);
266 }
267
268/*
269 * The following flags have to be released exactly in this order, otherwise the
270 * DS12887 (popular MC146818A clone with integrated battery and quartz) will
271 * not reset the oscillator and will not update precisely 500 ms later. You
272 * won't find this mentioned in the Dallas Semiconductor data sheets, but who
273 * believes data sheets anyway ... -- Markus Kuhn
274 */
275
276 CMOS_WRITE(control, RTC_CONTROL);
277 CMOS_WRITE(freq_select, RTC_FREQ_SELECT);
278
279 spin_unlock(&rtc_lock);
280}
281
282
283/* monotonic_clock(): returns # of nanoseconds passed since time_init()
284 * Note: This function is required to return accurate
285 * time even in the absence of multiple timer ticks.
286 */
287unsigned long long monotonic_clock(void)
288{
289 unsigned long seq;
290 u32 last_offset, this_offset, offset;
291 unsigned long long base;
292
293 if (vxtime.mode == VXTIME_HPET) {
294 do {
295 seq = read_seqbegin(&xtime_lock);
296
297 last_offset = vxtime.last;
298 base = monotonic_base;
a3a00751 299 this_offset = hpet_readl(HPET_COUNTER);
1da177e4
LT		 300
301 } while (read_seqretry(&xtime_lock, seq));
302 offset = (this_offset - last_offset);
303 offset *=(NSEC_PER_SEC/HZ)/hpet_tick;
304 return base + offset;
305 }else{
306 do {
307 seq = read_seqbegin(&xtime_lock);
308
309 last_offset = vxtime.last_tsc;
310 base = monotonic_base;
311 } while (read_seqretry(&xtime_lock, seq));
312 sync_core();
313 rdtscll(this_offset);
314 offset = (this_offset - last_offset)*1000/cpu_khz;
315 return base + offset;
316 }
317
318
319}
320EXPORT_SYMBOL(monotonic_clock);
321
322static noinline void handle_lost_ticks(int lost, struct pt_regs *regs)
323{
324 static long lost_count;
325 static int warned;
326
327 if (report_lost_ticks) {
328 printk(KERN_WARNING "time.c: Lost %d timer "
329 "tick(s)! ", lost);
330 print_symbol("rip %s)\n", regs->rip);
331 }
332
333 if (lost_count == 1000 && !warned) {
334 printk(KERN_WARNING
335 "warning: many lost ticks.\n"
336 KERN_WARNING "Your time source seems to be instable or "
337 "some driver is hogging interupts\n");
338 print_symbol("rip %s\n", regs->rip);
339 if (vxtime.mode == VXTIME_TSC && vxtime.hpet_address) {
340 printk(KERN_WARNING "Falling back to HPET\n");
341 vxtime.last = hpet_readl(HPET_T0_CMP) - hpet_tick;
342 vxtime.mode = VXTIME_HPET;
343 do_gettimeoffset = do_gettimeoffset_hpet;
344 }
345 /* else should fall back to PIT, but code missing. */
346 warned = 1;
347 } else
348 lost_count++;
349
350#ifdef CONFIG_CPU_FREQ
351 /* In some cases the CPU can change frequency without us noticing
352 (like going into thermal throttle)
353 Give cpufreq a change to catch up. */
354 if ((lost_count+1) % 25 == 0) {
355 cpufreq_delayed_get();
356 }
357#endif
358}
359
360static irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
361{
362 static unsigned long rtc_update = 0;
363 unsigned long tsc;
364 int delay, offset = 0, lost = 0;
365
366/*
367 * Here we are in the timer irq handler. We have irqs locally disabled (so we
368 * don't need spin_lock_irqsave()) but we don't know if the timer_bh is running
369 * on the other CPU, so we need a lock. We also need to lock the vsyscall
370 * variables, because both do_timer() and us change them -arca+vojtech
371 */
372
373 write_seqlock(&xtime_lock);
374
a3a00751
JS		 375 if (vxtime.hpet_address)
376 offset = hpet_readl(HPET_COUNTER);
377
378 if (hpet_use_timer) {
379 /* if we're using the hpet timer functionality,
380 * we can more accurately know the counter value
381 * when the timer interrupt occured.
382 */
1da177e4
LT		 383 offset = hpet_readl(HPET_T0_CMP) - hpet_tick;
384 delay = hpet_readl(HPET_COUNTER) - offset;
385 } else {
386 spin_lock(&i8253_lock);
387 outb_p(0x00, 0x43);
388 delay = inb_p(0x40);
389 delay |= inb(0x40) << 8;
390 spin_unlock(&i8253_lock);
391 delay = LATCH - 1 - delay;
392 }
393
394 rdtscll_sync(&tsc);
395
396 if (vxtime.mode == VXTIME_HPET) {
397 if (offset - vxtime.last > hpet_tick) {
398 lost = (offset - vxtime.last) / hpet_tick - 1;
399 }
400
401 monotonic_base +=
402 (offset - vxtime.last)*(NSEC_PER_SEC/HZ) / hpet_tick;
403
404 vxtime.last = offset;
312df5f1
AK		 405#ifdef CONFIG_X86_PM_TIMER
406 } else if (vxtime.mode == VXTIME_PMTMR) {
407 lost = pmtimer_mark_offset();
408#endif
1da177e4
LT		 409 } else {
410 offset = (((tsc - vxtime.last_tsc) *
411 vxtime.tsc_quot) >> 32) - (USEC_PER_SEC / HZ);
412
413 if (offset < 0)
414 offset = 0;
415
416 if (offset > (USEC_PER_SEC / HZ)) {
417 lost = offset / (USEC_PER_SEC / HZ);
418 offset %= (USEC_PER_SEC / HZ);
419 }
420
421 monotonic_base += (tsc - vxtime.last_tsc)*1000000/cpu_khz ;
422
423 vxtime.last_tsc = tsc - vxtime.quot * delay / vxtime.tsc_quot;
424
425 if ((((tsc - vxtime.last_tsc) *
426 vxtime.tsc_quot) >> 32) < offset)
427 vxtime.last_tsc = tsc -
428 (((long) offset << 32) / vxtime.tsc_quot) - 1;
429 }
430
431 if (lost > 0) {
432 handle_lost_ticks(lost, regs);
433 jiffies += lost;
434 }
435
436/*
437 * Do the timer stuff.
438 */
439
440 do_timer(regs);
441#ifndef CONFIG_SMP
442 update_process_times(user_mode(regs));
443#endif
444
445/*
446 * In the SMP case we use the local APIC timer interrupt to do the profiling,
447 * except when we simulate SMP mode on a uniprocessor system, in that case we
448 * have to call the local interrupt handler.
449 */
450
451#ifndef CONFIG_X86_LOCAL_APIC
452 profile_tick(CPU_PROFILING, regs);
453#else
454 if (!using_apic_timer)
455 smp_local_timer_interrupt(regs);
456#endif
457
458/*
459 * If we have an externally synchronized Linux clock, then update CMOS clock
460 * accordingly every ~11 minutes. set_rtc_mmss() will be called in the jiffy
461 * closest to exactly 500 ms before the next second. If the update fails, we
462 * don't care, as it'll be updated on the next turn, and the problem (time way
463 * off) isn't likely to go away much sooner anyway.
464 */
465
b149ee22 466 if (ntp_synced() && xtime.tv_sec > rtc_update &&
1da177e4
LT		 467 abs(xtime.tv_nsec - 500000000) <= tick_nsec / 2) {
468 set_rtc_mmss(xtime.tv_sec);
469 rtc_update = xtime.tv_sec + 660;
470 }
471
472 write_sequnlock(&xtime_lock);
473
474 return IRQ_HANDLED;
475}
476
477static unsigned int cyc2ns_scale;
478#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
479
dacb16b1 480static inline void set_cyc2ns_scale(unsigned long cpu_khz)
1da177e4 481{
dacb16b1 482 cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz;
1da177e4
LT		 483}
484
485static inline unsigned long long cycles_2_ns(unsigned long long cyc)
486{
487 return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
488}
489
490unsigned long long sched_clock(void)
491{
492 unsigned long a = 0;
493
494#if 0
495 /* Don't do a HPET read here. Using TSC always is much faster
496 and HPET may not be mapped yet when the scheduler first runs.
497 Disadvantage is a small drift between CPUs in some configurations,
498 but that should be tolerable. */
499 if (__vxtime.mode == VXTIME_HPET)
500 return (hpet_readl(HPET_COUNTER) * vxtime.quot) >> 32;
501#endif
502
503 /* Could do CPU core sync here. Opteron can execute rdtsc speculatively,
504 which means it is not completely exact and may not be monotonous between
505 CPUs. But the errors should be too small to matter for scheduling
506 purposes. */
507
508 rdtscll(a);
509 return cycles_2_ns(a);
510}
511
512unsigned long get_cmos_time(void)
513{
514 unsigned int timeout, year, mon, day, hour, min, sec;
515 unsigned char last, this;
516 unsigned long flags;
517
518/*
519 * The Linux interpretation of the CMOS clock register contents: When the
520 * Update-In-Progress (UIP) flag goes from 1 to 0, the RTC registers show the
521 * second which has precisely just started. Waiting for this can take up to 1
522 * second, we timeout approximately after 2.4 seconds on a machine with
523 * standard 8.3 MHz ISA bus.
524 */
525
526 spin_lock_irqsave(&rtc_lock, flags);
527
528 timeout = 1000000;
529 last = this = 0;
530
531 while (timeout && last && !this) {
532 last = this;
533 this = CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP;
534 timeout--;
535 }
536
537/*
538 * Here we are safe to assume the registers won't change for a whole second, so
539 * we just go ahead and read them.
540 */
541
542 sec = CMOS_READ(RTC_SECONDS);
543 min = CMOS_READ(RTC_MINUTES);
544 hour = CMOS_READ(RTC_HOURS);
545 day = CMOS_READ(RTC_DAY_OF_MONTH);
546 mon = CMOS_READ(RTC_MONTH);
547 year = CMOS_READ(RTC_YEAR);
548
549 spin_unlock_irqrestore(&rtc_lock, flags);
550
551/*
552 * We know that x86-64 always uses BCD format, no need to check the config
553 * register.
554 */
555
556 BCD_TO_BIN(sec);
557 BCD_TO_BIN(min);
558 BCD_TO_BIN(hour);
559 BCD_TO_BIN(day);
560 BCD_TO_BIN(mon);
561 BCD_TO_BIN(year);
562
563/*
564 * x86-64 systems only exists since 2002.
565 * This will work up to Dec 31, 2100
566 */
567 year += 2000;
568
569 return mktime(year, mon, day, hour, min, sec);
570}
571
572#ifdef CONFIG_CPU_FREQ
573
574/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
575 changes.
576
577 RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
578 not that important because current Opteron setups do not support
579 scaling on SMP anyroads.
580
581 Should fix up last_tsc too. Currently gettimeofday in the
582 first tick after the change will be slightly wrong. */
583
584#include <linux/workqueue.h>
585
586static unsigned int cpufreq_delayed_issched = 0;
587static unsigned int cpufreq_init = 0;
588static struct work_struct cpufreq_delayed_get_work;
589
590static void handle_cpufreq_delayed_get(void *v)
591{
592 unsigned int cpu;
593 for_each_online_cpu(cpu) {
594 cpufreq_get(cpu);
595 }
596 cpufreq_delayed_issched = 0;
597}
598
599/* if we notice lost ticks, schedule a call to cpufreq_get() as it tries
600 * to verify the CPU frequency the timing core thinks the CPU is running
601 * at is still correct.
602 */
603static void cpufreq_delayed_get(void)
604{
605 static int warned;
606 if (cpufreq_init && !cpufreq_delayed_issched) {
607 cpufreq_delayed_issched = 1;
608 if (!warned) {
609 warned = 1;
610 printk(KERN_DEBUG "Losing some ticks... checking if CPU frequency changed.\n");
611 }
612 schedule_work(&cpufreq_delayed_get_work);
613 }
614}
615
616static unsigned int ref_freq = 0;
617static unsigned long loops_per_jiffy_ref = 0;
618
619static unsigned long cpu_khz_ref = 0;
620
621static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
622 void *data)
623{
624 struct cpufreq_freqs *freq = data;
625 unsigned long *lpj, dummy;
626
c29601e9
AK		 627 if (cpu_has(&cpu_data[freq->cpu], X86_FEATURE_CONSTANT_TSC))
628 return 0;
629
1da177e4
LT		 630 lpj = &dummy;
631 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
632#ifdef CONFIG_SMP
633 lpj = &cpu_data[freq->cpu].loops_per_jiffy;
634#else
635 lpj = &boot_cpu_data.loops_per_jiffy;
636#endif
637
1da177e4
LT		 638 if (!ref_freq) {
639 ref_freq = freq->old;
640 loops_per_jiffy_ref = *lpj;
641 cpu_khz_ref = cpu_khz;
642 }
643 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
644 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
645 (val == CPUFREQ_RESUMECHANGE)) {
646 *lpj =
647 cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
648
649 cpu_khz = cpufreq_scale(cpu_khz_ref, ref_freq, freq->new);
650 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
651 vxtime.tsc_quot = (1000L << 32) / cpu_khz;
652 }
653
dacb16b1 654 set_cyc2ns_scale(cpu_khz_ref);
1da177e4
LT		 655
656 return 0;
657}
658
659static struct notifier_block time_cpufreq_notifier_block = {
660 .notifier_call = time_cpufreq_notifier
661};
662
663static int __init cpufreq_tsc(void)
664{
665 INIT_WORK(&cpufreq_delayed_get_work, handle_cpufreq_delayed_get, NULL);
666 if (!cpufreq_register_notifier(&time_cpufreq_notifier_block,
667 CPUFREQ_TRANSITION_NOTIFIER))
668 cpufreq_init = 1;
669 return 0;
670}
671
672core_initcall(cpufreq_tsc);
673
674#endif
675
676/*
677 * calibrate_tsc() calibrates the processor TSC in a very simple way, comparing
678 * it to the HPET timer of known frequency.
679 */
680
681#define TICK_COUNT 100000000
682
683static unsigned int __init hpet_calibrate_tsc(void)
684{
685 int tsc_start, hpet_start;
686 int tsc_now, hpet_now;
687 unsigned long flags;
688
689 local_irq_save(flags);
690 local_irq_disable();
691
692 hpet_start = hpet_readl(HPET_COUNTER);
693 rdtscl(tsc_start);
694
695 do {
696 local_irq_disable();
697 hpet_now = hpet_readl(HPET_COUNTER);
698 sync_core();
699 rdtscl(tsc_now);
700 local_irq_restore(flags);
701 } while ((tsc_now - tsc_start) < TICK_COUNT &&
702 (hpet_now - hpet_start) < TICK_COUNT);
703
704 return (tsc_now - tsc_start) * 1000000000L
705 / ((hpet_now - hpet_start) * hpet_period / 1000);
706}
707
708
709/*
710 * pit_calibrate_tsc() uses the speaker output (channel 2) of
711 * the PIT. This is better than using the timer interrupt output,
712 * because we can read the value of the speaker with just one inb(),
713 * where we need three i/o operations for the interrupt channel.
714 * We count how many ticks the TSC does in 50 ms.
715 */
716
717static unsigned int __init pit_calibrate_tsc(void)
718{
719 unsigned long start, end;
720 unsigned long flags;
721
722 spin_lock_irqsave(&i8253_lock, flags);
723
724 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
725
726 outb(0xb0, 0x43);
727 outb((PIT_TICK_RATE / (1000 / 50)) & 0xff, 0x42);
728 outb((PIT_TICK_RATE / (1000 / 50)) >> 8, 0x42);
729 rdtscll(start);
730 sync_core();
731 while ((inb(0x61) & 0x20) == 0);
732 sync_core();
733 rdtscll(end);
734
735 spin_unlock_irqrestore(&i8253_lock, flags);
736
737 return (end - start) / 50;
738}
739
740#ifdef CONFIG_HPET
741static __init int late_hpet_init(void)
742{
743 struct hpet_data hd;
744 unsigned int ntimer;
745
746 if (!vxtime.hpet_address)
747 return -1;
748
749 memset(&hd, 0, sizeof (hd));
750
751 ntimer = hpet_readl(HPET_ID);
752 ntimer = (ntimer & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
753 ntimer++;
754
755 /*
756 * Register with driver.
757 * Timer0 and Timer1 is used by platform.
758 */
759 hd.hd_phys_address = vxtime.hpet_address;
760 hd.hd_address = (void *)fix_to_virt(FIX_HPET_BASE);
761 hd.hd_nirqs = ntimer;
762 hd.hd_flags = HPET_DATA_PLATFORM;
763 hpet_reserve_timer(&hd, 0);
764#ifdef CONFIG_HPET_EMULATE_RTC
765 hpet_reserve_timer(&hd, 1);
766#endif
767 hd.hd_irq[0] = HPET_LEGACY_8254;
768 hd.hd_irq[1] = HPET_LEGACY_RTC;
769 if (ntimer > 2) {
770 struct hpet *hpet;
771 struct hpet_timer *timer;
772 int i;
773
774 hpet = (struct hpet *) fix_to_virt(FIX_HPET_BASE);
775
776 for (i = 2, timer = &hpet->hpet_timers[2]; i < ntimer;
777 timer++, i++)
778 hd.hd_irq[i] = (timer->hpet_config &
779 Tn_INT_ROUTE_CNF_MASK) >>
780 Tn_INT_ROUTE_CNF_SHIFT;
781
782 }
783
784 hpet_alloc(&hd);
785 return 0;
786}
787fs_initcall(late_hpet_init);
788#endif
789
790static int hpet_timer_stop_set_go(unsigned long tick)
791{
792 unsigned int cfg;
793
794/*
795 * Stop the timers and reset the main counter.
796 */
797
798 cfg = hpet_readl(HPET_CFG);
799 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
800 hpet_writel(cfg, HPET_CFG);
801 hpet_writel(0, HPET_COUNTER);
802 hpet_writel(0, HPET_COUNTER + 4);
803
804/*
805 * Set up timer 0, as periodic with first interrupt to happen at hpet_tick,
806 * and period also hpet_tick.
807 */
a3a00751
JS		 808 if (hpet_use_timer) {
809 hpet_writel(HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL |
1da177e4 810 HPET_TN_32BIT, HPET_T0_CFG);
a3a00751
JS		 811 hpet_writel(hpet_tick, HPET_T0_CMP);
812 hpet_writel(hpet_tick, HPET_T0_CMP); /* AK: why twice? */
813 cfg |= HPET_CFG_LEGACY;
814 }
1da177e4
LT		 815/*
816 * Go!
817 */
818
a3a00751 819 cfg |= HPET_CFG_ENABLE;
1da177e4
LT		 820 hpet_writel(cfg, HPET_CFG);
821
822 return 0;
823}
824
825static int hpet_init(void)
826{
827 unsigned int id;
828
829 if (!vxtime.hpet_address)
830 return -1;
831 set_fixmap_nocache(FIX_HPET_BASE, vxtime.hpet_address);
832 __set_fixmap(VSYSCALL_HPET, vxtime.hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
833
834/*
835 * Read the period, compute tick and quotient.
836 */
837
838 id = hpet_readl(HPET_ID);
839
a3a00751 840 if (!(id & HPET_ID_VENDOR) || !(id & HPET_ID_NUMBER))
1da177e4
LT		 841 return -1;
842
843 hpet_period = hpet_readl(HPET_PERIOD);
844 if (hpet_period < 100000 || hpet_period > 100000000)
845 return -1;
846
847 hpet_tick = (1000000000L * (USEC_PER_SEC / HZ) + hpet_period / 2) /
848 hpet_period;
849
a3a00751
JS		 850 hpet_use_timer = (id & HPET_ID_LEGSUP);
851
1da177e4
LT		 852 return hpet_timer_stop_set_go(hpet_tick);
853}
854
855static int hpet_reenable(void)
856{
857 return hpet_timer_stop_set_go(hpet_tick);
858}
859
860void __init pit_init(void)
861{
862 unsigned long flags;
863
864 spin_lock_irqsave(&i8253_lock, flags);
865 outb_p(0x34, 0x43); /* binary, mode 2, LSB/MSB, ch 0 */
866 outb_p(LATCH & 0xff, 0x40); /* LSB */
867 outb_p(LATCH >> 8, 0x40); /* MSB */
868 spin_unlock_irqrestore(&i8253_lock, flags);
869}
870
871int __init time_setup(char *str)
872{
873 report_lost_ticks = 1;
874 return 1;
875}
876
877static struct irqaction irq0 = {
878 timer_interrupt, SA_INTERRUPT, CPU_MASK_NONE, "timer", NULL, NULL
879};
880
881extern void __init config_acpi_tables(void);
882
883void __init time_init(void)
884{
885 char *timename;
886
887#ifdef HPET_HACK_ENABLE_DANGEROUS
888 if (!vxtime.hpet_address) {
889 printk(KERN_WARNING "time.c: WARNING: Enabling HPET base "
890 "manually!\n");
891 outl(0x800038a0, 0xcf8);
892 outl(0xff000001, 0xcfc);
893 outl(0x800038a0, 0xcf8);
894 vxtime.hpet_address = inl(0xcfc) & 0xfffffffe;
895 printk(KERN_WARNING "time.c: WARNING: Enabled HPET "
896 "at %#lx.\n", vxtime.hpet_address);
897 }
898#endif
899 if (nohpet)
900 vxtime.hpet_address = 0;
901
902 xtime.tv_sec = get_cmos_time();
903 xtime.tv_nsec = 0;
904
905 set_normalized_timespec(&wall_to_monotonic,
906 -xtime.tv_sec, -xtime.tv_nsec);
907
a3a00751 908 if (!hpet_init())
1da177e4
LT		 909 vxtime_hz = (1000000000000000L + hpet_period / 2) /
910 hpet_period;
a3a00751
JS		 911
912 if (hpet_use_timer) {
1da177e4
LT		 913 cpu_khz = hpet_calibrate_tsc();
914 timename = "HPET";
312df5f1
AK		 915#ifdef CONFIG_X86_PM_TIMER
916 } else if (pmtmr_ioport) {
917 vxtime_hz = PM_TIMER_FREQUENCY;
918 timename = "PM";
919 pit_init();
920 cpu_khz = pit_calibrate_tsc();
921#endif
1da177e4
LT		 922 } else {
923 pit_init();
924 cpu_khz = pit_calibrate_tsc();
925 timename = "PIT";
926 }
927
928 printk(KERN_INFO "time.c: Using %ld.%06ld MHz %s timer.\n",
929 vxtime_hz / 1000000, vxtime_hz % 1000000, timename);
930 printk(KERN_INFO "time.c: Detected %d.%03d MHz processor.\n",
931 cpu_khz / 1000, cpu_khz % 1000);
932 vxtime.mode = VXTIME_TSC;
933 vxtime.quot = (1000000L << 32) / vxtime_hz;
934 vxtime.tsc_quot = (1000L << 32) / cpu_khz;
1da177e4
LT		 935 rdtscll_sync(&vxtime.last_tsc);
936 setup_irq(0, &irq0);
937
dacb16b1 938 set_cyc2ns_scale(cpu_khz);
a8ab26fe
AK		 939
940#ifndef CONFIG_SMP
941 time_init_gtod();
942#endif
1da177e4
LT		 943}
944
312df5f1
AK		 945/*
946 * Make an educated guess if the TSC is trustworthy and synchronized
947 * over all CPUs.
948 */
949static __init int unsynchronized_tsc(void)
950{
951#ifdef CONFIG_SMP
952 if (oem_force_hpet_timer())
953 return 1;
954 /* Intel systems are normally all synchronized. Exceptions
955 are handled in the OEM check above. */
956 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
957 return 0;
312df5f1
AK		 958#endif
959 /* Assume multi socket systems are not synchronized */
960 return num_online_cpus() > 1;
961}
962
a8ab26fe
AK		 963/*
964 * Decide after all CPUs are booted what mode gettimeofday should use.
965 */
966void __init time_init_gtod(void)
1da177e4
LT		 967{
968 char *timetype;
969
312df5f1 970 if (unsynchronized_tsc())
1da177e4
LT		 971 notsc = 1;
972 if (vxtime.hpet_address && notsc) {
a3a00751 973 timetype = hpet_use_timer ? "HPET" : "PIT/HPET";
1da177e4
LT		 974 vxtime.last = hpet_readl(HPET_T0_CMP) - hpet_tick;
975 vxtime.mode = VXTIME_HPET;
976 do_gettimeoffset = do_gettimeoffset_hpet;
312df5f1
AK		 977#ifdef CONFIG_X86_PM_TIMER
978 /* Using PM for gettimeofday is quite slow, but we have no other
979 choice because the TSC is too unreliable on some systems. */
980 } else if (pmtmr_ioport && !vxtime.hpet_address && notsc) {
981 timetype = "PM";
982 do_gettimeoffset = do_gettimeoffset_pm;
983 vxtime.mode = VXTIME_PMTMR;
984 sysctl_vsyscall = 0;
985 printk(KERN_INFO "Disabling vsyscall due to use of PM timer\n");
986#endif
1da177e4 987 } else {
a3a00751 988 timetype = hpet_use_timer ? "HPET/TSC" : "PIT/TSC";
1da177e4
LT		 989 vxtime.mode = VXTIME_TSC;
990 }
991
992 printk(KERN_INFO "time.c: Using %s based timekeeping.\n", timetype);
993}
994
995__setup("report_lost_ticks", time_setup);
996
997static long clock_cmos_diff;
998static unsigned long sleep_start;
999
0b9c33a7 1000static int timer_suspend(struct sys_device *dev, pm_message_t state)
1da177e4
LT		 1001{
1002 /*
1003 * Estimate time zone so that set_time can update the clock
1004 */
1005 long cmos_time = get_cmos_time();
1006
1007 clock_cmos_diff = -cmos_time;
1008 clock_cmos_diff += get_seconds();
1009 sleep_start = cmos_time;
1010 return 0;
1011}
1012
1013static int timer_resume(struct sys_device *dev)
1014{
1015 unsigned long flags;
1016 unsigned long sec;
1017 unsigned long ctime = get_cmos_time();
1018 unsigned long sleep_length = (ctime - sleep_start) * HZ;
1019
1020 if (vxtime.hpet_address)
1021 hpet_reenable();
1022 else
1023 i8254_timer_resume();
1024
1025 sec = ctime + clock_cmos_diff;
1026 write_seqlock_irqsave(&xtime_lock,flags);
1027 xtime.tv_sec = sec;
1028 xtime.tv_nsec = 0;
1029 write_sequnlock_irqrestore(&xtime_lock,flags);
1030 jiffies += sleep_length;
1031 wall_jiffies += sleep_length;
8446f1d3 1032 touch_softlockup_watchdog();
1da177e4
LT		 1033 return 0;
1034}
1035
1036static struct sysdev_class timer_sysclass = {
1037 .resume = timer_resume,
1038 .suspend = timer_suspend,
1039 set_kset_name("timer"),
1040};
1041
1042
1043/* XXX this driverfs stuff should probably go elsewhere later -john */
1044static struct sys_device device_timer = {
1045 .id = 0,
1046 .cls = &timer_sysclass,
1047};
1048
1049static int time_init_device(void)
1050{
1051 int error = sysdev_class_register(&timer_sysclass);
1052 if (!error)
1053 error = sysdev_register(&device_timer);
1054 return error;
1055}
1056
1057device_initcall(time_init_device);
1058
1059#ifdef CONFIG_HPET_EMULATE_RTC
1060/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
1061 * is enabled, we support RTC interrupt functionality in software.
1062 * RTC has 3 kinds of interrupts:
1063 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
1064 * is updated
1065 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
1066 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
1067 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
1068 * (1) and (2) above are implemented using polling at a frequency of
1069 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
1070 * overhead. (DEFAULT_RTC_INT_FREQ)
1071 * For (3), we use interrupts at 64Hz or user specified periodic
1072 * frequency, whichever is higher.
1073 */
1074#include <linux/rtc.h>
1075
1076extern irqreturn_t rtc_interrupt(int irq, void *dev_id, struct pt_regs *regs);
1077
1078#define DEFAULT_RTC_INT_FREQ 64
1079#define RTC_NUM_INTS 1
1080
1081static unsigned long UIE_on;
1082static unsigned long prev_update_sec;
1083
1084static unsigned long AIE_on;
1085static struct rtc_time alarm_time;
1086
1087static unsigned long PIE_on;
1088static unsigned long PIE_freq = DEFAULT_RTC_INT_FREQ;
1089static unsigned long PIE_count;
1090
1091static unsigned long hpet_rtc_int_freq; /* RTC interrupt frequency */
1092
1093int is_hpet_enabled(void)
1094{
1095 return vxtime.hpet_address != 0;
1096}
1097
1098/*
1099 * Timer 1 for RTC, we do not use periodic interrupt feature,
1100 * even if HPET supports periodic interrupts on Timer 1.
1101 * The reason being, to set up a periodic interrupt in HPET, we need to
1102 * stop the main counter. And if we do that everytime someone diables/enables
1103 * RTC, we will have adverse effect on main kernel timer running on Timer 0.
1104 * So, for the time being, simulate the periodic interrupt in software.
1105 *
1106 * hpet_rtc_timer_init() is called for the first time and during subsequent
1107 * interuppts reinit happens through hpet_rtc_timer_reinit().
1108 */
1109int hpet_rtc_timer_init(void)
1110{
1111 unsigned int cfg, cnt;
1112 unsigned long flags;
1113
1114 if (!is_hpet_enabled())
1115 return 0;
1116 /*
1117 * Set the counter 1 and enable the interrupts.
1118 */
1119 if (PIE_on && (PIE_freq > DEFAULT_RTC_INT_FREQ))
1120 hpet_rtc_int_freq = PIE_freq;
1121 else
1122 hpet_rtc_int_freq = DEFAULT_RTC_INT_FREQ;
1123
1124 local_irq_save(flags);
1125 cnt = hpet_readl(HPET_COUNTER);
1126 cnt += ((hpet_tick*HZ)/hpet_rtc_int_freq);
1127 hpet_writel(cnt, HPET_T1_CMP);
1128 local_irq_restore(flags);
1129
1130 cfg = hpet_readl(HPET_T1_CFG);
1131 cfg |= HPET_TN_ENABLE | HPET_TN_SETVAL | HPET_TN_32BIT;
1132 hpet_writel(cfg, HPET_T1_CFG);
1133
1134 return 1;
1135}
1136
1137static void hpet_rtc_timer_reinit(void)
1138{
1139 unsigned int cfg, cnt;
1140
1141 if (!(PIE_on | AIE_on | UIE_on))
1142 return;
1143
1144 if (PIE_on && (PIE_freq > DEFAULT_RTC_INT_FREQ))
1145 hpet_rtc_int_freq = PIE_freq;
1146 else
1147 hpet_rtc_int_freq = DEFAULT_RTC_INT_FREQ;
1148
1149 /* It is more accurate to use the comparator value than current count.*/
1150 cnt = hpet_readl(HPET_T1_CMP);
1151 cnt += hpet_tick*HZ/hpet_rtc_int_freq;
1152 hpet_writel(cnt, HPET_T1_CMP);
1153
1154 cfg = hpet_readl(HPET_T1_CFG);
1155 cfg |= HPET_TN_ENABLE | HPET_TN_SETVAL | HPET_TN_32BIT;
1156 hpet_writel(cfg, HPET_T1_CFG);
1157
1158 return;
1159}
1160
1161/*
1162 * The functions below are called from rtc driver.
1163 * Return 0 if HPET is not being used.
1164 * Otherwise do the necessary changes and return 1.
1165 */
1166int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1167{
1168 if (!is_hpet_enabled())
1169 return 0;
1170
1171 if (bit_mask & RTC_UIE)
1172 UIE_on = 0;
1173 if (bit_mask & RTC_PIE)
1174 PIE_on = 0;
1175 if (bit_mask & RTC_AIE)
1176 AIE_on = 0;
1177
1178 return 1;
1179}
1180
1181int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1182{
1183 int timer_init_reqd = 0;
1184
1185 if (!is_hpet_enabled())
1186 return 0;
1187
1188 if (!(PIE_on | AIE_on | UIE_on))
1189 timer_init_reqd = 1;
1190
1191 if (bit_mask & RTC_UIE) {
1192 UIE_on = 1;
1193 }
1194 if (bit_mask & RTC_PIE) {
1195 PIE_on = 1;
1196 PIE_count = 0;
1197 }
1198 if (bit_mask & RTC_AIE) {
1199 AIE_on = 1;
1200 }
1201
1202 if (timer_init_reqd)
1203 hpet_rtc_timer_init();
1204
1205 return 1;
1206}
1207
1208int hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec)
1209{
1210 if (!is_hpet_enabled())
1211 return 0;
1212
1213 alarm_time.tm_hour = hrs;
1214 alarm_time.tm_min = min;
1215 alarm_time.tm_sec = sec;
1216
1217 return 1;
1218}
1219
1220int hpet_set_periodic_freq(unsigned long freq)
1221{
1222 if (!is_hpet_enabled())
1223 return 0;
1224
1225 PIE_freq = freq;
1226 PIE_count = 0;
1227
1228 return 1;
1229}
1230
1231int hpet_rtc_dropped_irq(void)
1232{
1233 if (!is_hpet_enabled())
1234 return 0;
1235
1236 return 1;
1237}
1238
1239irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1240{
1241 struct rtc_time curr_time;
1242 unsigned long rtc_int_flag = 0;
1243 int call_rtc_interrupt = 0;
1244
1245 hpet_rtc_timer_reinit();
1246
1247 if (UIE_on | AIE_on) {
1248 rtc_get_rtc_time(&curr_time);
1249 }
1250 if (UIE_on) {
1251 if (curr_time.tm_sec != prev_update_sec) {
1252 /* Set update int info, call real rtc int routine */
1253 call_rtc_interrupt = 1;
1254 rtc_int_flag = RTC_UF;
1255 prev_update_sec = curr_time.tm_sec;
1256 }
1257 }
1258 if (PIE_on) {
1259 PIE_count++;
1260 if (PIE_count >= hpet_rtc_int_freq/PIE_freq) {
1261 /* Set periodic int info, call real rtc int routine */
1262 call_rtc_interrupt = 1;
1263 rtc_int_flag |= RTC_PF;
1264 PIE_count = 0;
1265 }
1266 }
1267 if (AIE_on) {
1268 if ((curr_time.tm_sec == alarm_time.tm_sec) &&
1269 (curr_time.tm_min == alarm_time.tm_min) &&
1270 (curr_time.tm_hour == alarm_time.tm_hour)) {
1271 /* Set alarm int info, call real rtc int routine */
1272 call_rtc_interrupt = 1;
1273 rtc_int_flag |= RTC_AF;
1274 }
1275 }
1276 if (call_rtc_interrupt) {
1277 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1278 rtc_interrupt(rtc_int_flag, dev_id, regs);
1279 }
1280 return IRQ_HANDLED;
1281}
1282#endif
1283
1284
1285
1286static int __init nohpet_setup(char *s)
1287{
1288 nohpet = 1;
1289 return 0;
1290}
1291
1292__setup("nohpet", nohpet_setup);
1293
1294
1295static int __init notsc_setup(char *s)
1296{
1297 notsc = 1;
1298 return 0;
1299}
1300
1301__setup("notsc", notsc_setup);
1302
1303
kernel source for telekom puls (alcatel/mediatek)