projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge master.kernel.org:/pub/scm/linux/kernel/git/wim/linux-2.6-watchdog
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86_64 / kernel / io_apic.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
1da177e4
LT		 24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
28#include <linux/config.h>
29#include <linux/smp_lock.h>
30#include <linux/mc146818rtc.h>
31#include <linux/acpi.h>
32#include <linux/sysdev.h>
33
34#include <asm/io.h>
35#include <asm/smp.h>
36#include <asm/desc.h>
37#include <asm/proto.h>
38#include <asm/mach_apic.h>
8d916406 39#include <asm/acpi.h>
1da177e4
LT		 40
41#define __apicdebuginit __init
42
43int sis_apic_bug; /* not actually supported, dummy for compile */
44
14d98cad
AK		 45static int no_timer_check;
46
66759a01
CE		 47int disable_timer_pin_1 __initdata;
48
1da177e4
LT		 49static DEFINE_SPINLOCK(ioapic_lock);
50
51/*
52 * # of IRQ routing registers
53 */
54int nr_ioapic_registers[MAX_IO_APICS];
55
56/*
57 * Rough estimation of how many shared IRQs there are, can
58 * be changed anytime.
59 */
60#define MAX_PLUS_SHARED_IRQS NR_IRQS
61#define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
62
63/*
64 * This is performance-critical, we want to do it O(1)
65 *
66 * the indexing order of this array favors 1:1 mappings
67 * between pins and IRQs.
68 */
69
70static struct irq_pin_list {
71 short apic, pin, next;
72} irq_2_pin[PIN_MAP_SIZE];
73
6c231b7b 74int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
1da177e4
LT		 75#ifdef CONFIG_PCI_MSI
76#define vector_to_irq(vector) \
77 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
78#else
79#define vector_to_irq(vector) (vector)
80#endif
81
54d5d424
AR		 82#define __DO_ACTION(R, ACTION, FINAL) \
83 \
84{ \
85 int pin; \
86 struct irq_pin_list *entry = irq_2_pin + irq; \
87 \
88 for (;;) { \
89 unsigned int reg; \
90 pin = entry->pin; \
91 if (pin == -1) \
92 break; \
93 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
94 reg ACTION; \
95 io_apic_modify(entry->apic, reg); \
96 if (!entry->next) \
97 break; \
98 entry = irq_2_pin + entry->next; \
99 } \
100 FINAL; \
101}
102
103#ifdef CONFIG_SMP
104static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
105{
106 unsigned long flags;
107 unsigned int dest;
108 cpumask_t tmp;
109
110 cpus_and(tmp, mask, cpu_online_map);
111 if (cpus_empty(tmp))
112 tmp = TARGET_CPUS;
113
114 cpus_and(mask, tmp, CPU_MASK_ALL);
115
116 dest = cpu_mask_to_apicid(mask);
117
118 /*
119 * Only the high 8 bits are valid.
120 */
121 dest = SET_APIC_LOGICAL_ID(dest);
122
123 spin_lock_irqsave(&ioapic_lock, flags);
124 __DO_ACTION(1, = dest, )
125 set_irq_info(irq, mask);
126 spin_unlock_irqrestore(&ioapic_lock, flags);
127}
128#endif
129
1da177e4
LT		 130/*
131 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
132 * shared ISA-space IRQs, so we have to support them. We are super
133 * fast in the common case, and fast for shared ISA-space IRQs.
134 */
135static void add_pin_to_irq(unsigned int irq, int apic, int pin)
136{
137 static int first_free_entry = NR_IRQS;
138 struct irq_pin_list *entry = irq_2_pin + irq;
139
140 while (entry->next)
141 entry = irq_2_pin + entry->next;
142
143 if (entry->pin != -1) {
144 entry->next = first_free_entry;
145 entry = irq_2_pin + entry->next;
146 if (++first_free_entry >= PIN_MAP_SIZE)
147 panic("io_apic.c: whoops");
148 }
149 entry->apic = apic;
150 entry->pin = pin;
151}
152
1da177e4
LT		 153
154#define DO_ACTION(name,R,ACTION, FINAL) \
155 \
156 static void name##_IO_APIC_irq (unsigned int irq) \
157 __DO_ACTION(R, ACTION, FINAL)
158
159DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
160 /* mask = 1 */
161DO_ACTION( __unmask, 0, &= 0xfffeffff, )
162 /* mask = 0 */
163
164static void mask_IO_APIC_irq (unsigned int irq)
165{
166 unsigned long flags;
167
168 spin_lock_irqsave(&ioapic_lock, flags);
169 __mask_IO_APIC_irq(irq);
170 spin_unlock_irqrestore(&ioapic_lock, flags);
171}
172
173static void unmask_IO_APIC_irq (unsigned int irq)
174{
175 unsigned long flags;
176
177 spin_lock_irqsave(&ioapic_lock, flags);
178 __unmask_IO_APIC_irq(irq);
179 spin_unlock_irqrestore(&ioapic_lock, flags);
180}
181
182static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
183{
184 struct IO_APIC_route_entry entry;
185 unsigned long flags;
186
187 /* Check delivery_mode to be sure we're not clearing an SMI pin */
188 spin_lock_irqsave(&ioapic_lock, flags);
189 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
190 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
191 spin_unlock_irqrestore(&ioapic_lock, flags);
192 if (entry.delivery_mode == dest_SMI)
193 return;
194 /*
195 * Disable it in the IO-APIC irq-routing table:
196 */
197 memset(&entry, 0, sizeof(entry));
198 entry.mask = 1;
199 spin_lock_irqsave(&ioapic_lock, flags);
200 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
201 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
202 spin_unlock_irqrestore(&ioapic_lock, flags);
203}
204
205static void clear_IO_APIC (void)
206{
207 int apic, pin;
208
209 for (apic = 0; apic < nr_ioapics; apic++)
210 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
211 clear_IO_APIC_pin(apic, pin);
212}
213
214/*
215 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
216 * specific CPU-side IRQs.
217 */
218
219#define MAX_PIRQS 8
220static int pirq_entries [MAX_PIRQS];
221static int pirqs_enabled;
222int skip_ioapic_setup;
223int ioapic_force;
224
225/* dummy parsing: see setup.c */
226
227static int __init disable_ioapic_setup(char *str)
228{
229 skip_ioapic_setup = 1;
230 return 1;
231}
232
233static int __init enable_ioapic_setup(char *str)
234{
235 ioapic_force = 1;
236 skip_ioapic_setup = 0;
237 return 1;
238}
239
240__setup("noapic", disable_ioapic_setup);
241__setup("apic", enable_ioapic_setup);
242
243#include <asm/pci-direct.h>
244#include <linux/pci_ids.h>
245#include <linux/pci.h>
246
247/* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
248 off. Check for an Nvidia or VIA PCI bridge and turn it off.
249 Use pci direct infrastructure because this runs before the PCI subsystem.
250
251 Can be overwritten with "apic"
252
253 And another hack to disable the IOMMU on VIA chipsets.
254
255 Kludge-O-Rama. */
256void __init check_ioapic(void)
257{
258 int num,slot,func;
259 if (ioapic_force)
260 return;
261
262 /* Poor man's PCI discovery */
263 for (num = 0; num < 32; num++) {
264 for (slot = 0; slot < 32; slot++) {
265 for (func = 0; func < 8; func++) {
266 u32 class;
267 u32 vendor;
268 u8 type;
269 class = read_pci_config(num,slot,func,
270 PCI_CLASS_REVISION);
271 if (class == 0xffffffff)
272 break;
273
274 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
275 continue;
276
277 vendor = read_pci_config(num, slot, func,
278 PCI_VENDOR_ID);
279 vendor &= 0xffff;
280 switch (vendor) {
281 case PCI_VENDOR_ID_VIA:
282#ifdef CONFIG_GART_IOMMU
283 if ((end_pfn >= (0xffffffff>>PAGE_SHIFT) ||
284 force_iommu) &&
285 !iommu_aperture_allowed) {
286 printk(KERN_INFO
287 "Looks like a VIA chipset. Disabling IOMMU. Overwrite with \"iommu=allowed\"\n");
288 iommu_aperture_disabled = 1;
289 }
290#endif
291 return;
292 case PCI_VENDOR_ID_NVIDIA:
293#ifdef CONFIG_ACPI
294 /* All timer overrides on Nvidia
295 seem to be wrong. Skip them. */
296 acpi_skip_timer_override = 1;
297 printk(KERN_INFO
298 "Nvidia board detected. Ignoring ACPI timer override.\n");
299#endif
300 /* RED-PEN skip them on mptables too? */
301 return;
66759a01
CE		 302 case PCI_VENDOR_ID_ATI:
303 /* All timer interrupts on atiixp
304 are doubled. Disable one. */
305 if (disable_timer_pin_1 == 0) {
306 disable_timer_pin_1 = 1;
307 printk(KERN_INFO
308 "ATI board detected. Disabling timer pin 1.\n");
309 }
310 return;
1da177e4
LT		 311 }
312
313 /* No multi-function device? */
314 type = read_pci_config_byte(num,slot,func,
315 PCI_HEADER_TYPE);
316 if (!(type & 0x80))
317 break;
318 }
319 }
320 }
321}
322
323static int __init ioapic_pirq_setup(char *str)
324{
325 int i, max;
326 int ints[MAX_PIRQS+1];
327
328 get_options(str, ARRAY_SIZE(ints), ints);
329
330 for (i = 0; i < MAX_PIRQS; i++)
331 pirq_entries[i] = -1;
332
333 pirqs_enabled = 1;
334 apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
335 max = MAX_PIRQS;
336 if (ints[0] < MAX_PIRQS)
337 max = ints[0];
338
339 for (i = 0; i < max; i++) {
340 apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
341 /*
342 * PIRQs are mapped upside down, usually.
343 */
344 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
345 }
346 return 1;
347}
348
349__setup("pirq=", ioapic_pirq_setup);
350
351/*
352 * Find the IRQ entry number of a certain pin.
353 */
354static int find_irq_entry(int apic, int pin, int type)
355{
356 int i;
357
358 for (i = 0; i < mp_irq_entries; i++)
359 if (mp_irqs[i].mpc_irqtype == type &&
360 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
361 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
362 mp_irqs[i].mpc_dstirq == pin)
363 return i;
364
365 return -1;
366}
367
368/*
369 * Find the pin to which IRQ[irq] (ISA) is connected
370 */
208fb931 371static int find_isa_irq_pin(int irq, int type)
1da177e4
LT		 372{
373 int i;
374
375 for (i = 0; i < mp_irq_entries; i++) {
376 int lbus = mp_irqs[i].mpc_srcbus;
377
378 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
379 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
380 mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
381 (mp_irqs[i].mpc_irqtype == type) &&
382 (mp_irqs[i].mpc_srcbusirq == irq))
383
384 return mp_irqs[i].mpc_dstirq;
385 }
386 return -1;
387}
388
389/*
390 * Find a specific PCI IRQ entry.
391 * Not an __init, possibly needed by modules
392 */
393static int pin_2_irq(int idx, int apic, int pin);
394
395int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
396{
397 int apic, i, best_guess = -1;
398
399 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
400 bus, slot, pin);
401 if (mp_bus_id_to_pci_bus[bus] == -1) {
402 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
403 return -1;
404 }
405 for (i = 0; i < mp_irq_entries; i++) {
406 int lbus = mp_irqs[i].mpc_srcbus;
407
408 for (apic = 0; apic < nr_ioapics; apic++)
409 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
410 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
411 break;
412
413 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
414 !mp_irqs[i].mpc_irqtype &&
415 (bus == lbus) &&
416 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
417 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
418
419 if (!(apic || IO_APIC_IRQ(irq)))
420 continue;
421
422 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
423 return irq;
424 /*
425 * Use the first all-but-pin matching entry as a
426 * best-guess fuzzy result for broken mptables.
427 */
428 if (best_guess < 0)
429 best_guess = irq;
430 }
431 }
432 return best_guess;
433}
434
435/*
436 * EISA Edge/Level control register, ELCR
437 */
438static int EISA_ELCR(unsigned int irq)
439{
440 if (irq < 16) {
441 unsigned int port = 0x4d0 + (irq >> 3);
442 return (inb(port) >> (irq & 7)) & 1;
443 }
444 apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
445 return 0;
446}
447
448/* EISA interrupts are always polarity zero and can be edge or level
449 * trigger depending on the ELCR value. If an interrupt is listed as
450 * EISA conforming in the MP table, that means its trigger type must
451 * be read in from the ELCR */
452
453#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
454#define default_EISA_polarity(idx) (0)
455
456/* ISA interrupts are always polarity zero edge triggered,
457 * when listed as conforming in the MP table. */
458
459#define default_ISA_trigger(idx) (0)
460#define default_ISA_polarity(idx) (0)
461
462/* PCI interrupts are always polarity one level triggered,
463 * when listed as conforming in the MP table. */
464
465#define default_PCI_trigger(idx) (1)
466#define default_PCI_polarity(idx) (1)
467
468/* MCA interrupts are always polarity zero level triggered,
469 * when listed as conforming in the MP table. */
470
471#define default_MCA_trigger(idx) (1)
472#define default_MCA_polarity(idx) (0)
473
474static int __init MPBIOS_polarity(int idx)
475{
476 int bus = mp_irqs[idx].mpc_srcbus;
477 int polarity;
478
479 /*
480 * Determine IRQ line polarity (high active or low active):
481 */
482 switch (mp_irqs[idx].mpc_irqflag & 3)
483 {
484 case 0: /* conforms, ie. bus-type dependent polarity */
485 {
486 switch (mp_bus_id_to_type[bus])
487 {
488 case MP_BUS_ISA: /* ISA pin */
489 {
490 polarity = default_ISA_polarity(idx);
491 break;
492 }
493 case MP_BUS_EISA: /* EISA pin */
494 {
495 polarity = default_EISA_polarity(idx);
496 break;
497 }
498 case MP_BUS_PCI: /* PCI pin */
499 {
500 polarity = default_PCI_polarity(idx);
501 break;
502 }
503 case MP_BUS_MCA: /* MCA pin */
504 {
505 polarity = default_MCA_polarity(idx);
506 break;
507 }
508 default:
509 {
510 printk(KERN_WARNING "broken BIOS!!\n");
511 polarity = 1;
512 break;
513 }
514 }
515 break;
516 }
517 case 1: /* high active */
518 {
519 polarity = 0;
520 break;
521 }
522 case 2: /* reserved */
523 {
524 printk(KERN_WARNING "broken BIOS!!\n");
525 polarity = 1;
526 break;
527 }
528 case 3: /* low active */
529 {
530 polarity = 1;
531 break;
532 }
533 default: /* invalid */
534 {
535 printk(KERN_WARNING "broken BIOS!!\n");
536 polarity = 1;
537 break;
538 }
539 }
540 return polarity;
541}
542
543static int MPBIOS_trigger(int idx)
544{
545 int bus = mp_irqs[idx].mpc_srcbus;
546 int trigger;
547
548 /*
549 * Determine IRQ trigger mode (edge or level sensitive):
550 */
551 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
552 {
553 case 0: /* conforms, ie. bus-type dependent */
554 {
555 switch (mp_bus_id_to_type[bus])
556 {
557 case MP_BUS_ISA: /* ISA pin */
558 {
559 trigger = default_ISA_trigger(idx);
560 break;
561 }
562 case MP_BUS_EISA: /* EISA pin */
563 {
564 trigger = default_EISA_trigger(idx);
565 break;
566 }
567 case MP_BUS_PCI: /* PCI pin */
568 {
569 trigger = default_PCI_trigger(idx);
570 break;
571 }
572 case MP_BUS_MCA: /* MCA pin */
573 {
574 trigger = default_MCA_trigger(idx);
575 break;
576 }
577 default:
578 {
579 printk(KERN_WARNING "broken BIOS!!\n");
580 trigger = 1;
581 break;
582 }
583 }
584 break;
585 }
586 case 1: /* edge */
587 {
588 trigger = 0;
589 break;
590 }
591 case 2: /* reserved */
592 {
593 printk(KERN_WARNING "broken BIOS!!\n");
594 trigger = 1;
595 break;
596 }
597 case 3: /* level */
598 {
599 trigger = 1;
600 break;
601 }
602 default: /* invalid */
603 {
604 printk(KERN_WARNING "broken BIOS!!\n");
605 trigger = 0;
606 break;
607 }
608 }
609 return trigger;
610}
611
612static inline int irq_polarity(int idx)
613{
614 return MPBIOS_polarity(idx);
615}
616
617static inline int irq_trigger(int idx)
618{
619 return MPBIOS_trigger(idx);
620}
621
622static int pin_2_irq(int idx, int apic, int pin)
623{
624 int irq, i;
625 int bus = mp_irqs[idx].mpc_srcbus;
626
627 /*
628 * Debugging check, we are in big trouble if this message pops up!
629 */
630 if (mp_irqs[idx].mpc_dstirq != pin)
631 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
632
633 switch (mp_bus_id_to_type[bus])
634 {
635 case MP_BUS_ISA: /* ISA pin */
636 case MP_BUS_EISA:
637 case MP_BUS_MCA:
638 {
639 irq = mp_irqs[idx].mpc_srcbusirq;
640 break;
641 }
642 case MP_BUS_PCI: /* PCI pin */
643 {
644 /*
645 * PCI IRQs are mapped in order
646 */
647 i = irq = 0;
648 while (i < apic)
649 irq += nr_ioapic_registers[i++];
650 irq += pin;
651 break;
652 }
653 default:
654 {
655 printk(KERN_ERR "unknown bus type %d.\n",bus);
656 irq = 0;
657 break;
658 }
659 }
660
661 /*
662 * PCI IRQ command line redirection. Yes, limits are hardcoded.
663 */
664 if ((pin >= 16) && (pin <= 23)) {
665 if (pirq_entries[pin-16] != -1) {
666 if (!pirq_entries[pin-16]) {
667 apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
668 } else {
669 irq = pirq_entries[pin-16];
670 apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
671 pin-16, irq);
672 }
673 }
674 }
675 return irq;
676}
677
678static inline int IO_APIC_irq_trigger(int irq)
679{
680 int apic, idx, pin;
681
682 for (apic = 0; apic < nr_ioapics; apic++) {
683 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
684 idx = find_irq_entry(apic,pin,mp_INT);
685 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
686 return irq_trigger(idx);
687 }
688 }
689 /*
690 * nonexistent IRQs are edge default
691 */
692 return 0;
693}
694
695/* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
6c231b7b 696u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1da177e4
LT		 697
698int assign_irq_vector(int irq)
699{
700 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
701
702 BUG_ON(irq >= NR_IRQ_VECTORS);
703 if (IO_APIC_VECTOR(irq) > 0)
704 return IO_APIC_VECTOR(irq);
705next:
706 current_vector += 8;
707 if (current_vector == IA32_SYSCALL_VECTOR)
708 goto next;
709
710 if (current_vector >= FIRST_SYSTEM_VECTOR) {
711 offset++;
712 if (!(offset%8))
713 return -ENOSPC;
714 current_vector = FIRST_DEVICE_VECTOR + offset;
715 }
716
717 vector_irq[current_vector] = irq;
718 if (irq != AUTO_ASSIGN)
719 IO_APIC_VECTOR(irq) = current_vector;
720
721 return current_vector;
722}
723
724extern void (*interrupt[NR_IRQS])(void);
725static struct hw_interrupt_type ioapic_level_type;
726static struct hw_interrupt_type ioapic_edge_type;
727
728#define IOAPIC_AUTO -1
729#define IOAPIC_EDGE 0
730#define IOAPIC_LEVEL 1
731
732static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
733{
734 if (use_pci_vector() && !platform_legacy_irq(irq)) {
735 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
736 trigger == IOAPIC_LEVEL)
737 irq_desc[vector].handler = &ioapic_level_type;
738 else
739 irq_desc[vector].handler = &ioapic_edge_type;
740 set_intr_gate(vector, interrupt[vector]);
741 } else {
742 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
743 trigger == IOAPIC_LEVEL)
744 irq_desc[irq].handler = &ioapic_level_type;
745 else
746 irq_desc[irq].handler = &ioapic_edge_type;
747 set_intr_gate(vector, interrupt[irq]);
748 }
749}
750
751static void __init setup_IO_APIC_irqs(void)
752{
753 struct IO_APIC_route_entry entry;
754 int apic, pin, idx, irq, first_notcon = 1, vector;
755 unsigned long flags;
756
757 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
758
759 for (apic = 0; apic < nr_ioapics; apic++) {
760 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
761
762 /*
763 * add it to the IO-APIC irq-routing table:
764 */
765 memset(&entry,0,sizeof(entry));
766
767 entry.delivery_mode = INT_DELIVERY_MODE;
768 entry.dest_mode = INT_DEST_MODE;
769 entry.mask = 0; /* enable IRQ */
770 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
771
772 idx = find_irq_entry(apic,pin,mp_INT);
773 if (idx == -1) {
774 if (first_notcon) {
775 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
776 first_notcon = 0;
777 } else
778 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
779 continue;
780 }
781
782 entry.trigger = irq_trigger(idx);
783 entry.polarity = irq_polarity(idx);
784
785 if (irq_trigger(idx)) {
786 entry.trigger = 1;
787 entry.mask = 1;
788 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
789 }
790
791 irq = pin_2_irq(idx, apic, pin);
792 add_pin_to_irq(irq, apic, pin);
793
794 if (!apic && !IO_APIC_IRQ(irq))
795 continue;
796
797 if (IO_APIC_IRQ(irq)) {
798 vector = assign_irq_vector(irq);
799 entry.vector = vector;
800
801 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
802 if (!apic && (irq < 16))
803 disable_8259A_irq(irq);
804 }
805 spin_lock_irqsave(&ioapic_lock, flags);
806 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
807 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
54d5d424 808 set_native_irq_info(irq, TARGET_CPUS);
1da177e4
LT		 809 spin_unlock_irqrestore(&ioapic_lock, flags);
810 }
811 }
812
813 if (!first_notcon)
814 apic_printk(APIC_VERBOSE," not connected.\n");
815}
816
817/*
818 * Set up the 8259A-master output pin as broadcast to all
819 * CPUs.
820 */
821static void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
822{
823 struct IO_APIC_route_entry entry;
824 unsigned long flags;
825
826 memset(&entry,0,sizeof(entry));
827
828 disable_8259A_irq(0);
829
830 /* mask LVT0 */
831 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
832
833 /*
834 * We use logical delivery to get the timer IRQ
835 * to the first CPU.
836 */
837 entry.dest_mode = INT_DEST_MODE;
838 entry.mask = 0; /* unmask IRQ now */
839 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
840 entry.delivery_mode = INT_DELIVERY_MODE;
841 entry.polarity = 0;
842 entry.trigger = 0;
843 entry.vector = vector;
844
845 /*
846 * The timer IRQ doesn't have to know that behind the
847 * scene we have a 8259A-master in AEOI mode ...
848 */
849 irq_desc[0].handler = &ioapic_edge_type;
850
851 /*
852 * Add it to the IO-APIC irq-routing table:
853 */
854 spin_lock_irqsave(&ioapic_lock, flags);
855 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
856 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
857 spin_unlock_irqrestore(&ioapic_lock, flags);
858
859 enable_8259A_irq(0);
860}
861
862void __init UNEXPECTED_IO_APIC(void)
863{
864}
865
866void __apicdebuginit print_IO_APIC(void)
867{
868 int apic, i;
869 union IO_APIC_reg_00 reg_00;
870 union IO_APIC_reg_01 reg_01;
871 union IO_APIC_reg_02 reg_02;
872 unsigned long flags;
873
874 if (apic_verbosity == APIC_QUIET)
875 return;
876
877 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
878 for (i = 0; i < nr_ioapics; i++)
879 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
880 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
881
882 /*
883 * We are a bit conservative about what we expect. We have to
884 * know about every hardware change ASAP.
885 */
886 printk(KERN_INFO "testing the IO APIC.......................\n");
887
888 for (apic = 0; apic < nr_ioapics; apic++) {
889
890 spin_lock_irqsave(&ioapic_lock, flags);
891 reg_00.raw = io_apic_read(apic, 0);
892 reg_01.raw = io_apic_read(apic, 1);
893 if (reg_01.bits.version >= 0x10)
894 reg_02.raw = io_apic_read(apic, 2);
895 spin_unlock_irqrestore(&ioapic_lock, flags);
896
897 printk("\n");
898 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
899 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
900 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
901 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
902 UNEXPECTED_IO_APIC();
903
904 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
905 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
906 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
907 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
908 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
909 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
910 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
911 (reg_01.bits.entries != 0x2E) &&
912 (reg_01.bits.entries != 0x3F) &&
913 (reg_01.bits.entries != 0x03)
914 )
915 UNEXPECTED_IO_APIC();
916
917 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
918 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
919 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
920 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
921 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
922 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
923 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
924 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
925 )
926 UNEXPECTED_IO_APIC();
927 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
928 UNEXPECTED_IO_APIC();
929
930 if (reg_01.bits.version >= 0x10) {
931 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
932 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
933 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
934 UNEXPECTED_IO_APIC();
935 }
936
937 printk(KERN_DEBUG ".... IRQ redirection table:\n");
938
939 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
940 " Stat Dest Deli Vect: \n");
941
942 for (i = 0; i <= reg_01.bits.entries; i++) {
943 struct IO_APIC_route_entry entry;
944
945 spin_lock_irqsave(&ioapic_lock, flags);
946 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
947 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
948 spin_unlock_irqrestore(&ioapic_lock, flags);
949
950 printk(KERN_DEBUG " %02x %03X %02X ",
951 i,
952 entry.dest.logical.logical_dest,
953 entry.dest.physical.physical_dest
954 );
955
956 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
957 entry.mask,
958 entry.trigger,
959 entry.irr,
960 entry.polarity,
961 entry.delivery_status,
962 entry.dest_mode,
963 entry.delivery_mode,
964 entry.vector
965 );
966 }
967 }
968 if (use_pci_vector())
969 printk(KERN_INFO "Using vector-based indexing\n");
970 printk(KERN_DEBUG "IRQ to pin mappings:\n");
971 for (i = 0; i < NR_IRQS; i++) {
972 struct irq_pin_list *entry = irq_2_pin + i;
973 if (entry->pin < 0)
974 continue;
975 if (use_pci_vector() && !platform_legacy_irq(i))
976 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
977 else
978 printk(KERN_DEBUG "IRQ%d ", i);
979 for (;;) {
980 printk("-> %d:%d", entry->apic, entry->pin);
981 if (!entry->next)
982 break;
983 entry = irq_2_pin + entry->next;
984 }
985 printk("\n");
986 }
987
988 printk(KERN_INFO ".................................... done.\n");
989
990 return;
991}
992
993#if 0
994
995static __apicdebuginit void print_APIC_bitfield (int base)
996{
997 unsigned int v;
998 int i, j;
999
1000 if (apic_verbosity == APIC_QUIET)
1001 return;
1002
1003 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1004 for (i = 0; i < 8; i++) {
1005 v = apic_read(base + i*0x10);
1006 for (j = 0; j < 32; j++) {
1007 if (v & (1<<j))
1008 printk("1");
1009 else
1010 printk("0");
1011 }
1012 printk("\n");
1013 }
1014}
1015
1016void __apicdebuginit print_local_APIC(void * dummy)
1017{
1018 unsigned int v, ver, maxlvt;
1019
1020 if (apic_verbosity == APIC_QUIET)
1021 return;
1022
1023 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1024 smp_processor_id(), hard_smp_processor_id());
1025 v = apic_read(APIC_ID);
1026 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1027 v = apic_read(APIC_LVR);
1028 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1029 ver = GET_APIC_VERSION(v);
1030 maxlvt = get_maxlvt();
1031
1032 v = apic_read(APIC_TASKPRI);
1033 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1034
5a40b7c2
AK		 1035 v = apic_read(APIC_ARBPRI);
1036 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1037 v & APIC_ARBPRI_MASK);
1038 v = apic_read(APIC_PROCPRI);
1039 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1da177e4
LT		 1040
1041 v = apic_read(APIC_EOI);
1042 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1043 v = apic_read(APIC_RRR);
1044 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1045 v = apic_read(APIC_LDR);
1046 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1047 v = apic_read(APIC_DFR);
1048 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1049 v = apic_read(APIC_SPIV);
1050 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1051
1052 printk(KERN_DEBUG "... APIC ISR field:\n");
1053 print_APIC_bitfield(APIC_ISR);
1054 printk(KERN_DEBUG "... APIC TMR field:\n");
1055 print_APIC_bitfield(APIC_TMR);
1056 printk(KERN_DEBUG "... APIC IRR field:\n");
1057 print_APIC_bitfield(APIC_IRR);
1058
5a40b7c2
AK		 1059 v = apic_read(APIC_ESR);
1060 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1da177e4
LT		 1061
1062 v = apic_read(APIC_ICR);
1063 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1064 v = apic_read(APIC_ICR2);
1065 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1066
1067 v = apic_read(APIC_LVTT);
1068 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1069
1070 if (maxlvt > 3) { /* PC is LVT#4. */
1071 v = apic_read(APIC_LVTPC);
1072 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1073 }
1074 v = apic_read(APIC_LVT0);
1075 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1076 v = apic_read(APIC_LVT1);
1077 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1078
1079 if (maxlvt > 2) { /* ERR is LVT#3. */
1080 v = apic_read(APIC_LVTERR);
1081 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1082 }
1083
1084 v = apic_read(APIC_TMICT);
1085 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1086 v = apic_read(APIC_TMCCT);
1087 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1088 v = apic_read(APIC_TDCR);
1089 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1090 printk("\n");
1091}
1092
1093void print_all_local_APICs (void)
1094{
1095 on_each_cpu(print_local_APIC, NULL, 1, 1);
1096}
1097
1098void __apicdebuginit print_PIC(void)
1099{
1da177e4
LT		 1100 unsigned int v;
1101 unsigned long flags;
1102
1103 if (apic_verbosity == APIC_QUIET)
1104 return;
1105
1106 printk(KERN_DEBUG "\nprinting PIC contents\n");
1107
1108 spin_lock_irqsave(&i8259A_lock, flags);
1109
1110 v = inb(0xa1) << 8 | inb(0x21);
1111 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1112
1113 v = inb(0xa0) << 8 | inb(0x20);
1114 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1115
1116 outb(0x0b,0xa0);
1117 outb(0x0b,0x20);
1118 v = inb(0xa0) << 8 | inb(0x20);
1119 outb(0x0a,0xa0);
1120 outb(0x0a,0x20);
1121
1122 spin_unlock_irqrestore(&i8259A_lock, flags);
1123
1124 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1125
1126 v = inb(0x4d1) << 8 | inb(0x4d0);
1127 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1128}
1129
1130#endif /* 0 */
1131
1132static void __init enable_IO_APIC(void)
1133{
1134 union IO_APIC_reg_01 reg_01;
1135 int i;
1136 unsigned long flags;
1137
1138 for (i = 0; i < PIN_MAP_SIZE; i++) {
1139 irq_2_pin[i].pin = -1;
1140 irq_2_pin[i].next = 0;
1141 }
1142 if (!pirqs_enabled)
1143 for (i = 0; i < MAX_PIRQS; i++)
1144 pirq_entries[i] = -1;
1145
1146 /*
1147 * The number of IO-APIC IRQ registers (== #pins):
1148 */
1149 for (i = 0; i < nr_ioapics; i++) {
1150 spin_lock_irqsave(&ioapic_lock, flags);
1151 reg_01.raw = io_apic_read(i, 1);
1152 spin_unlock_irqrestore(&ioapic_lock, flags);
1153 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1154 }
1155
1156 /*
1157 * Do not trust the IO-APIC being empty at bootup
1158 */
1159 clear_IO_APIC();
1160}
1161
1162/*
1163 * Not an __init, needed by the reboot code
1164 */
1165void disable_IO_APIC(void)
1166{
208fb931 1167 int pin;
1da177e4
LT		 1168 /*
1169 * Clear the IO-APIC before rebooting:
1170 */
1171 clear_IO_APIC();
1172
208fb931 1173 /*
0b968d23 1174 * If the i8259 is routed through an IOAPIC
208fb931 1175 * Put that IOAPIC in virtual wire mode
0b968d23 1176 * so legacy interrupts can be delivered.
208fb931
EB		 1177 */
1178 pin = find_isa_irq_pin(0, mp_ExtINT);
1179 if (pin != -1) {
1180 struct IO_APIC_route_entry entry;
1181 unsigned long flags;
1182
1183 memset(&entry, 0, sizeof(entry));
1184 entry.mask = 0; /* Enabled */
1185 entry.trigger = 0; /* Edge */
1186 entry.irr = 0;
1187 entry.polarity = 0; /* High */
1188 entry.delivery_status = 0;
1189 entry.dest_mode = 0; /* Physical */
1190 entry.delivery_mode = 7; /* ExtInt */
1191 entry.vector = 0;
1192 entry.dest.physical.physical_dest = 0;
1193
1194
1195 /*
1196 * Add it to the IO-APIC irq-routing table:
1197 */
1198 spin_lock_irqsave(&ioapic_lock, flags);
1199 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1200 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1201 spin_unlock_irqrestore(&ioapic_lock, flags);
1202 }
1203
1204 disconnect_bsp_APIC(pin != -1);
1da177e4
LT		 1205}
1206
1207/*
1208 * function to set the IO-APIC physical IDs based on the
1209 * values stored in the MPC table.
1210 *
1211 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1212 */
1213
1214static void __init setup_ioapic_ids_from_mpc (void)
1215{
1216 union IO_APIC_reg_00 reg_00;
1217 int apic;
1218 int i;
1219 unsigned char old_id;
1220 unsigned long flags;
1221
1222 /*
1223 * Set the IOAPIC ID to the value stored in the MPC table.
1224 */
1225 for (apic = 0; apic < nr_ioapics; apic++) {
1226
1227 /* Read the register 0 value */
1228 spin_lock_irqsave(&ioapic_lock, flags);
1229 reg_00.raw = io_apic_read(apic, 0);
1230 spin_unlock_irqrestore(&ioapic_lock, flags);
1231
1232 old_id = mp_ioapics[apic].mpc_apicid;
1233
1234
1235 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1236
1237
1238 /*
1239 * We need to adjust the IRQ routing table
1240 * if the ID changed.
1241 */
1242 if (old_id != mp_ioapics[apic].mpc_apicid)
1243 for (i = 0; i < mp_irq_entries; i++)
1244 if (mp_irqs[i].mpc_dstapic == old_id)
1245 mp_irqs[i].mpc_dstapic
1246 = mp_ioapics[apic].mpc_apicid;
1247
1248 /*
1249 * Read the right value from the MPC table and
1250 * write it into the ID register.
1251 */
1252 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1253 mp_ioapics[apic].mpc_apicid);
1254
1255 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1256 spin_lock_irqsave(&ioapic_lock, flags);
1257 io_apic_write(apic, 0, reg_00.raw);
1258 spin_unlock_irqrestore(&ioapic_lock, flags);
1259
1260 /*
1261 * Sanity check
1262 */
1263 spin_lock_irqsave(&ioapic_lock, flags);
1264 reg_00.raw = io_apic_read(apic, 0);
1265 spin_unlock_irqrestore(&ioapic_lock, flags);
1266 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1267 printk("could not set ID!\n");
1268 else
1269 apic_printk(APIC_VERBOSE," ok.\n");
1270 }
1271}
1272
1273/*
1274 * There is a nasty bug in some older SMP boards, their mptable lies
1275 * about the timer IRQ. We do the following to work around the situation:
1276 *
1277 * - timer IRQ defaults to IO-APIC IRQ
1278 * - if this function detects that timer IRQs are defunct, then we fall
1279 * back to ISA timer IRQs
1280 */
1281static int __init timer_irq_works(void)
1282{
1283 unsigned long t1 = jiffies;
1284
1285 local_irq_enable();
1286 /* Let ten ticks pass... */
1287 mdelay((10 * 1000) / HZ);
1288
1289 /*
1290 * Expect a few ticks at least, to be sure some possible
1291 * glue logic does not lock up after one or two first
1292 * ticks in a non-ExtINT mode. Also the local APIC
1293 * might have cached one ExtINT interrupt. Finally, at
1294 * least one tick may be lost due to delays.
1295 */
1296
1297 /* jiffies wrap? */
1298 if (jiffies - t1 > 4)
1299 return 1;
1300 return 0;
1301}
1302
1303/*
1304 * In the SMP+IOAPIC case it might happen that there are an unspecified
1305 * number of pending IRQ events unhandled. These cases are very rare,
1306 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1307 * better to do it this way as thus we do not have to be aware of
1308 * 'pending' interrupts in the IRQ path, except at this point.
1309 */
1310/*
1311 * Edge triggered needs to resend any interrupt
1312 * that was delayed but this is now handled in the device
1313 * independent code.
1314 */
1315
1316/*
1317 * Starting up a edge-triggered IO-APIC interrupt is
1318 * nasty - we need to make sure that we get the edge.
1319 * If it is already asserted for some reason, we need
1320 * return 1 to indicate that is was pending.
1321 *
1322 * This is not complete - we should be able to fake
1323 * an edge even if it isn't on the 8259A...
1324 */
1325
1326static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1327{
1328 int was_pending = 0;
1329 unsigned long flags;
1330
1331 spin_lock_irqsave(&ioapic_lock, flags);
1332 if (irq < 16) {
1333 disable_8259A_irq(irq);
1334 if (i8259A_irq_pending(irq))
1335 was_pending = 1;
1336 }
1337 __unmask_IO_APIC_irq(irq);
1338 spin_unlock_irqrestore(&ioapic_lock, flags);
1339
1340 return was_pending;
1341}
1342
1343/*
1344 * Once we have recorded IRQ_PENDING already, we can mask the
1345 * interrupt for real. This prevents IRQ storms from unhandled
1346 * devices.
1347 */
1348static void ack_edge_ioapic_irq(unsigned int irq)
1349{
54d5d424 1350 move_irq(irq);
1da177e4
LT		 1351 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1352 == (IRQ_PENDING | IRQ_DISABLED))
1353 mask_IO_APIC_irq(irq);
1354 ack_APIC_irq();
1355}
1356
1357/*
1358 * Level triggered interrupts can just be masked,
1359 * and shutting down and starting up the interrupt
1360 * is the same as enabling and disabling them -- except
1361 * with a startup need to return a "was pending" value.
1362 *
1363 * Level triggered interrupts are special because we
1364 * do not touch any IO-APIC register while handling
1365 * them. We ack the APIC in the end-IRQ handler, not
1366 * in the start-IRQ-handler. Protection against reentrance
1367 * from the same interrupt is still provided, both by the
1368 * generic IRQ layer and by the fact that an unacked local
1369 * APIC does not accept IRQs.
1370 */
1371static unsigned int startup_level_ioapic_irq (unsigned int irq)
1372{
1373 unmask_IO_APIC_irq(irq);
1374
1375 return 0; /* don't check for pending */
1376}
1377
1378static void end_level_ioapic_irq (unsigned int irq)
1379{
54d5d424 1380 move_irq(irq);
1da177e4
LT		 1381 ack_APIC_irq();
1382}
1383
1da177e4
LT		 1384#ifdef CONFIG_PCI_MSI
1385static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1386{
1387 int irq = vector_to_irq(vector);
1388
1389 return startup_edge_ioapic_irq(irq);
1390}
1391
1392static void ack_edge_ioapic_vector(unsigned int vector)
1393{
1394 int irq = vector_to_irq(vector);
1395
54d5d424 1396 move_native_irq(vector);
1da177e4
LT		 1397 ack_edge_ioapic_irq(irq);
1398}
1399
1400static unsigned int startup_level_ioapic_vector (unsigned int vector)
1401{
1402 int irq = vector_to_irq(vector);
1403
1404 return startup_level_ioapic_irq (irq);
1405}
1406
1407static void end_level_ioapic_vector (unsigned int vector)
1408{
1409 int irq = vector_to_irq(vector);
1410
54d5d424 1411 move_native_irq(vector);
1da177e4
LT		 1412 end_level_ioapic_irq(irq);
1413}
1414
1415static void mask_IO_APIC_vector (unsigned int vector)
1416{
1417 int irq = vector_to_irq(vector);
1418
1419 mask_IO_APIC_irq(irq);
1420}
1421
1422static void unmask_IO_APIC_vector (unsigned int vector)
1423{
1424 int irq = vector_to_irq(vector);
1425
1426 unmask_IO_APIC_irq(irq);
1427}
1428
54d5d424 1429#ifdef CONFIG_SMP
1da177e4
LT		 1430static void set_ioapic_affinity_vector (unsigned int vector,
1431 cpumask_t cpu_mask)
1432{
1433 int irq = vector_to_irq(vector);
1434
54d5d424 1435 set_native_irq_info(vector, cpu_mask);
1da177e4
LT		 1436 set_ioapic_affinity_irq(irq, cpu_mask);
1437}
54d5d424
AR		 1438#endif // CONFIG_SMP
1439#endif // CONFIG_PCI_MSI
1da177e4
LT		 1440
1441/*
1442 * Level and edge triggered IO-APIC interrupts need different handling,
1443 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1444 * handled with the level-triggered descriptor, but that one has slightly
1445 * more overhead. Level-triggered interrupts cannot be handled with the
1446 * edge-triggered handler, without risking IRQ storms and other ugly
1447 * races.
1448 */
1449
6c231b7b 1450static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1da177e4
LT		 1451 .typename = "IO-APIC-edge",
1452 .startup = startup_edge_ioapic,
1453 .shutdown = shutdown_edge_ioapic,
1454 .enable = enable_edge_ioapic,
1455 .disable = disable_edge_ioapic,
1456 .ack = ack_edge_ioapic,
1457 .end = end_edge_ioapic,
54d5d424 1458#ifdef CONFIG_SMP
1da177e4 1459 .set_affinity = set_ioapic_affinity,
54d5d424 1460#endif
1da177e4
LT		 1461};
1462
6c231b7b 1463static struct hw_interrupt_type ioapic_level_type __read_mostly = {
1da177e4
LT		 1464 .typename = "IO-APIC-level",
1465 .startup = startup_level_ioapic,
1466 .shutdown = shutdown_level_ioapic,
1467 .enable = enable_level_ioapic,
1468 .disable = disable_level_ioapic,
1469 .ack = mask_and_ack_level_ioapic,
1470 .end = end_level_ioapic,
54d5d424 1471#ifdef CONFIG_SMP
1da177e4 1472 .set_affinity = set_ioapic_affinity,
54d5d424 1473#endif
1da177e4
LT		 1474};
1475
1476static inline void init_IO_APIC_traps(void)
1477{
1478 int irq;
1479
1480 /*
1481 * NOTE! The local APIC isn't very good at handling
1482 * multiple interrupts at the same interrupt level.
1483 * As the interrupt level is determined by taking the
1484 * vector number and shifting that right by 4, we
1485 * want to spread these out a bit so that they don't
1486 * all fall in the same interrupt level.
1487 *
1488 * Also, we've got to be careful not to trash gate
1489 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1490 */
1491 for (irq = 0; irq < NR_IRQS ; irq++) {
1492 int tmp = irq;
1493 if (use_pci_vector()) {
1494 if (!platform_legacy_irq(tmp))
1495 if ((tmp = vector_to_irq(tmp)) == -1)
1496 continue;
1497 }
1498 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1499 /*
1500 * Hmm.. We don't have an entry for this,
1501 * so default to an old-fashioned 8259
1502 * interrupt if we can..
1503 */
1504 if (irq < 16)
1505 make_8259A_irq(irq);
1506 else
1507 /* Strange. Oh, well.. */
1508 irq_desc[irq].handler = &no_irq_type;
1509 }
1510 }
1511}
1512
1513static void enable_lapic_irq (unsigned int irq)
1514{
1515 unsigned long v;
1516
1517 v = apic_read(APIC_LVT0);
1518 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1519}
1520
1521static void disable_lapic_irq (unsigned int irq)
1522{
1523 unsigned long v;
1524
1525 v = apic_read(APIC_LVT0);
1526 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1527}
1528
1529static void ack_lapic_irq (unsigned int irq)
1530{
1531 ack_APIC_irq();
1532}
1533
1534static void end_lapic_irq (unsigned int i) { /* nothing */ }
1535
6c231b7b 1536static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1da177e4
LT		 1537 .typename = "local-APIC-edge",
1538 .startup = NULL, /* startup_irq() not used for IRQ0 */
1539 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1540 .enable = enable_lapic_irq,
1541 .disable = disable_lapic_irq,
1542 .ack = ack_lapic_irq,
1543 .end = end_lapic_irq,
1544};
1545
1546static void setup_nmi (void)
1547{
1548 /*
1549 * Dirty trick to enable the NMI watchdog ...
1550 * We put the 8259A master into AEOI mode and
1551 * unmask on all local APICs LVT0 as NMI.
1552 *
1553 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1554 * is from Maciej W. Rozycki - so we do not have to EOI from
1555 * the NMI handler or the timer interrupt.
1556 */
1557 printk(KERN_INFO "activating NMI Watchdog ...");
1558
1559 enable_NMI_through_LVT0(NULL);
1560
1561 printk(" done.\n");
1562}
1563
1564/*
1565 * This looks a bit hackish but it's about the only one way of sending
1566 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1567 * not support the ExtINT mode, unfortunately. We need to send these
1568 * cycles as some i82489DX-based boards have glue logic that keeps the
1569 * 8259A interrupt line asserted until INTA. --macro
1570 */
1571static inline void unlock_ExtINT_logic(void)
1572{
1573 int pin, i;
1574 struct IO_APIC_route_entry entry0, entry1;
1575 unsigned char save_control, save_freq_select;
1576 unsigned long flags;
1577
1578 pin = find_isa_irq_pin(8, mp_INT);
1579 if (pin == -1)
1580 return;
1581
1582 spin_lock_irqsave(&ioapic_lock, flags);
1583 *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1584 *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1585 spin_unlock_irqrestore(&ioapic_lock, flags);
1586 clear_IO_APIC_pin(0, pin);
1587
1588 memset(&entry1, 0, sizeof(entry1));
1589
1590 entry1.dest_mode = 0; /* physical delivery */
1591 entry1.mask = 0; /* unmask IRQ now */
1592 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1593 entry1.delivery_mode = dest_ExtINT;
1594 entry1.polarity = entry0.polarity;
1595 entry1.trigger = 0;
1596 entry1.vector = 0;
1597
1598 spin_lock_irqsave(&ioapic_lock, flags);
1599 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1600 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1601 spin_unlock_irqrestore(&ioapic_lock, flags);
1602
1603 save_control = CMOS_READ(RTC_CONTROL);
1604 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1605 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1606 RTC_FREQ_SELECT);
1607 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1608
1609 i = 100;
1610 while (i-- > 0) {
1611 mdelay(10);
1612 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1613 i -= 10;
1614 }
1615
1616 CMOS_WRITE(save_control, RTC_CONTROL);
1617 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1618 clear_IO_APIC_pin(0, pin);
1619
1620 spin_lock_irqsave(&ioapic_lock, flags);
1621 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1622 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1623 spin_unlock_irqrestore(&ioapic_lock, flags);
1624}
1625
1626/*
1627 * This code may look a bit paranoid, but it's supposed to cooperate with
1628 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1629 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1630 * fanatically on his truly buggy board.
1631 */
1632static inline void check_timer(void)
1633{
1634 int pin1, pin2;
1635 int vector;
1636
1637 /*
1638 * get/set the timer IRQ vector:
1639 */
1640 disable_8259A_irq(0);
1641 vector = assign_irq_vector(0);
1642 set_intr_gate(vector, interrupt[0]);
1643
1644 /*
1645 * Subtle, code in do_timer_interrupt() expects an AEOI
1646 * mode for the 8259A whenever interrupts are routed
1647 * through I/O APICs. Also IRQ0 has to be enabled in
1648 * the 8259A which implies the virtual wire has to be
1649 * disabled in the local APIC.
1650 */
1651 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1652 init_8259A(1);
1653 enable_8259A_irq(0);
1654
1655 pin1 = find_isa_irq_pin(0, mp_INT);
1656 pin2 = find_isa_irq_pin(0, mp_ExtINT);
1657
1658 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1659
1660 if (pin1 != -1) {
1661 /*
1662 * Ok, does IRQ0 through the IOAPIC work?
1663 */
1664 unmask_IO_APIC_irq(0);
14d98cad 1665 if (!no_timer_check && timer_irq_works()) {
1da177e4
LT		 1666 nmi_watchdog_default();
1667 if (nmi_watchdog == NMI_IO_APIC) {
1668 disable_8259A_irq(0);
1669 setup_nmi();
1670 enable_8259A_irq(0);
1da177e4 1671 }
66759a01
CE		 1672 if (disable_timer_pin_1 > 0)
1673 clear_IO_APIC_pin(0, pin1);
1da177e4
LT		 1674 return;
1675 }
1676 clear_IO_APIC_pin(0, pin1);
1677 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1678 }
1679
1680 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1681 if (pin2 != -1) {
1682 apic_printk(APIC_VERBOSE,"\n..... (found pin %d) ...", pin2);
1683 /*
1684 * legacy devices should be connected to IO APIC #0
1685 */
1686 setup_ExtINT_IRQ0_pin(pin2, vector);
1687 if (timer_irq_works()) {
1688 printk("works.\n");
1689 nmi_watchdog_default();
1690 if (nmi_watchdog == NMI_IO_APIC) {
1691 setup_nmi();
1da177e4
LT		 1692 }
1693 return;
1694 }
1695 /*
1696 * Cleanup, just in case ...
1697 */
1698 clear_IO_APIC_pin(0, pin2);
1699 }
1700 printk(" failed.\n");
1701
1702 if (nmi_watchdog) {
1703 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1704 nmi_watchdog = 0;
1705 }
1706
1707 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1708
1709 disable_8259A_irq(0);
1710 irq_desc[0].handler = &lapic_irq_type;
1711 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1712 enable_8259A_irq(0);
1713
1714 if (timer_irq_works()) {
1715 apic_printk(APIC_QUIET, " works.\n");
1716 return;
1717 }
1718 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1719 apic_printk(APIC_VERBOSE," failed.\n");
1720
1721 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1722
1723 init_8259A(0);
1724 make_8259A_irq(0);
1725 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1726
1727 unlock_ExtINT_logic();
1728
1729 if (timer_irq_works()) {
1730 apic_printk(APIC_VERBOSE," works.\n");
1731 return;
1732 }
1733 apic_printk(APIC_VERBOSE," failed :(.\n");
1734 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1735}
1736
14d98cad
AK		 1737static int __init notimercheck(char *s)
1738{
1739 no_timer_check = 1;
1740 return 1;
1741}
1742__setup("no_timer_check", notimercheck);
1743
1da177e4
LT		 1744/*
1745 *
1746 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1747 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1748 * Linux doesn't really care, as it's not actually used
1749 * for any interrupt handling anyway.
1750 */
1751#define PIC_IRQS (1<<2)
1752
1753void __init setup_IO_APIC(void)
1754{
1755 enable_IO_APIC();
1756
1757 if (acpi_ioapic)
1758 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1759 else
1760 io_apic_irqs = ~PIC_IRQS;
1761
1762 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1763
1764 /*
1765 * Set up the IO-APIC IRQ routing table.
1766 */
1767 if (!acpi_ioapic)
1768 setup_ioapic_ids_from_mpc();
1769 sync_Arb_IDs();
1770 setup_IO_APIC_irqs();
1771 init_IO_APIC_traps();
1772 check_timer();
1773 if (!acpi_ioapic)
1774 print_IO_APIC();
1775}
1776
1777struct sysfs_ioapic_data {
1778 struct sys_device dev;
1779 struct IO_APIC_route_entry entry[0];
1780};
1781static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1782
0b9c33a7 1783static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4
LT		 1784{
1785 struct IO_APIC_route_entry *entry;
1786 struct sysfs_ioapic_data *data;
1787 unsigned long flags;
1788 int i;
1789
1790 data = container_of(dev, struct sysfs_ioapic_data, dev);
1791 entry = data->entry;
1792 spin_lock_irqsave(&ioapic_lock, flags);
1793 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1794 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
1795 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
1796 }
1797 spin_unlock_irqrestore(&ioapic_lock, flags);
1798
1799 return 0;
1800}
1801
1802static int ioapic_resume(struct sys_device *dev)
1803{
1804 struct IO_APIC_route_entry *entry;
1805 struct sysfs_ioapic_data *data;
1806 unsigned long flags;
1807 union IO_APIC_reg_00 reg_00;
1808 int i;
1809
1810 data = container_of(dev, struct sysfs_ioapic_data, dev);
1811 entry = data->entry;
1812
1813 spin_lock_irqsave(&ioapic_lock, flags);
1814 reg_00.raw = io_apic_read(dev->id, 0);
1815 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1816 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1817 io_apic_write(dev->id, 0, reg_00.raw);
1818 }
1819 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1820 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
1821 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
1822 }
1823 spin_unlock_irqrestore(&ioapic_lock, flags);
1824
1825 return 0;
1826}
1827
1828static struct sysdev_class ioapic_sysdev_class = {
1829 set_kset_name("ioapic"),
1830 .suspend = ioapic_suspend,
1831 .resume = ioapic_resume,
1832};
1833
1834static int __init ioapic_init_sysfs(void)
1835{
1836 struct sys_device * dev;
1837 int i, size, error = 0;
1838
1839 error = sysdev_class_register(&ioapic_sysdev_class);
1840 if (error)
1841 return error;
1842
1843 for (i = 0; i < nr_ioapics; i++ ) {
1844 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1845 * sizeof(struct IO_APIC_route_entry);
1846 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1847 if (!mp_ioapic_data[i]) {
1848 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1849 continue;
1850 }
1851 memset(mp_ioapic_data[i], 0, size);
1852 dev = &mp_ioapic_data[i]->dev;
1853 dev->id = i;
1854 dev->cls = &ioapic_sysdev_class;
1855 error = sysdev_register(dev);
1856 if (error) {
1857 kfree(mp_ioapic_data[i]);
1858 mp_ioapic_data[i] = NULL;
1859 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1860 continue;
1861 }
1862 }
1863
1864 return 0;
1865}
1866
1867device_initcall(ioapic_init_sysfs);
1868
1869/* --------------------------------------------------------------------------
1870 ACPI-based IOAPIC Configuration
1871 -------------------------------------------------------------------------- */
1872
888ba6c6 1873#ifdef CONFIG_ACPI
1da177e4
LT		 1874
1875#define IO_APIC_MAX_ID 0xFE
1876
1da177e4
LT		 1877int __init io_apic_get_version (int ioapic)
1878{
1879 union IO_APIC_reg_01 reg_01;
1880 unsigned long flags;
1881
1882 spin_lock_irqsave(&ioapic_lock, flags);
1883 reg_01.raw = io_apic_read(ioapic, 1);
1884 spin_unlock_irqrestore(&ioapic_lock, flags);
1885
1886 return reg_01.bits.version;
1887}
1888
1889
1890int __init io_apic_get_redir_entries (int ioapic)
1891{
1892 union IO_APIC_reg_01 reg_01;
1893 unsigned long flags;
1894
1895 spin_lock_irqsave(&ioapic_lock, flags);
1896 reg_01.raw = io_apic_read(ioapic, 1);
1897 spin_unlock_irqrestore(&ioapic_lock, flags);
1898
1899 return reg_01.bits.entries;
1900}
1901
1902
1903int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
1904{
1905 struct IO_APIC_route_entry entry;
1906 unsigned long flags;
1907
1908 if (!IO_APIC_IRQ(irq)) {
1909 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1910 ioapic);
1911 return -EINVAL;
1912 }
1913
1914 /*
1915 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1916 * Note that we mask (disable) IRQs now -- these get enabled when the
1917 * corresponding device driver registers for this IRQ.
1918 */
1919
1920 memset(&entry,0,sizeof(entry));
1921
1922 entry.delivery_mode = INT_DELIVERY_MODE;
1923 entry.dest_mode = INT_DEST_MODE;
1924 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1925 entry.trigger = edge_level;
1926 entry.polarity = active_high_low;
1927 entry.mask = 1; /* Disabled (masked) */
1928
1929 /*
1930 * IRQs < 16 are already in the irq_2_pin[] map
1931 */
1932 if (irq >= 16)
1933 add_pin_to_irq(irq, ioapic, pin);
1934
1935 entry.vector = assign_irq_vector(irq);
1936
1937 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1938 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1939 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1940 edge_level, active_high_low);
1941
1942 ioapic_register_intr(irq, entry.vector, edge_level);
1943
1944 if (!ioapic && (irq < 16))
1945 disable_8259A_irq(irq);
1946
1947 spin_lock_irqsave(&ioapic_lock, flags);
1948 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
1949 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
54d5d424 1950 set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
1da177e4
LT		 1951 spin_unlock_irqrestore(&ioapic_lock, flags);
1952
1953 return 0;
1954}
1955
888ba6c6 1956#endif /* CONFIG_ACPI */
1da177e4
LT		 1957
1958
1959/*
1960 * This function currently is only a helper for the i386 smp boot process where
1961 * we need to reprogram the ioredtbls to cater for the cpus which have come online
1962 * so mask in all cases should simply be TARGET_CPUS
1963 */
54d5d424 1964#ifdef CONFIG_SMP
1da177e4
LT		 1965void __init setup_ioapic_dest(void)
1966{
1967 int pin, ioapic, irq, irq_entry;
1968
1969 if (skip_ioapic_setup == 1)
1970 return;
1971
1972 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
1973 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
1974 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
1975 if (irq_entry == -1)
1976 continue;
1977 irq = pin_2_irq(irq_entry, ioapic, pin);
1978 set_ioapic_affinity_irq(irq, TARGET_CPUS);
1979 }
1980
1981 }
1982}
54d5d424 1983#endif
kernel source for telekom puls (alcatel/mediatek)