[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kernel / pci-dma.c

#include <linux/dma-mapping.h>
#include <linux/dma-debug.h>
#include <linux/dmar.h>
#include <linux/bootmem.h>
#include <linux/gfp.h>
#include <linux/pci.h>
#include <linux/kmemleak.h>

#include <asm/proto.h>
#include <asm/dma.h>
#include <asm/iommu.h>
#include <asm/gart.h>
#include <asm/calgary.h>
#include <asm/amd_iommu.h>
#include <asm/x86_init.h>

static int forbid_dac __read_mostly;

struct dma_map_ops *dma_ops = &nommu_dma_ops;
EXPORT_SYMBOL(dma_ops);

static int iommu_sac_force __read_mostly;

#ifdef CONFIG_IOMMU_DEBUG
int panic_on_overflow __read_mostly = 1;
int force_iommu __read_mostly = 1;
#else
int panic_on_overflow __read_mostly = 0;
int force_iommu __read_mostly = 0;
#endif

int iommu_merge __read_mostly = 0;

int no_iommu __read_mostly;
/* Set this to 1 if there is a HW IOMMU in the system */
int iommu_detected __read_mostly = 0;

/*
 * This variable becomes 1 if iommu=pt is passed on the kernel command line.
 * If this variable is 1, IOMMU implementations do no DMA translation for
 * devices and allow every device to access to whole physical memory. This is
 * useful if a user wants to use an IOMMU only for KVM device assignment to
 * guests and not for driver dma translation.
 */
int iommu_pass_through __read_mostly;

/* Dummy device used for NULL arguments (normally ISA). */
struct device x86_dma_fallback_dev = {
	.init_name = "fallback device",
	.coherent_dma_mask = ISA_DMA_BIT_MASK,
	.dma_mask = &x86_dma_fallback_dev.coherent_dma_mask,
};
EXPORT_SYMBOL(x86_dma_fallback_dev);

/* Number of entries preallocated for DMA-API debugging */
#define PREALLOC_DMA_DEBUG_ENTRIES       32768

int dma_set_mask(struct device *dev, u64 mask)
{
	if (!dev->dma_mask || !dma_supported(dev, mask))
		return -EIO;

	*dev->dma_mask = mask;

	return 0;
}
EXPORT_SYMBOL(dma_set_mask);

#if defined(CONFIG_X86_64) && !defined(CONFIG_NUMA)
static __initdata void *dma32_bootmem_ptr;
static unsigned long dma32_bootmem_size __initdata = (128ULL<<20);

static int __init parse_dma32_size_opt(char *p)
{
	if (!p)
		return -EINVAL;
	dma32_bootmem_size = memparse(p, &p);
	return 0;
}
early_param("dma32_size", parse_dma32_size_opt);

void __init dma32_reserve_bootmem(void)
{
	unsigned long size, align;
	if (max_pfn <= MAX_DMA32_PFN)
		return;

	/*
	 * check aperture_64.c allocate_aperture() for reason about
	 * using 512M as goal
	 */
	align = 64ULL<<20;
	size = roundup(dma32_bootmem_size, align);
	dma32_bootmem_ptr = __alloc_bootmem_nopanic(size, align,
				 512ULL<<20);
	/*
	 * Kmemleak should not scan this block as it may not be mapped via the
	 * kernel direct mapping.
	 */
	kmemleak_ignore(dma32_bootmem_ptr);
	if (dma32_bootmem_ptr)
		dma32_bootmem_size = size;
	else
		dma32_bootmem_size = 0;
}
static void __init dma32_free_bootmem(void)
{

	if (max_pfn <= MAX_DMA32_PFN)
		return;

	if (!dma32_bootmem_ptr)
		return;

	free_bootmem(__pa(dma32_bootmem_ptr), dma32_bootmem_size);

	dma32_bootmem_ptr = NULL;
	dma32_bootmem_size = 0;
}
#else
void __init dma32_reserve_bootmem(void)
{
}
static void __init dma32_free_bootmem(void)
{
}

#endif

void __init pci_iommu_alloc(void)
{
	/* free the range so iommu could get some range less than 4G */
	dma32_free_bootmem();

	if (pci_swiotlb_detect())
		goto out;

	gart_iommu_hole_init();

	detect_calgary();

	detect_intel_iommu();

	/* needs to be called after gart_iommu_hole_init */
	amd_iommu_detect();
out:
	pci_swiotlb_init();
}

void *dma_generic_alloc_coherent(struct device *dev, size_t size,
				 dma_addr_t *dma_addr, gfp_t flag)
{
	unsigned long dma_mask;
	struct page *page;
	dma_addr_t addr;

	dma_mask = dma_alloc_coherent_mask(dev, flag);

	flag |= __GFP_ZERO;
again:
	page = alloc_pages_node(dev_to_node(dev), flag, get_order(size));
	if (!page)
		return NULL;

	addr = page_to_phys(page);
	if (addr + size > dma_mask) {
		__free_pages(page, get_order(size));

		if (dma_mask < DMA_BIT_MASK(32) && !(flag & GFP_DMA)) {
			flag = (flag & ~GFP_DMA32) | GFP_DMA;
			goto again;
		}

		return NULL;
	}

	*dma_addr = addr;
	return page_address(page);
}

/*
 * See <Documentation/x86_64/boot-options.txt> for the iommu kernel parameter
 * documentation.
 */
static __init int iommu_setup(char *p)
{
	iommu_merge = 1;

	if (!p)
		return -EINVAL;

	while (*p) {
		if (!strncmp(p, "off", 3))
			no_iommu = 1;
		/* gart_parse_options has more force support */
		if (!strncmp(p, "force", 5))
			force_iommu = 1;
		if (!strncmp(p, "noforce", 7)) {
			iommu_merge = 0;
			force_iommu = 0;
		}

		if (!strncmp(p, "biomerge", 8)) {
			iommu_merge = 1;
			force_iommu = 1;
		}
		if (!strncmp(p, "panic", 5))
			panic_on_overflow = 1;
		if (!strncmp(p, "nopanic", 7))
			panic_on_overflow = 0;
		if (!strncmp(p, "merge", 5)) {
			iommu_merge = 1;
			force_iommu = 1;
		}
		if (!strncmp(p, "nomerge", 7))
			iommu_merge = 0;
		if (!strncmp(p, "forcesac", 8))
			iommu_sac_force = 1;
		if (!strncmp(p, "allowdac", 8))
			forbid_dac = 0;
		if (!strncmp(p, "nodac", 5))
			forbid_dac = 1;
		if (!strncmp(p, "usedac", 6)) {
			forbid_dac = -1;
			return 1;
		}
#ifdef CONFIG_SWIOTLB
		if (!strncmp(p, "soft", 4))
			swiotlb = 1;
#endif
		if (!strncmp(p, "pt", 2))
			iommu_pass_through = 1;

		gart_parse_options(p);

#ifdef CONFIG_CALGARY_IOMMU
		if (!strncmp(p, "calgary", 7))
			use_calgary = 1;
#endif /* CONFIG_CALGARY_IOMMU */

		p += strcspn(p, ",");
		if (*p == ',')
			++p;
	}
	return 0;
}
early_param("iommu", iommu_setup);

int dma_supported(struct device *dev, u64 mask)
{
	struct dma_map_ops *ops = get_dma_ops(dev);

#ifdef CONFIG_PCI
	if (mask > 0xffffffff && forbid_dac > 0) {
		dev_info(dev, "PCI: Disallowing DAC for device\n");
		return 0;
	}
#endif

	if (ops->dma_supported)
		return ops->dma_supported(dev, mask);

	/* Copied from i386. Doesn't make much sense, because it will
	   only work for pci_alloc_coherent.
	   The caller just has to use GFP_DMA in this case. */
	if (mask < DMA_BIT_MASK(24))
		return 0;

	/* Tell the device to use SAC when IOMMU force is on.  This
	   allows the driver to use cheaper accesses in some cases.

	   Problem with this is that if we overflow the IOMMU area and
	   return DAC as fallback address the device may not handle it
	   correctly.

	   As a special case some controllers have a 39bit address
	   mode that is as efficient as 32bit (aic79xx). Don't force
	   SAC for these.  Assume all masks <= 40 bits are of this
	   type. Normally this doesn't make any difference, but gives
	   more gentle handling of IOMMU overflow. */
	if (iommu_sac_force && (mask >= DMA_BIT_MASK(40))) {
		dev_info(dev, "Force SAC with mask %Lx\n", mask);
		return 0;
	}

	return 1;
}
EXPORT_SYMBOL(dma_supported);

static int __init pci_iommu_init(void)
{
	dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);

#ifdef CONFIG_PCI
	dma_debug_add_bus(&pci_bus_type);
#endif
	x86_init.iommu.iommu_init();

	if (swiotlb) {
		printk(KERN_INFO "PCI-DMA: "
		       "Using software bounce buffering for IO (SWIOTLB)\n");
		swiotlb_print_info();
	} else
		swiotlb_free();

	return 0;
}
/* Must execute after PCI subsystem */
rootfs_initcall(pci_iommu_init);

#ifdef CONFIG_PCI
/* Many VIA bridges seem to corrupt data for DAC. Disable it here */

static __devinit void via_no_dac(struct pci_dev *dev)
{
	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && forbid_dac == 0) {
		dev_info(&dev->dev, "disabling DAC on VIA PCI bridge\n");
		forbid_dac = 1;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID, via_no_dac);
#endif
Commit	Line	Data
459121c9	1	#include <linux/dma-mapping.h>
2118d0c5	2	#include <linux/dma-debug.h>
cb5867a5	3	#include <linux/dmar.h>
116890d5	4	#include <linux/bootmem.h>
5a0e3ad6	5	#include <linux/gfp.h>
bca5c096	6	#include <linux/pci.h>
acde31dc	7	#include <linux/kmemleak.h>
cb5867a5	8
116890d5 GC	9	#include <asm/proto.h>
116890d5 GC	10	#include <asm/dma.h>
46a7fa27	11	#include <asm/iommu.h>
1d9b16d1	12	#include <asm/gart.h>
cb5867a5	13	#include <asm/calgary.h>
a69ca340	14	#include <asm/amd_iommu.h>
b4941a9a	15	#include <asm/x86_init.h>
459121c9	16
3b15e581 FY	17	static int forbid_dac __read_mostly;
3b15e581 FY	18
a3b28ee1	19	struct dma_map_ops *dma_ops = &nommu_dma_ops;
85c246ee GC	20	EXPORT_SYMBOL(dma_ops);
85c246ee GC	21
b4cdc430	22	static int iommu_sac_force __read_mostly;
8e0c3797	23
f9c258de GC	24	#ifdef CONFIG_IOMMU_DEBUG
	25	int panic_on_overflow __read_mostly = 1;
	26	int force_iommu __read_mostly = 1;
	27	#else
	28	int panic_on_overflow __read_mostly = 0;
	29	int force_iommu __read_mostly = 0;
	30	#endif
	31
fae9a0d8 GC	32	int iommu_merge __read_mostly = 0;
	33
	34	int no_iommu __read_mostly;
	35	/* Set this to 1 if there is a HW IOMMU in the system */
	36	int iommu_detected __read_mostly = 0;
	37
ac0101d3 JR	38	/*
ac0101d3 JR	39	* This variable becomes 1 if iommu=pt is passed on the kernel command line.
e3be785f	40	* If this variable is 1, IOMMU implementations do no DMA translation for
ac0101d3	41	* devices and allow every device to access to whole physical memory. This is
fb637f3c	42	* useful if a user wants to use an IOMMU only for KVM device assignment to
ac0101d3 JR	43	* guests and not for driver dma translation.
	44	*/
	45	int iommu_pass_through __read_mostly;
aed5d5f4	46
eb647138	47	/* Dummy device used for NULL arguments (normally ISA). */
6c505ce3	48	struct device x86_dma_fallback_dev = {
1a927133	49	.init_name = "fallback device",
eb647138	50	.coherent_dma_mask = ISA_DMA_BIT_MASK,
6c505ce3	51	.dma_mask = &x86_dma_fallback_dev.coherent_dma_mask,
098cb7f2	52	};
6c505ce3	53	EXPORT_SYMBOL(x86_dma_fallback_dev);
098cb7f2	54
2118d0c5 JR	55	/* Number of entries preallocated for DMA-API debugging */
	56	#define PREALLOC_DMA_DEBUG_ENTRIES 32768
	57
459121c9 GC	58	int dma_set_mask(struct device *dev, u64 mask)
	59	{
	60	if (!dev->dma_mask \|\| !dma_supported(dev, mask))
	61	return -EIO;
	62
	63	*dev->dma_mask = mask;
	64
	65	return 0;
	66	}
	67	EXPORT_SYMBOL(dma_set_mask);
	68
c252a5bb	69	#if defined(CONFIG_X86_64) && !defined(CONFIG_NUMA)
116890d5 GC	70	static __initdata void *dma32_bootmem_ptr;
	71	static unsigned long dma32_bootmem_size __initdata = (128ULL<<20);
	72
	73	static int __init parse_dma32_size_opt(char *p)
	74	{
	75	if (!p)
	76	return -EINVAL;
	77	dma32_bootmem_size = memparse(p, &p);
	78	return 0;
	79	}
	80	early_param("dma32_size", parse_dma32_size_opt);
	81
	82	void __init dma32_reserve_bootmem(void)
	83	{
	84	unsigned long size, align;
c987d12f	85	if (max_pfn <= MAX_DMA32_PFN)
116890d5 GC	86	return;
116890d5 GC	87
7677b2ef YL	88	/*
	89	* check aperture_64.c allocate_aperture() for reason about
	90	* using 512M as goal
	91	*/
116890d5	92	align = 64ULL<<20;
1ddb5518	93	size = roundup(dma32_bootmem_size, align);
116890d5	94	dma32_bootmem_ptr = __alloc_bootmem_nopanic(size, align,
7677b2ef	95	512ULL<<20);
acde31dc CM	96	/*
	97	* Kmemleak should not scan this block as it may not be mapped via the
	98	* kernel direct mapping.
	99	*/
	100	kmemleak_ignore(dma32_bootmem_ptr);
116890d5 GC	101	if (dma32_bootmem_ptr)
	102	dma32_bootmem_size = size;
	103	else
	104	dma32_bootmem_size = 0;
	105	}
	106	static void __init dma32_free_bootmem(void)
	107	{
116890d5	108
c987d12f	109	if (max_pfn <= MAX_DMA32_PFN)
116890d5 GC	110	return;
	111
	112	if (!dma32_bootmem_ptr)
	113	return;
	114
330fce23	115	free_bootmem(__pa(dma32_bootmem_ptr), dma32_bootmem_size);
116890d5 GC	116
	117	dma32_bootmem_ptr = NULL;
	118	dma32_bootmem_size = 0;
	119	}
c252a5bb YL	120	#else
	121	void __init dma32_reserve_bootmem(void)
	122	{
	123	}
	124	static void __init dma32_free_bootmem(void)
	125	{
	126	}
	127
cfb80c9e	128	#endif
116890d5 GC	129
	130	void __init pci_iommu_alloc(void)
	131	{
	132	/* free the range so iommu could get some range less than 4G */
	133	dma32_free_bootmem();
c252a5bb	134
186a2502 FT	135	if (pci_swiotlb_detect())
186a2502 FT	136	goto out;
cfb80c9e	137
116890d5	138	gart_iommu_hole_init();
116890d5	139
116890d5	140	detect_calgary();
116890d5 GC	141
	142	detect_intel_iommu();
	143
75f1cdf1	144	/* needs to be called after gart_iommu_hole_init */
a69ca340	145	amd_iommu_detect();
186a2502 FT	146	out:
186a2502 FT	147	pci_swiotlb_init();
116890d5	148	}
8978b742	149
9f6ac577 FT	150	void dma_generic_alloc_coherent(struct device dev, size_t size,
	151	dma_addr_t *dma_addr, gfp_t flag)
	152	{
	153	unsigned long dma_mask;
	154	struct page *page;
	155	dma_addr_t addr;
	156
	157	dma_mask = dma_alloc_coherent_mask(dev, flag);
	158
	159	flag \|= __GFP_ZERO;
	160	again:
	161	page = alloc_pages_node(dev_to_node(dev), flag, get_order(size));
	162	if (!page)
	163	return NULL;
	164
	165	addr = page_to_phys(page);
a4c2baa6	166	if (addr + size > dma_mask) {
9f6ac577 FT	167	__free_pages(page, get_order(size));
9f6ac577 FT	168
284901a9	169	if (dma_mask < DMA_BIT_MASK(32) && !(flag & GFP_DMA)) {
9f6ac577 FT	170	flag = (flag & ~GFP_DMA32) \| GFP_DMA;
	171	goto again;
	172	}
	173
	174	return NULL;
	175	}
	176
	177	*dma_addr = addr;
	178	return page_address(page);
	179	}
	180
fae9a0d8 GC	181	/*
	182	* See <Documentation/x86_64/boot-options.txt> for the iommu kernel parameter
	183	* documentation.
	184	*/
	185	static __init int iommu_setup(char *p)
	186	{
	187	iommu_merge = 1;
	188
	189	if (!p)
	190	return -EINVAL;
	191
	192	while (*p) {
	193	if (!strncmp(p, "off", 3))
	194	no_iommu = 1;
	195	/* gart_parse_options has more force support */
	196	if (!strncmp(p, "force", 5))
	197	force_iommu = 1;
	198	if (!strncmp(p, "noforce", 7)) {
	199	iommu_merge = 0;
	200	force_iommu = 0;
	201	}
	202
	203	if (!strncmp(p, "biomerge", 8)) {
fae9a0d8 GC	204	iommu_merge = 1;
	205	force_iommu = 1;
	206	}
	207	if (!strncmp(p, "panic", 5))
	208	panic_on_overflow = 1;
	209	if (!strncmp(p, "nopanic", 7))
	210	panic_on_overflow = 0;
	211	if (!strncmp(p, "merge", 5)) {
	212	iommu_merge = 1;
	213	force_iommu = 1;
	214	}
	215	if (!strncmp(p, "nomerge", 7))
	216	iommu_merge = 0;
	217	if (!strncmp(p, "forcesac", 8))
	218	iommu_sac_force = 1;
	219	if (!strncmp(p, "allowdac", 8))
	220	forbid_dac = 0;
	221	if (!strncmp(p, "nodac", 5))
2ae8bb75	222	forbid_dac = 1;
fae9a0d8 GC	223	if (!strncmp(p, "usedac", 6)) {
	224	forbid_dac = -1;
	225	return 1;
	226	}
	227	#ifdef CONFIG_SWIOTLB
	228	if (!strncmp(p, "soft", 4))
	229	swiotlb = 1;
3238c0c4	230	#endif
80286879	231	if (!strncmp(p, "pt", 2))
4ed0d3e6	232	iommu_pass_through = 1;
fae9a0d8	233
fae9a0d8	234	gart_parse_options(p);
fae9a0d8 GC	235
	236	#ifdef CONFIG_CALGARY_IOMMU
	237	if (!strncmp(p, "calgary", 7))
	238	use_calgary = 1;
	239	#endif /* CONFIG_CALGARY_IOMMU */
	240
	241	p += strcspn(p, ",");
	242	if (*p == ',')
	243	++p;
	244	}
	245	return 0;
	246	}
	247	early_param("iommu", iommu_setup);
	248
8e0c3797 GC	249	int dma_supported(struct device *dev, u64 mask)
8e0c3797 GC	250	{
160c1d8e	251	struct dma_map_ops *ops = get_dma_ops(dev);
8d8bb39b	252
8e0c3797 GC	253	#ifdef CONFIG_PCI
8e0c3797 GC	254	if (mask > 0xffffffff && forbid_dac > 0) {
fc3a8828	255	dev_info(dev, "PCI: Disallowing DAC for device\n");
8e0c3797 GC	256	return 0;
	257	}
	258	#endif
	259
8d8bb39b FT	260	if (ops->dma_supported)
8d8bb39b FT	261	return ops->dma_supported(dev, mask);
8e0c3797 GC	262
	263	/* Copied from i386. Doesn't make much sense, because it will
	264	only work for pci_alloc_coherent.
	265	The caller just has to use GFP_DMA in this case. */
2f4f27d4	266	if (mask < DMA_BIT_MASK(24))
8e0c3797 GC	267	return 0;
	268
	269	/* Tell the device to use SAC when IOMMU force is on. This
	270	allows the driver to use cheaper accesses in some cases.
	271
	272	Problem with this is that if we overflow the IOMMU area and
	273	return DAC as fallback address the device may not handle it
	274	correctly.
	275
	276	As a special case some controllers have a 39bit address
	277	mode that is as efficient as 32bit (aic79xx). Don't force
	278	SAC for these. Assume all masks <= 40 bits are of this
	279	type. Normally this doesn't make any difference, but gives
	280	more gentle handling of IOMMU overflow. */
50cf156a	281	if (iommu_sac_force && (mask >= DMA_BIT_MASK(40))) {
fc3a8828	282	dev_info(dev, "Force SAC with mask %Lx\n", mask);
8e0c3797 GC	283	return 0;
	284	}
	285
	286	return 1;
	287	}
	288	EXPORT_SYMBOL(dma_supported);
	289
cb5867a5 GC	290	static int __init pci_iommu_init(void)
cb5867a5 GC	291	{
2118d0c5 JR	292	dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
2118d0c5 JR	293
86f31952 JR	294	#ifdef CONFIG_PCI
	295	dma_debug_add_bus(&pci_bus_type);
	296	#endif
d07c1be0 FT	297	x86_init.iommu.iommu_init();
d07c1be0 FT	298
75f1cdf1 FT	299	if (swiotlb) {
	300	printk(KERN_INFO "PCI-DMA: "
	301	"Using software bounce buffering for IO (SWIOTLB)\n");
	302	swiotlb_print_info();
	303	} else
	304	swiotlb_free();
	305
cb5867a5 GC	306	return 0;
cb5867a5 GC	307	}
cb5867a5	308	/* Must execute after PCI subsystem */
9a821b23	309	rootfs_initcall(pci_iommu_init);
3b15e581 FY	310
	311	#ifdef CONFIG_PCI
	312	/* Many VIA bridges seem to corrupt data for DAC. Disable it here */
	313
	314	static __devinit void via_no_dac(struct pci_dev *dev)
	315	{
	316	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && forbid_dac == 0) {
13bf7576	317	dev_info(&dev->dev, "disabling DAC on VIA PCI bridge\n");
3b15e581 FY	318	forbid_dac = 1;
	319	}
	320	}
	321	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID, via_no_dac);
	322	#endif