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x86, AMD IOMMU: honor iommu=off instead of amd_iommu=off
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kernel / amd_iommu_init.c
CommitLineData
f6e2e6b6
JR		 1/*
2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/pci.h>
21#include <linux/acpi.h>
22#include <linux/gfp.h>
23#include <linux/list.h>
7441e9cb 24#include <linux/sysdev.h>
f6e2e6b6
JR		 25#include <asm/pci-direct.h>
26#include <asm/amd_iommu_types.h>
c6da992e 27#include <asm/amd_iommu.h>
f6e2e6b6
JR		 28#include <asm/gart.h>
29
30/*
31 * definitions for the ACPI scanning code
32 */
33#define UPDATE_LAST_BDF(x) do {\
34 if ((x) > amd_iommu_last_bdf) \
35 amd_iommu_last_bdf = (x); \
36 } while (0);
37
38#define DEVID(bus, devfn) (((bus) << 8) | (devfn))
39#define PCI_BUS(x) (((x) >> 8) & 0xff)
40#define IVRS_HEADER_LENGTH 48
41#define TBL_SIZE(x) (1 << (PAGE_SHIFT + get_order(amd_iommu_last_bdf * (x))))
42
43#define ACPI_IVHD_TYPE 0x10
44#define ACPI_IVMD_TYPE_ALL 0x20
45#define ACPI_IVMD_TYPE 0x21
46#define ACPI_IVMD_TYPE_RANGE 0x22
47
48#define IVHD_DEV_ALL 0x01
49#define IVHD_DEV_SELECT 0x02
50#define IVHD_DEV_SELECT_RANGE_START 0x03
51#define IVHD_DEV_RANGE_END 0x04
52#define IVHD_DEV_ALIAS 0x42
53#define IVHD_DEV_ALIAS_RANGE 0x43
54#define IVHD_DEV_EXT_SELECT 0x46
55#define IVHD_DEV_EXT_SELECT_RANGE 0x47
56
57#define IVHD_FLAG_HT_TUN_EN 0x00
58#define IVHD_FLAG_PASSPW_EN 0x01
59#define IVHD_FLAG_RESPASSPW_EN 0x02
60#define IVHD_FLAG_ISOC_EN 0x03
61
62#define IVMD_FLAG_EXCL_RANGE 0x08
63#define IVMD_FLAG_UNITY_MAP 0x01
64
65#define ACPI_DEVFLAG_INITPASS 0x01
66#define ACPI_DEVFLAG_EXTINT 0x02
67#define ACPI_DEVFLAG_NMI 0x04
68#define ACPI_DEVFLAG_SYSMGT1 0x10
69#define ACPI_DEVFLAG_SYSMGT2 0x20
70#define ACPI_DEVFLAG_LINT0 0x40
71#define ACPI_DEVFLAG_LINT1 0x80
72#define ACPI_DEVFLAG_ATSDIS 0x10000000
73
74struct ivhd_header {
75 u8 type;
76 u8 flags;
77 u16 length;
78 u16 devid;
79 u16 cap_ptr;
80 u64 mmio_phys;
81 u16 pci_seg;
82 u16 info;
83 u32 reserved;
84} __attribute__((packed));
85
86struct ivhd_entry {
87 u8 type;
88 u16 devid;
89 u8 flags;
90 u32 ext;
91} __attribute__((packed));
92
93struct ivmd_header {
94 u8 type;
95 u8 flags;
96 u16 length;
97 u16 devid;
98 u16 aux;
99 u64 resv;
100 u64 range_start;
101 u64 range_length;
102} __attribute__((packed));
103
928abd25
JR		 104u16 amd_iommu_last_bdf;
105struct list_head amd_iommu_unity_map;
106unsigned amd_iommu_aperture_order = 26;
107int amd_iommu_isolate;
108
109struct list_head amd_iommu_list;
110struct dev_table_entry *amd_iommu_dev_table;
111u16 *amd_iommu_alias_table;
112struct amd_iommu **amd_iommu_rlookup_table;
113struct protection_domain **amd_iommu_pd_table;
114unsigned long *amd_iommu_pd_alloc_bitmap;
115
116static u32 dev_table_size;
117static u32 alias_table_size;
118static u32 rlookup_table_size;
3e8064ba 119
b2026aa2
JR		 120static void __init iommu_set_exclusion_range(struct amd_iommu *iommu)
121{
122 u64 start = iommu->exclusion_start & PAGE_MASK;
123 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
124 u64 entry;
125
126 if (!iommu->exclusion_start)
127 return;
128
129 entry = start | MMIO_EXCL_ENABLE_MASK;
130 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
131 &entry, sizeof(entry));
132
133 entry = limit;
134 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
135 &entry, sizeof(entry));
136}
137
138static void __init iommu_set_device_table(struct amd_iommu *iommu)
139{
140 u32 entry;
141
142 BUG_ON(iommu->mmio_base == NULL);
143
144 entry = virt_to_phys(amd_iommu_dev_table);
145 entry |= (dev_table_size >> 12) - 1;
146 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
147 &entry, sizeof(entry));
148}
149
150static void __init iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
151{
152 u32 ctrl;
153
154 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
155 ctrl |= (1 << bit);
156 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
157}
158
159static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
160{
161 u32 ctrl;
162
163 ctrl = (u64)readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
164 ctrl &= ~(1 << bit);
165 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
166}
167
168void __init iommu_enable(struct amd_iommu *iommu)
169{
170 u32 ctrl;
171
172 printk(KERN_INFO "AMD IOMMU: Enabling IOMMU at ");
173 print_devid(iommu->devid, 0);
174 printk(" cap 0x%hx\n", iommu->cap_ptr);
175
176 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
177 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
178}
179
6c56747b
JR		 180static u8 * __init iommu_map_mmio_space(u64 address)
181{
182 u8 *ret;
183
184 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu"))
185 return NULL;
186
187 ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
188 if (ret != NULL)
189 return ret;
190
191 release_mem_region(address, MMIO_REGION_LENGTH);
192
193 return NULL;
194}
195
196static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
197{
198 if (iommu->mmio_base)
199 iounmap(iommu->mmio_base);
200 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
201}
202
3e8064ba
JR		 203static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
204{
205 u32 cap;
206
207 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
208 UPDATE_LAST_BDF(DEVID(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
209
210 return 0;
211}
212
213static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
214{
215 u8 *p = (void *)h, *end = (void *)h;
216 struct ivhd_entry *dev;
217
218 p += sizeof(*h);
219 end += h->length;
220
221 find_last_devid_on_pci(PCI_BUS(h->devid),
222 PCI_SLOT(h->devid),
223 PCI_FUNC(h->devid),
224 h->cap_ptr);
225
226 while (p < end) {
227 dev = (struct ivhd_entry *)p;
228 switch (dev->type) {
229 case IVHD_DEV_SELECT:
230 case IVHD_DEV_RANGE_END:
231 case IVHD_DEV_ALIAS:
232 case IVHD_DEV_EXT_SELECT:
233 UPDATE_LAST_BDF(dev->devid);
234 break;
235 default:
236 break;
237 }
238 p += 0x04 << (*p >> 6);
239 }
240
241 WARN_ON(p != end);
242
243 return 0;
244}
245
246static int __init find_last_devid_acpi(struct acpi_table_header *table)
247{
248 int i;
249 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
250 struct ivhd_header *h;
251
252 /*
253 * Validate checksum here so we don't need to do it when
254 * we actually parse the table
255 */
256 for (i = 0; i < table->length; ++i)
257 checksum += p[i];
258 if (checksum != 0)
259 /* ACPI table corrupt */
260 return -ENODEV;
261
262 p += IVRS_HEADER_LENGTH;
263
264 end += table->length;
265 while (p < end) {
266 h = (struct ivhd_header *)p;
267 switch (h->type) {
268 case ACPI_IVHD_TYPE:
269 find_last_devid_from_ivhd(h);
270 break;
271 default:
272 break;
273 }
274 p += h->length;
275 }
276 WARN_ON(p != end);
277
278 return 0;
279}
280
b36ca91e
JR		 281static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
282{
283 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL,
284 get_order(CMD_BUFFER_SIZE));
285 u64 entry = 0;
286
287 if (cmd_buf == NULL)
288 return NULL;
289
290 iommu->cmd_buf_size = CMD_BUFFER_SIZE;
291
292 memset(cmd_buf, 0, CMD_BUFFER_SIZE);
293
294 entry = (u64)virt_to_phys(cmd_buf);
295 entry |= MMIO_CMD_SIZE_512;
296 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
297 &entry, sizeof(entry));
298
299 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
300
301 return cmd_buf;
302}
303
304static void __init free_command_buffer(struct amd_iommu *iommu)
305{
306 if (iommu->cmd_buf)
307 free_pages((unsigned long)iommu->cmd_buf,
308 get_order(CMD_BUFFER_SIZE));
309}
310
3566b778
JR		 311static void set_dev_entry_bit(u16 devid, u8 bit)
312{
313 int i = (bit >> 5) & 0x07;
314 int _bit = bit & 0x1f;
315
316 amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
317}
318
319static void __init set_dev_entry_from_acpi(u16 devid, u32 flags, u32 ext_flags)
320{
321 if (flags & ACPI_DEVFLAG_INITPASS)
322 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
323 if (flags & ACPI_DEVFLAG_EXTINT)
324 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
325 if (flags & ACPI_DEVFLAG_NMI)
326 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
327 if (flags & ACPI_DEVFLAG_SYSMGT1)
328 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
329 if (flags & ACPI_DEVFLAG_SYSMGT2)
330 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
331 if (flags & ACPI_DEVFLAG_LINT0)
332 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
333 if (flags & ACPI_DEVFLAG_LINT1)
334 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
335}
336
337static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
338{
339 amd_iommu_rlookup_table[devid] = iommu;
340}
341
342static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
343{
344 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
345
346 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
347 return;
348
349 if (iommu) {
350 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
351 iommu->exclusion_start = m->range_start;
352 iommu->exclusion_length = m->range_length;
353 }
354}
355
5d0c8e49
JR		 356static void __init init_iommu_from_pci(struct amd_iommu *iommu)
357{
358 int bus = PCI_BUS(iommu->devid);
359 int dev = PCI_SLOT(iommu->devid);
360 int fn = PCI_FUNC(iommu->devid);
361 int cap_ptr = iommu->cap_ptr;
362 u32 range;
363
364 iommu->cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_CAP_HDR_OFFSET);
365
366 range = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
367 iommu->first_device = DEVID(MMIO_GET_BUS(range), MMIO_GET_FD(range));
368 iommu->last_device = DEVID(MMIO_GET_BUS(range), MMIO_GET_LD(range));
369}
370
371static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
372 struct ivhd_header *h)
373{
374 u8 *p = (u8 *)h;
375 u8 *end = p, flags = 0;
376 u16 dev_i, devid = 0, devid_start = 0, devid_to = 0;
377 u32 ext_flags = 0;
378 bool alias = 0;
379 struct ivhd_entry *e;
380
381 /*
382 * First set the recommended feature enable bits from ACPI
383 * into the IOMMU control registers
384 */
385 h->flags & IVHD_FLAG_HT_TUN_EN ?
386 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
387 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
388
389 h->flags & IVHD_FLAG_PASSPW_EN ?
390 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
391 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
392
393 h->flags & IVHD_FLAG_RESPASSPW_EN ?
394 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
395 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
396
397 h->flags & IVHD_FLAG_ISOC_EN ?
398 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
399 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
400
401 /*
402 * make IOMMU memory accesses cache coherent
403 */
404 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
405
406 /*
407 * Done. Now parse the device entries
408 */
409 p += sizeof(struct ivhd_header);
410 end += h->length;
411
412 while (p < end) {
413 e = (struct ivhd_entry *)p;
414 switch (e->type) {
415 case IVHD_DEV_ALL:
416 for (dev_i = iommu->first_device;
417 dev_i <= iommu->last_device; ++dev_i)
418 set_dev_entry_from_acpi(dev_i, e->flags, 0);
419 break;
420 case IVHD_DEV_SELECT:
421 devid = e->devid;
422 set_dev_entry_from_acpi(devid, e->flags, 0);
423 break;
424 case IVHD_DEV_SELECT_RANGE_START:
425 devid_start = e->devid;
426 flags = e->flags;
427 ext_flags = 0;
428 alias = 0;
429 break;
430 case IVHD_DEV_ALIAS:
431 devid = e->devid;
432 devid_to = e->ext >> 8;
433 set_dev_entry_from_acpi(devid, e->flags, 0);
434 amd_iommu_alias_table[devid] = devid_to;
435 break;
436 case IVHD_DEV_ALIAS_RANGE:
437 devid_start = e->devid;
438 flags = e->flags;
439 devid_to = e->ext >> 8;
440 ext_flags = 0;
441 alias = 1;
442 break;
443 case IVHD_DEV_EXT_SELECT:
444 devid = e->devid;
445 set_dev_entry_from_acpi(devid, e->flags, e->ext);
446 break;
447 case IVHD_DEV_EXT_SELECT_RANGE:
448 devid_start = e->devid;
449 flags = e->flags;
450 ext_flags = e->ext;
451 alias = 0;
452 break;
453 case IVHD_DEV_RANGE_END:
454 devid = e->devid;
455 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
456 if (alias)
457 amd_iommu_alias_table[dev_i] = devid_to;
458 set_dev_entry_from_acpi(
459 amd_iommu_alias_table[dev_i],
460 flags, ext_flags);
461 }
462 break;
463 default:
464 break;
465 }
466
467 p += 0x04 << (e->type >> 6);
468 }
469}
470
471static int __init init_iommu_devices(struct amd_iommu *iommu)
472{
473 u16 i;
474
475 for (i = iommu->first_device; i <= iommu->last_device; ++i)
476 set_iommu_for_device(iommu, i);
477
478 return 0;
479}
480
e47d402d
JR		 481static void __init free_iommu_one(struct amd_iommu *iommu)
482{
483 free_command_buffer(iommu);
484 iommu_unmap_mmio_space(iommu);
485}
486
487static void __init free_iommu_all(void)
488{
489 struct amd_iommu *iommu, *next;
490
491 list_for_each_entry_safe(iommu, next, &amd_iommu_list, list) {
492 list_del(&iommu->list);
493 free_iommu_one(iommu);
494 kfree(iommu);
495 }
496}
497
498static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
499{
500 spin_lock_init(&iommu->lock);
501 list_add_tail(&iommu->list, &amd_iommu_list);
502
503 /*
504 * Copy data from ACPI table entry to the iommu struct
505 */
506 iommu->devid = h->devid;
507 iommu->cap_ptr = h->cap_ptr;
508 iommu->mmio_phys = h->mmio_phys;
509 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
510 if (!iommu->mmio_base)
511 return -ENOMEM;
512
513 iommu_set_device_table(iommu);
514 iommu->cmd_buf = alloc_command_buffer(iommu);
515 if (!iommu->cmd_buf)
516 return -ENOMEM;
517
518 init_iommu_from_pci(iommu);
519 init_iommu_from_acpi(iommu, h);
520 init_iommu_devices(iommu);
521
522 return 0;
523}
524
525static int __init init_iommu_all(struct acpi_table_header *table)
526{
527 u8 *p = (u8 *)table, *end = (u8 *)table;
528 struct ivhd_header *h;
529 struct amd_iommu *iommu;
530 int ret;
531
532 INIT_LIST_HEAD(&amd_iommu_list);
533
534 end += table->length;
535 p += IVRS_HEADER_LENGTH;
536
537 while (p < end) {
538 h = (struct ivhd_header *)p;
539 switch (*p) {
540 case ACPI_IVHD_TYPE:
541 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
542 if (iommu == NULL)
543 return -ENOMEM;
544 ret = init_iommu_one(iommu, h);
545 if (ret)
546 return ret;
547 break;
548 default:
549 break;
550 }
551 p += h->length;
552
553 }
554 WARN_ON(p != end);
555
556 return 0;
557}
558
be2a022c
JR		 559static void __init free_unity_maps(void)
560{
561 struct unity_map_entry *entry, *next;
562
563 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
564 list_del(&entry->list);
565 kfree(entry);
566 }
567}
568
569static int __init init_exclusion_range(struct ivmd_header *m)
570{
571 int i;
572
573 switch (m->type) {
574 case ACPI_IVMD_TYPE:
575 set_device_exclusion_range(m->devid, m);
576 break;
577 case ACPI_IVMD_TYPE_ALL:
578 for (i = 0; i < amd_iommu_last_bdf; ++i)
579 set_device_exclusion_range(i, m);
580 break;
581 case ACPI_IVMD_TYPE_RANGE:
582 for (i = m->devid; i <= m->aux; ++i)
583 set_device_exclusion_range(i, m);
584 break;
585 default:
586 break;
587 }
588
589 return 0;
590}
591
592static int __init init_unity_map_range(struct ivmd_header *m)
593{
594 struct unity_map_entry *e = 0;
595
596 e = kzalloc(sizeof(*e), GFP_KERNEL);
597 if (e == NULL)
598 return -ENOMEM;
599
600 switch (m->type) {
601 default:
602 case ACPI_IVMD_TYPE:
603 e->devid_start = e->devid_end = m->devid;
604 break;
605 case ACPI_IVMD_TYPE_ALL:
606 e->devid_start = 0;
607 e->devid_end = amd_iommu_last_bdf;
608 break;
609 case ACPI_IVMD_TYPE_RANGE:
610 e->devid_start = m->devid;
611 e->devid_end = m->aux;
612 break;
613 }
614 e->address_start = PAGE_ALIGN(m->range_start);
615 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
616 e->prot = m->flags >> 1;
617
618 list_add_tail(&e->list, &amd_iommu_unity_map);
619
620 return 0;
621}
622
623static int __init init_memory_definitions(struct acpi_table_header *table)
624{
625 u8 *p = (u8 *)table, *end = (u8 *)table;
626 struct ivmd_header *m;
627
628 INIT_LIST_HEAD(&amd_iommu_unity_map);
629
630 end += table->length;
631 p += IVRS_HEADER_LENGTH;
632
633 while (p < end) {
634 m = (struct ivmd_header *)p;
635 if (m->flags & IVMD_FLAG_EXCL_RANGE)
636 init_exclusion_range(m);
637 else if (m->flags & IVMD_FLAG_UNITY_MAP)
638 init_unity_map_range(m);
639
640 p += m->length;
641 }
642
643 return 0;
644}
645
8736197b
JR		 646static void __init enable_iommus(void)
647{
648 struct amd_iommu *iommu;
649
650 list_for_each_entry(iommu, &amd_iommu_list, list) {
651 iommu_set_exclusion_range(iommu);
652 iommu_enable(iommu);
653 }
654}
655
7441e9cb
JR		 656/*
657 * Suspend/Resume support
658 * disable suspend until real resume implemented
659 */
660
661static int amd_iommu_resume(struct sys_device *dev)
662{
663 return 0;
664}
665
666static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state)
667{
668 return -EINVAL;
669}
670
671static struct sysdev_class amd_iommu_sysdev_class = {
672 .name = "amd_iommu",
673 .suspend = amd_iommu_suspend,
674 .resume = amd_iommu_resume,
675};
676
677static struct sys_device device_amd_iommu = {
678 .id = 0,
679 .cls = &amd_iommu_sysdev_class,
680};
681
fe74c9cf
JR		 682int __init amd_iommu_init(void)
683{
684 int i, ret = 0;
685
686
8b14518f 687 if (no_iommu) {
fe74c9cf
JR		 688 printk(KERN_INFO "AMD IOMMU disabled by kernel command line\n");
689 return 0;
690 }
691
692 /*
693 * First parse ACPI tables to find the largest Bus/Dev/Func
694 * we need to handle. Upon this information the shared data
695 * structures for the IOMMUs in the system will be allocated
696 */
697 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
698 return -ENODEV;
699
700 dev_table_size = TBL_SIZE(DEV_TABLE_ENTRY_SIZE);
701 alias_table_size = TBL_SIZE(ALIAS_TABLE_ENTRY_SIZE);
702 rlookup_table_size = TBL_SIZE(RLOOKUP_TABLE_ENTRY_SIZE);
703
704 ret = -ENOMEM;
705
706 /* Device table - directly used by all IOMMUs */
707 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL,
708 get_order(dev_table_size));
709 if (amd_iommu_dev_table == NULL)
710 goto out;
711
712 /*
713 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
714 * IOMMU see for that device
715 */
716 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
717 get_order(alias_table_size));
718 if (amd_iommu_alias_table == NULL)
719 goto free;
720
721 /* IOMMU rlookup table - find the IOMMU for a specific device */
722 amd_iommu_rlookup_table = (void *)__get_free_pages(GFP_KERNEL,
723 get_order(rlookup_table_size));
724 if (amd_iommu_rlookup_table == NULL)
725 goto free;
726
727 /*
728 * Protection Domain table - maps devices to protection domains
729 * This table has the same size as the rlookup_table
730 */
731 amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL,
732 get_order(rlookup_table_size));
733 if (amd_iommu_pd_table == NULL)
734 goto free;
735
736 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(GFP_KERNEL,
737 get_order(MAX_DOMAIN_ID/8));
738 if (amd_iommu_pd_alloc_bitmap == NULL)
739 goto free;
740
741 /*
742 * memory is allocated now; initialize the device table with all zeroes
743 * and let all alias entries point to itself
744 */
745 memset(amd_iommu_dev_table, 0, dev_table_size);
746 for (i = 0; i < amd_iommu_last_bdf; ++i)
747 amd_iommu_alias_table[i] = i;
748
749 memset(amd_iommu_pd_table, 0, rlookup_table_size);
750 memset(amd_iommu_pd_alloc_bitmap, 0, MAX_DOMAIN_ID / 8);
751
752 /*
753 * never allocate domain 0 because its used as the non-allocated and
754 * error value placeholder
755 */
756 amd_iommu_pd_alloc_bitmap[0] = 1;
757
758 /*
759 * now the data structures are allocated and basically initialized
760 * start the real acpi table scan
761 */
762 ret = -ENODEV;
763 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
764 goto free;
765
766 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
767 goto free;
768
8736197b
JR		 769 ret = amd_iommu_init_dma_ops();
770 if (ret)
771 goto free;
772
7441e9cb
JR		 773 ret = sysdev_class_register(&amd_iommu_sysdev_class);
774 if (ret)
775 goto free;
776
777 ret = sysdev_register(&device_amd_iommu);
778 if (ret)
779 goto free;
780
8736197b
JR		 781 enable_iommus();
782
fe74c9cf
JR		 783 printk(KERN_INFO "AMD IOMMU: aperture size is %d MB\n",
784 (1 << (amd_iommu_aperture_order-20)));
785
786 printk(KERN_INFO "AMD IOMMU: device isolation ");
787 if (amd_iommu_isolate)
788 printk("enabled\n");
789 else
790 printk("disabled\n");
791
792out:
793 return ret;
794
795free:
796 if (amd_iommu_pd_alloc_bitmap)
797 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, 1);
798
799 if (amd_iommu_pd_table)
800 free_pages((unsigned long)amd_iommu_pd_table,
801 get_order(rlookup_table_size));
802
803 if (amd_iommu_rlookup_table)
804 free_pages((unsigned long)amd_iommu_rlookup_table,
805 get_order(rlookup_table_size));
806
807 if (amd_iommu_alias_table)
808 free_pages((unsigned long)amd_iommu_alias_table,
809 get_order(alias_table_size));
810
811 if (amd_iommu_dev_table)
812 free_pages((unsigned long)amd_iommu_dev_table,
813 get_order(dev_table_size));
814
815 free_iommu_all();
816
817 free_unity_maps();
818
819 goto out;
820}
821
ae7877de
JR		 822static int __init early_amd_iommu_detect(struct acpi_table_header *table)
823{
824 return 0;
825}
826
827void __init amd_iommu_detect(void)
828{
829 if (swiotlb || no_iommu || iommu_detected)
830 return;
831
ae7877de
JR		 832 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
833 iommu_detected = 1;
92af4e29 834#ifdef CONFIG_GART_IOMMU
ae7877de
JR		 835 gart_iommu_aperture_disabled = 1;
836 gart_iommu_aperture = 0;
92af4e29 837#endif
ae7877de
JR		 838 }
839}
840
918ad6c5
JR		 841static int __init parse_amd_iommu_options(char *str)
842{
843 for (; *str; ++str) {
918ad6c5
JR		 844 if (strcmp(str, "isolate") == 0)
845 amd_iommu_isolate = 1;
846 }
847
848 return 1;
849}
850
851static int __init parse_amd_iommu_size_options(char *str)
852{
853 for (; *str; ++str) {
854 if (strcmp(str, "32M") == 0)
855 amd_iommu_aperture_order = 25;
856 if (strcmp(str, "64M") == 0)
857 amd_iommu_aperture_order = 26;
858 if (strcmp(str, "128M") == 0)
859 amd_iommu_aperture_order = 27;
860 if (strcmp(str, "256M") == 0)
861 amd_iommu_aperture_order = 28;
862 if (strcmp(str, "512M") == 0)
863 amd_iommu_aperture_order = 29;
864 if (strcmp(str, "1G") == 0)
865 amd_iommu_aperture_order = 30;
866 }
867
868 return 1;
869}
870
871__setup("amd_iommu=", parse_amd_iommu_options);
872__setup("amd_iommu_size=", parse_amd_iommu_size_options);
kernel source for telekom puls (alcatel/mediatek)