[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / sparc / mm / iommu.c

/*
 * iommu.c:  IOMMU specific routines for memory management.
 *
 * Copyright (C) 1995 David S. Miller  (davem@caip.rutgers.edu)
 * Copyright (C) 1995,2002 Pete Zaitcev     (zaitcev@yahoo.com)
 * Copyright (C) 1996 Eddie C. Dost    (ecd@skynet.be)
 * Copyright (C) 1997,1998 Jakub Jelinek    (jj@sunsite.mff.cuni.cz)
 */
 
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/highmem.h>	/* pte_offset_map => kmap_atomic */
#include <linux/scatterlist.h>
#include <linux/of.h>
#include <linux/of_device.h>

#include <asm/pgalloc.h>
#include <asm/pgtable.h>
#include <asm/io.h>
#include <asm/mxcc.h>
#include <asm/mbus.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/bitext.h>
#include <asm/iommu.h>
#include <asm/dma.h>

/*
 * This can be sized dynamically, but we will do this
 * only when we have a guidance about actual I/O pressures.
 */
#define IOMMU_RNGE	IOMMU_RNGE_256MB
#define IOMMU_START	0xF0000000
#define IOMMU_WINSIZE	(256*1024*1024U)
#define IOMMU_NPTES	(IOMMU_WINSIZE/PAGE_SIZE)	/* 64K PTEs, 256KB */
#define IOMMU_ORDER	6				/* 4096 * (1<<6) */

/* srmmu.c */
extern int viking_mxcc_present;
extern int flush_page_for_dma_global;
static int viking_flush;
/* viking.S */
extern void viking_flush_page(unsigned long page);
extern void viking_mxcc_flush_page(unsigned long page);

/*
 * Values precomputed according to CPU type.
 */
static unsigned int ioperm_noc;		/* Consistent mapping iopte flags */
static pgprot_t dvma_prot;		/* Consistent mapping pte flags */

#define IOPERM        (IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID)
#define MKIOPTE(pfn, perm) (((((pfn)<<8) & IOPTE_PAGE) | (perm)) & ~IOPTE_WAZ)

static void __init sbus_iommu_init(struct platform_device *op)
{
	struct iommu_struct *iommu;
	unsigned int impl, vers;
	unsigned long *bitmap;
	unsigned long tmp;

	iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL);
	if (!iommu) {
		prom_printf("Unable to allocate iommu structure\n");
		prom_halt();
	}

	iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3,
				 "iommu_regs");
	if (!iommu->regs) {
		prom_printf("Cannot map IOMMU registers\n");
		prom_halt();
	}
	impl = (iommu->regs->control & IOMMU_CTRL_IMPL) >> 28;
	vers = (iommu->regs->control & IOMMU_CTRL_VERS) >> 24;
	tmp = iommu->regs->control;
	tmp &= ~(IOMMU_CTRL_RNGE);
	tmp |= (IOMMU_RNGE_256MB | IOMMU_CTRL_ENAB);
	iommu->regs->control = tmp;
	iommu_invalidate(iommu->regs);
	iommu->start = IOMMU_START;
	iommu->end = 0xffffffff;

	/* Allocate IOMMU page table */
	/* Stupid alignment constraints give me a headache. 
	   We need 256K or 512K or 1M or 2M area aligned to
           its size and current gfp will fortunately give
           it to us. */
        tmp = __get_free_pages(GFP_KERNEL, IOMMU_ORDER);
	if (!tmp) {
		prom_printf("Unable to allocate iommu table [0x%lx]\n",
			    IOMMU_NPTES * sizeof(iopte_t));
		prom_halt();
	}
	iommu->page_table = (iopte_t *)tmp;

	/* Initialize new table. */
	memset(iommu->page_table, 0, IOMMU_NPTES*sizeof(iopte_t));
	flush_cache_all();
	flush_tlb_all();
	iommu->regs->base = __pa((unsigned long) iommu->page_table) >> 4;
	iommu_invalidate(iommu->regs);

	bitmap = kmalloc(IOMMU_NPTES>>3, GFP_KERNEL);
	if (!bitmap) {
		prom_printf("Unable to allocate iommu bitmap [%d]\n",
			    (int)(IOMMU_NPTES>>3));
		prom_halt();
	}
	bit_map_init(&iommu->usemap, bitmap, IOMMU_NPTES);
	/* To be coherent on HyperSparc, the page color of DVMA
	 * and physical addresses must match.
	 */
	if (srmmu_modtype == HyperSparc)
		iommu->usemap.num_colors = vac_cache_size >> PAGE_SHIFT;
	else
		iommu->usemap.num_colors = 1;

	printk(KERN_INFO "IOMMU: impl %d vers %d table 0x%p[%d B] map [%d b]\n",
	       impl, vers, iommu->page_table,
	       (int)(IOMMU_NPTES*sizeof(iopte_t)), (int)IOMMU_NPTES);

	op->dev.archdata.iommu = iommu;
}

static int __init iommu_init(void)
{
	struct device_node *dp;

	for_each_node_by_name(dp, "iommu") {
		struct platform_device *op = of_find_device_by_node(dp);

		sbus_iommu_init(op);
		of_propagate_archdata(op);
	}

	return 0;
}

subsys_initcall(iommu_init);

/* Flush the iotlb entries to ram. */
/* This could be better if we didn't have to flush whole pages. */
static void iommu_flush_iotlb(iopte_t *iopte, unsigned int niopte)
{
	unsigned long start;
	unsigned long end;

	start = (unsigned long)iopte;
	end = PAGE_ALIGN(start + niopte*sizeof(iopte_t));
	start &= PAGE_MASK;
	if (viking_mxcc_present) {
		while(start < end) {
			viking_mxcc_flush_page(start);
			start += PAGE_SIZE;
		}
	} else if (viking_flush) {
		while(start < end) {
			viking_flush_page(start);
			start += PAGE_SIZE;
		}
	} else {
		while(start < end) {
			__flush_page_to_ram(start);
			start += PAGE_SIZE;
		}
	}
}

static u32 iommu_get_one(struct device *dev, struct page *page, int npages)
{
	struct iommu_struct *iommu = dev->archdata.iommu;
	int ioptex;
	iopte_t *iopte, *iopte0;
	unsigned int busa, busa0;
	int i;

	/* page color = pfn of page */
	ioptex = bit_map_string_get(&iommu->usemap, npages, page_to_pfn(page));
	if (ioptex < 0)
		panic("iommu out");
	busa0 = iommu->start + (ioptex << PAGE_SHIFT);
	iopte0 = &iommu->page_table[ioptex];

	busa = busa0;
	iopte = iopte0;
	for (i = 0; i < npages; i++) {
		iopte_val(*iopte) = MKIOPTE(page_to_pfn(page), IOPERM);
		iommu_invalidate_page(iommu->regs, busa);
		busa += PAGE_SIZE;
		iopte++;
		page++;
	}

	iommu_flush_iotlb(iopte0, npages);

	return busa0;
}

static u32 iommu_get_scsi_one(struct device *dev, char *vaddr, unsigned int len)
{
	unsigned long off;
	int npages;
	struct page *page;
	u32 busa;

	off = (unsigned long)vaddr & ~PAGE_MASK;
	npages = (off + len + PAGE_SIZE-1) >> PAGE_SHIFT;
	page = virt_to_page((unsigned long)vaddr & PAGE_MASK);
	busa = iommu_get_one(dev, page, npages);
	return busa + off;
}

static __u32 iommu_get_scsi_one_gflush(struct device *dev, char *vaddr, unsigned long len)
{
	flush_page_for_dma(0);
	return iommu_get_scsi_one(dev, vaddr, len);
}

static __u32 iommu_get_scsi_one_pflush(struct device *dev, char *vaddr, unsigned long len)
{
	unsigned long page = ((unsigned long) vaddr) & PAGE_MASK;

	while(page < ((unsigned long)(vaddr + len))) {
		flush_page_for_dma(page);
		page += PAGE_SIZE;
	}
	return iommu_get_scsi_one(dev, vaddr, len);
}

static void iommu_get_scsi_sgl_gflush(struct device *dev, struct scatterlist *sg, int sz)
{
	int n;

	flush_page_for_dma(0);
	while (sz != 0) {
		--sz;
		n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT;
		sg->dma_address = iommu_get_one(dev, sg_page(sg), n) + sg->offset;
		sg->dma_length = sg->length;
		sg = sg_next(sg);
	}
}

static void iommu_get_scsi_sgl_pflush(struct device *dev, struct scatterlist *sg, int sz)
{
	unsigned long page, oldpage = 0;
	int n, i;

	while(sz != 0) {
		--sz;

		n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT;

		/*
		 * We expect unmapped highmem pages to be not in the cache.
		 * XXX Is this a good assumption?
		 * XXX What if someone else unmaps it here and races us?
		 */
		if ((page = (unsigned long) page_address(sg_page(sg))) != 0) {
			for (i = 0; i < n; i++) {
				if (page != oldpage) {	/* Already flushed? */
					flush_page_for_dma(page);
					oldpage = page;
				}
				page += PAGE_SIZE;
			}
		}

		sg->dma_address = iommu_get_one(dev, sg_page(sg), n) + sg->offset;
		sg->dma_length = sg->length;
		sg = sg_next(sg);
	}
}

static void iommu_release_one(struct device *dev, u32 busa, int npages)
{
	struct iommu_struct *iommu = dev->archdata.iommu;
	int ioptex;
	int i;

	BUG_ON(busa < iommu->start);
	ioptex = (busa - iommu->start) >> PAGE_SHIFT;
	for (i = 0; i < npages; i++) {
		iopte_val(iommu->page_table[ioptex + i]) = 0;
		iommu_invalidate_page(iommu->regs, busa);
		busa += PAGE_SIZE;
	}
	bit_map_clear(&iommu->usemap, ioptex, npages);
}

static void iommu_release_scsi_one(struct device *dev, __u32 vaddr, unsigned long len)
{
	unsigned long off;
	int npages;

	off = vaddr & ~PAGE_MASK;
	npages = (off + len + PAGE_SIZE-1) >> PAGE_SHIFT;
	iommu_release_one(dev, vaddr & PAGE_MASK, npages);
}

static void iommu_release_scsi_sgl(struct device *dev, struct scatterlist *sg, int sz)
{
	int n;

	while(sz != 0) {
		--sz;

		n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT;
		iommu_release_one(dev, sg->dma_address & PAGE_MASK, n);
		sg->dma_address = 0x21212121;
		sg = sg_next(sg);
	}
}

#ifdef CONFIG_SBUS
static int iommu_map_dma_area(struct device *dev, dma_addr_t *pba, unsigned long va,
			      unsigned long addr, int len)
{
	struct iommu_struct *iommu = dev->archdata.iommu;
	unsigned long page, end;
	iopte_t *iopte = iommu->page_table;
	iopte_t *first;
	int ioptex;

	BUG_ON((va & ~PAGE_MASK) != 0);
	BUG_ON((addr & ~PAGE_MASK) != 0);
	BUG_ON((len & ~PAGE_MASK) != 0);

	/* page color = physical address */
	ioptex = bit_map_string_get(&iommu->usemap, len >> PAGE_SHIFT,
		addr >> PAGE_SHIFT);
	if (ioptex < 0)
		panic("iommu out");

	iopte += ioptex;
	first = iopte;
	end = addr + len;
	while(addr < end) {
		page = va;
		{
			pgd_t *pgdp;
			pmd_t *pmdp;
			pte_t *ptep;

			if (viking_mxcc_present)
				viking_mxcc_flush_page(page);
			else if (viking_flush)
				viking_flush_page(page);
			else
				__flush_page_to_ram(page);

			pgdp = pgd_offset(&init_mm, addr);
			pmdp = pmd_offset(pgdp, addr);
			ptep = pte_offset_map(pmdp, addr);

			set_pte(ptep, mk_pte(virt_to_page(page), dvma_prot));
		}
		iopte_val(*iopte++) =
		    MKIOPTE(page_to_pfn(virt_to_page(page)), ioperm_noc);
		addr += PAGE_SIZE;
		va += PAGE_SIZE;
	}
	/* P3: why do we need this?
	 *
	 * DAVEM: Because there are several aspects, none of which
	 *        are handled by a single interface.  Some cpus are
	 *        completely not I/O DMA coherent, and some have
	 *        virtually indexed caches.  The driver DMA flushing
	 *        methods handle the former case, but here during
	 *        IOMMU page table modifications, and usage of non-cacheable
	 *        cpu mappings of pages potentially in the cpu caches, we have
	 *        to handle the latter case as well.
	 */
	flush_cache_all();
	iommu_flush_iotlb(first, len >> PAGE_SHIFT);
	flush_tlb_all();
	iommu_invalidate(iommu->regs);

	*pba = iommu->start + (ioptex << PAGE_SHIFT);
	return 0;
}

static void iommu_unmap_dma_area(struct device *dev, unsigned long busa, int len)
{
	struct iommu_struct *iommu = dev->archdata.iommu;
	iopte_t *iopte = iommu->page_table;
	unsigned long end;
	int ioptex = (busa - iommu->start) >> PAGE_SHIFT;

	BUG_ON((busa & ~PAGE_MASK) != 0);
	BUG_ON((len & ~PAGE_MASK) != 0);

	iopte += ioptex;
	end = busa + len;
	while (busa < end) {
		iopte_val(*iopte++) = 0;
		busa += PAGE_SIZE;
	}
	flush_tlb_all();
	iommu_invalidate(iommu->regs);
	bit_map_clear(&iommu->usemap, ioptex, len >> PAGE_SHIFT);
}
#endif

static const struct sparc32_dma_ops iommu_dma_gflush_ops = {
	.get_scsi_one		= iommu_get_scsi_one_gflush,
	.get_scsi_sgl		= iommu_get_scsi_sgl_gflush,
	.release_scsi_one	= iommu_release_scsi_one,
	.release_scsi_sgl	= iommu_release_scsi_sgl,
#ifdef CONFIG_SBUS
	.map_dma_area		= iommu_map_dma_area,
	.unmap_dma_area		= iommu_unmap_dma_area,
#endif
};

static const struct sparc32_dma_ops iommu_dma_pflush_ops = {
	.get_scsi_one		= iommu_get_scsi_one_pflush,
	.get_scsi_sgl		= iommu_get_scsi_sgl_pflush,
	.release_scsi_one	= iommu_release_scsi_one,
	.release_scsi_sgl	= iommu_release_scsi_sgl,
#ifdef CONFIG_SBUS
	.map_dma_area		= iommu_map_dma_area,
	.unmap_dma_area		= iommu_unmap_dma_area,
#endif
};

void __init ld_mmu_iommu(void)
{
	if (flush_page_for_dma_global) {
		/* flush_page_for_dma flushes everything, no matter of what page is it */
		sparc32_dma_ops = &iommu_dma_gflush_ops;
	} else {
		sparc32_dma_ops = &iommu_dma_pflush_ops;
	}

	if (viking_mxcc_present || srmmu_modtype == HyperSparc) {
		dvma_prot = __pgprot(SRMMU_CACHE | SRMMU_ET_PTE | SRMMU_PRIV);
		ioperm_noc = IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID;
	} else {
		dvma_prot = __pgprot(SRMMU_ET_PTE | SRMMU_PRIV);
		ioperm_noc = IOPTE_WRITE | IOPTE_VALID;
	}
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* iommu.c: IOMMU specific routines for memory management.
	3	*
	4	* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
	5	* Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
	6	* Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
	7	* Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	8	*/
	9
1da177e4 LT	10	#include <linux/kernel.h>
	11	#include <linux/init.h>
	12	#include <linux/mm.h>
	13	#include <linux/slab.h>
	14	#include <linux/highmem.h> /* pte_offset_map => kmap_atomic */
0912a5db	15	#include <linux/scatterlist.h>
9dc69230 DM	16	#include <linux/of.h>
9dc69230 DM	17	#include <linux/of_device.h>
1da177e4	18
1da177e4 LT	19	#include <asm/pgalloc.h>
1da177e4 LT	20	#include <asm/pgtable.h>
1da177e4 LT	21	#include <asm/io.h>
	22	#include <asm/mxcc.h>
	23	#include <asm/mbus.h>
	24	#include <asm/cacheflush.h>
	25	#include <asm/tlbflush.h>
	26	#include <asm/bitext.h>
	27	#include <asm/iommu.h>
	28	#include <asm/dma.h>
	29
	30	/*
	31	* This can be sized dynamically, but we will do this
	32	* only when we have a guidance about actual I/O pressures.
	33	*/
	34	#define IOMMU_RNGE IOMMU_RNGE_256MB
	35	#define IOMMU_START 0xF0000000
	36	#define IOMMU_WINSIZE (25610241024U)
9a0ac1b6	37	#define IOMMU_NPTES (IOMMU_WINSIZE/PAGE_SIZE) /* 64K PTEs, 256KB */
1da177e4 LT	38	#define IOMMU_ORDER 6 /* 4096 * (1<<6) */
	39
	40	/* srmmu.c */
	41	extern int viking_mxcc_present;
1da177e4 LT	42	extern int flush_page_for_dma_global;
	43	static int viking_flush;
	44	/* viking.S */
	45	extern void viking_flush_page(unsigned long page);
	46	extern void viking_mxcc_flush_page(unsigned long page);
	47
	48	/*
	49	* Values precomputed according to CPU type.
	50	*/
	51	static unsigned int ioperm_noc; /* Consistent mapping iopte flags */
	52	static pgprot_t dvma_prot; /* Consistent mapping pte flags */
	53
	54	#define IOPERM (IOPTE_CACHE \| IOPTE_WRITE \| IOPTE_VALID)
	55	#define MKIOPTE(pfn, perm) (((((pfn)<<8) & IOPTE_PAGE) \| (perm)) & ~IOPTE_WAZ)
	56
cd4cd730	57	static void __init sbus_iommu_init(struct platform_device *op)
1da177e4	58	{
1da177e4	59	struct iommu_struct *iommu;
e0039348	60	unsigned int impl, vers;
1da177e4	61	unsigned long *bitmap;
e0039348 DM	62	unsigned long tmp;
e0039348 DM	63
71cd03b0	64	iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL);
1da177e4 LT	65	if (!iommu) {
	66	prom_printf("Unable to allocate iommu structure\n");
	67	prom_halt();
	68	}
e0039348	69
046e26a8	70	iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3,
e0039348	71	"iommu_regs");
1da177e4 LT	72	if (!iommu->regs) {
	73	prom_printf("Cannot map IOMMU registers\n");
	74	prom_halt();
	75	}
	76	impl = (iommu->regs->control & IOMMU_CTRL_IMPL) >> 28;
	77	vers = (iommu->regs->control & IOMMU_CTRL_VERS) >> 24;
	78	tmp = iommu->regs->control;
	79	tmp &= ~(IOMMU_CTRL_RNGE);
	80	tmp \|= (IOMMU_RNGE_256MB \| IOMMU_CTRL_ENAB);
	81	iommu->regs->control = tmp;
	82	iommu_invalidate(iommu->regs);
	83	iommu->start = IOMMU_START;
	84	iommu->end = 0xffffffff;
	85
	86	/* Allocate IOMMU page table */
	87	/* Stupid alignment constraints give me a headache.
	88	We need 256K or 512K or 1M or 2M area aligned to
	89	its size and current gfp will fortunately give
	90	it to us. */
	91	tmp = __get_free_pages(GFP_KERNEL, IOMMU_ORDER);
	92	if (!tmp) {
5da444aa AM	93	prom_printf("Unable to allocate iommu table [0x%lx]\n",
5da444aa AM	94	IOMMU_NPTES * sizeof(iopte_t));
1da177e4 LT	95	prom_halt();
	96	}
	97	iommu->page_table = (iopte_t *)tmp;
	98
	99	/* Initialize new table. */
	100	memset(iommu->page_table, 0, IOMMU_NPTES*sizeof(iopte_t));
	101	flush_cache_all();
	102	flush_tlb_all();
	103	iommu->regs->base = __pa((unsigned long) iommu->page_table) >> 4;
	104	iommu_invalidate(iommu->regs);
	105
	106	bitmap = kmalloc(IOMMU_NPTES>>3, GFP_KERNEL);
	107	if (!bitmap) {
	108	prom_printf("Unable to allocate iommu bitmap [%d]\n",
	109	(int)(IOMMU_NPTES>>3));
	110	prom_halt();
	111	}
	112	bit_map_init(&iommu->usemap, bitmap, IOMMU_NPTES);
	113	/* To be coherent on HyperSparc, the page color of DVMA
	114	* and physical addresses must match.
	115	*/
	116	if (srmmu_modtype == HyperSparc)
	117	iommu->usemap.num_colors = vac_cache_size >> PAGE_SHIFT;
	118	else
	119	iommu->usemap.num_colors = 1;
	120
046e26a8 DM	121	printk(KERN_INFO "IOMMU: impl %d vers %d table 0x%p[%d B] map [%d b]\n",
	122	impl, vers, iommu->page_table,
	123	(int)(IOMMU_NPTES*sizeof(iopte_t)), (int)IOMMU_NPTES);
1da177e4	124
e0039348	125	op->dev.archdata.iommu = iommu;
1da177e4 LT	126	}
1da177e4 LT	127
046e26a8 DM	128	static int __init iommu_init(void)
	129	{
	130	struct device_node *dp;
	131
	132	for_each_node_by_name(dp, "iommu") {
cd4cd730	133	struct platform_device *op = of_find_device_by_node(dp);
046e26a8 DM	134
	135	sbus_iommu_init(op);
	136	of_propagate_archdata(op);
	137	}
	138
	139	return 0;
	140	}
	141
	142	subsys_initcall(iommu_init);
	143
1da177e4 LT	144	/* Flush the iotlb entries to ram. */
	145	/* This could be better if we didn't have to flush whole pages. */
	146	static void iommu_flush_iotlb(iopte_t *iopte, unsigned int niopte)
	147	{
	148	unsigned long start;
	149	unsigned long end;
	150
3185d4d2	151	start = (unsigned long)iopte;
1da177e4	152	end = PAGE_ALIGN(start + niopte*sizeof(iopte_t));
3185d4d2	153	start &= PAGE_MASK;
1da177e4 LT	154	if (viking_mxcc_present) {
	155	while(start < end) {
	156	viking_mxcc_flush_page(start);
	157	start += PAGE_SIZE;
	158	}
	159	} else if (viking_flush) {
	160	while(start < end) {
	161	viking_flush_page(start);
	162	start += PAGE_SIZE;
	163	}
	164	} else {
	165	while(start < end) {
	166	__flush_page_to_ram(start);
	167	start += PAGE_SIZE;
	168	}
	169	}
	170	}
	171
260489fa	172	static u32 iommu_get_one(struct device dev, struct page page, int npages)
1da177e4	173	{
260489fa	174	struct iommu_struct *iommu = dev->archdata.iommu;
1da177e4 LT	175	int ioptex;
	176	iopte_t iopte, iopte0;
	177	unsigned int busa, busa0;
	178	int i;
	179
	180	/* page color = pfn of page */
	181	ioptex = bit_map_string_get(&iommu->usemap, npages, page_to_pfn(page));
	182	if (ioptex < 0)
	183	panic("iommu out");
	184	busa0 = iommu->start + (ioptex << PAGE_SHIFT);
	185	iopte0 = &iommu->page_table[ioptex];
	186
	187	busa = busa0;
	188	iopte = iopte0;
	189	for (i = 0; i < npages; i++) {
	190	iopte_val(*iopte) = MKIOPTE(page_to_pfn(page), IOPERM);
	191	iommu_invalidate_page(iommu->regs, busa);
	192	busa += PAGE_SIZE;
	193	iopte++;
	194	page++;
	195	}
	196
	197	iommu_flush_iotlb(iopte0, npages);
	198
	199	return busa0;
	200	}
	201
260489fa	202	static u32 iommu_get_scsi_one(struct device dev, char vaddr, unsigned int len)
1da177e4 LT	203	{
	204	unsigned long off;
	205	int npages;
	206	struct page *page;
	207	u32 busa;
	208
	209	off = (unsigned long)vaddr & ~PAGE_MASK;
	210	npages = (off + len + PAGE_SIZE-1) >> PAGE_SHIFT;
	211	page = virt_to_page((unsigned long)vaddr & PAGE_MASK);
260489fa	212	busa = iommu_get_one(dev, page, npages);
1da177e4 LT	213	return busa + off;
	214	}
	215
260489fa	216	static __u32 iommu_get_scsi_one_gflush(struct device dev, char vaddr, unsigned long len)
1da177e4 LT	217	{
1da177e4 LT	218	flush_page_for_dma(0);
260489fa	219	return iommu_get_scsi_one(dev, vaddr, len);
1da177e4 LT	220	}
1da177e4 LT	221
260489fa	222	static __u32 iommu_get_scsi_one_pflush(struct device dev, char vaddr, unsigned long len)
1da177e4 LT	223	{
	224	unsigned long page = ((unsigned long) vaddr) & PAGE_MASK;
	225
	226	while(page < ((unsigned long)(vaddr + len))) {
	227	flush_page_for_dma(page);
	228	page += PAGE_SIZE;
	229	}
260489fa	230	return iommu_get_scsi_one(dev, vaddr, len);
1da177e4 LT	231	}
1da177e4 LT	232
260489fa	233	static void iommu_get_scsi_sgl_gflush(struct device dev, struct scatterlist sg, int sz)
1da177e4 LT	234	{
	235	int n;
	236
	237	flush_page_for_dma(0);
	238	while (sz != 0) {
	239	--sz;
	240	n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT;
aa83a26a RR	241	sg->dma_address = iommu_get_one(dev, sg_page(sg), n) + sg->offset;
aa83a26a RR	242	sg->dma_length = sg->length;
0912a5db	243	sg = sg_next(sg);
1da177e4 LT	244	}
	245	}
	246
260489fa	247	static void iommu_get_scsi_sgl_pflush(struct device dev, struct scatterlist sg, int sz)
1da177e4 LT	248	{
	249	unsigned long page, oldpage = 0;
	250	int n, i;
	251
	252	while(sz != 0) {
	253	--sz;
	254
	255	n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT;
	256
	257	/*
	258	* We expect unmapped highmem pages to be not in the cache.
	259	* XXX Is this a good assumption?
	260	* XXX What if someone else unmaps it here and races us?
	261	*/
58b053e4	262	if ((page = (unsigned long) page_address(sg_page(sg))) != 0) {
1da177e4 LT	263	for (i = 0; i < n; i++) {
	264	if (page != oldpage) { /* Already flushed? */
	265	flush_page_for_dma(page);
	266	oldpage = page;
	267	}
	268	page += PAGE_SIZE;
	269	}
	270	}
	271
aa83a26a RR	272	sg->dma_address = iommu_get_one(dev, sg_page(sg), n) + sg->offset;
aa83a26a RR	273	sg->dma_length = sg->length;
0912a5db	274	sg = sg_next(sg);
1da177e4 LT	275	}
	276	}
	277
260489fa	278	static void iommu_release_one(struct device *dev, u32 busa, int npages)
1da177e4	279	{
260489fa	280	struct iommu_struct *iommu = dev->archdata.iommu;
1da177e4 LT	281	int ioptex;
	282	int i;
	283
1ae61388	284	BUG_ON(busa < iommu->start);
1da177e4 LT	285	ioptex = (busa - iommu->start) >> PAGE_SHIFT;
	286	for (i = 0; i < npages; i++) {
	287	iopte_val(iommu->page_table[ioptex + i]) = 0;
	288	iommu_invalidate_page(iommu->regs, busa);
	289	busa += PAGE_SIZE;
	290	}
	291	bit_map_clear(&iommu->usemap, ioptex, npages);
	292	}
	293
260489fa	294	static void iommu_release_scsi_one(struct device *dev, __u32 vaddr, unsigned long len)
1da177e4 LT	295	{
	296	unsigned long off;
	297	int npages;
	298
	299	off = vaddr & ~PAGE_MASK;
	300	npages = (off + len + PAGE_SIZE-1) >> PAGE_SHIFT;
260489fa	301	iommu_release_one(dev, vaddr & PAGE_MASK, npages);
1da177e4 LT	302	}
1da177e4 LT	303
260489fa	304	static void iommu_release_scsi_sgl(struct device dev, struct scatterlist sg, int sz)
1da177e4 LT	305	{
	306	int n;
	307
	308	while(sz != 0) {
	309	--sz;
	310
	311	n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT;
aa83a26a RR	312	iommu_release_one(dev, sg->dma_address & PAGE_MASK, n);
aa83a26a RR	313	sg->dma_address = 0x21212121;
0912a5db	314	sg = sg_next(sg);
1da177e4 LT	315	}
	316	}
	317
	318	#ifdef CONFIG_SBUS
4b1c5df2 DM	319	static int iommu_map_dma_area(struct device dev, dma_addr_t pba, unsigned long va,
4b1c5df2 DM	320	unsigned long addr, int len)
1da177e4	321	{
4b1c5df2	322	struct iommu_struct *iommu = dev->archdata.iommu;
1da177e4	323	unsigned long page, end;
1da177e4 LT	324	iopte_t *iopte = iommu->page_table;
	325	iopte_t *first;
	326	int ioptex;
	327
1ae61388 ES	328	BUG_ON((va & ~PAGE_MASK) != 0);
	329	BUG_ON((addr & ~PAGE_MASK) != 0);
	330	BUG_ON((len & ~PAGE_MASK) != 0);
1da177e4 LT	331
	332	/* page color = physical address */
	333	ioptex = bit_map_string_get(&iommu->usemap, len >> PAGE_SHIFT,
	334	addr >> PAGE_SHIFT);
	335	if (ioptex < 0)
	336	panic("iommu out");
	337
	338	iopte += ioptex;
	339	first = iopte;
	340	end = addr + len;
	341	while(addr < end) {
	342	page = va;
	343	{
	344	pgd_t *pgdp;
	345	pmd_t *pmdp;
	346	pte_t *ptep;
	347
	348	if (viking_mxcc_present)
	349	viking_mxcc_flush_page(page);
	350	else if (viking_flush)
	351	viking_flush_page(page);
	352	else
	353	__flush_page_to_ram(page);
	354
	355	pgdp = pgd_offset(&init_mm, addr);
	356	pmdp = pmd_offset(pgdp, addr);
	357	ptep = pte_offset_map(pmdp, addr);
	358
	359	set_pte(ptep, mk_pte(virt_to_page(page), dvma_prot));
	360	}
	361	iopte_val(*iopte++) =
	362	MKIOPTE(page_to_pfn(virt_to_page(page)), ioperm_noc);
	363	addr += PAGE_SIZE;
	364	va += PAGE_SIZE;
	365	}
	366	/* P3: why do we need this?
	367	*
	368	* DAVEM: Because there are several aspects, none of which
	369	* are handled by a single interface. Some cpus are
	370	* completely not I/O DMA coherent, and some have
	371	* virtually indexed caches. The driver DMA flushing
	372	* methods handle the former case, but here during
	373	* IOMMU page table modifications, and usage of non-cacheable
	374	* cpu mappings of pages potentially in the cpu caches, we have
	375	* to handle the latter case as well.
	376	*/
	377	flush_cache_all();
	378	iommu_flush_iotlb(first, len >> PAGE_SHIFT);
	379	flush_tlb_all();
	380	iommu_invalidate(iommu->regs);
	381
	382	*pba = iommu->start + (ioptex << PAGE_SHIFT);
	383	return 0;
	384	}
	385
4b1c5df2	386	static void iommu_unmap_dma_area(struct device *dev, unsigned long busa, int len)
1da177e4	387	{
4b1c5df2	388	struct iommu_struct *iommu = dev->archdata.iommu;
1da177e4 LT	389	iopte_t *iopte = iommu->page_table;
	390	unsigned long end;
	391	int ioptex = (busa - iommu->start) >> PAGE_SHIFT;
	392
1ae61388 ES	393	BUG_ON((busa & ~PAGE_MASK) != 0);
1ae61388 ES	394	BUG_ON((len & ~PAGE_MASK) != 0);
1da177e4 LT	395
	396	iopte += ioptex;
	397	end = busa + len;
	398	while (busa < end) {
	399	iopte_val(*iopte++) = 0;
	400	busa += PAGE_SIZE;
	401	}
	402	flush_tlb_all();
	403	iommu_invalidate(iommu->regs);
	404	bit_map_clear(&iommu->usemap, ioptex, len >> PAGE_SHIFT);
	405	}
1da177e4 LT	406	#endif
1da177e4 LT	407
d894d964 DM	408	static const struct sparc32_dma_ops iommu_dma_gflush_ops = {
	409	.get_scsi_one = iommu_get_scsi_one_gflush,
	410	.get_scsi_sgl = iommu_get_scsi_sgl_gflush,
	411	.release_scsi_one = iommu_release_scsi_one,
	412	.release_scsi_sgl = iommu_release_scsi_sgl,
	413	#ifdef CONFIG_SBUS
	414	.map_dma_area = iommu_map_dma_area,
	415	.unmap_dma_area = iommu_unmap_dma_area,
	416	#endif
	417	};
	418
	419	static const struct sparc32_dma_ops iommu_dma_pflush_ops = {
	420	.get_scsi_one = iommu_get_scsi_one_pflush,
	421	.get_scsi_sgl = iommu_get_scsi_sgl_pflush,
	422	.release_scsi_one = iommu_release_scsi_one,
	423	.release_scsi_sgl = iommu_release_scsi_sgl,
	424	#ifdef CONFIG_SBUS
	425	.map_dma_area = iommu_map_dma_area,
	426	.unmap_dma_area = iommu_unmap_dma_area,
	427	#endif
	428	};
	429
1da177e4 LT	430	void __init ld_mmu_iommu(void)
1da177e4 LT	431	{
5d83d666	432	if (flush_page_for_dma_global) {
1da177e4	433	/* flush_page_for_dma flushes everything, no matter of what page is it */
d894d964	434	sparc32_dma_ops = &iommu_dma_gflush_ops;
1da177e4	435	} else {
d894d964	436	sparc32_dma_ops = &iommu_dma_pflush_ops;
1da177e4	437	}
1da177e4 LT	438
	439	if (viking_mxcc_present \|\| srmmu_modtype == HyperSparc) {
	440	dvma_prot = __pgprot(SRMMU_CACHE \| SRMMU_ET_PTE \| SRMMU_PRIV);
	441	ioperm_noc = IOPTE_CACHE \| IOPTE_WRITE \| IOPTE_VALID;
	442	} else {
	443	dvma_prot = __pgprot(SRMMU_ET_PTE \| SRMMU_PRIV);
	444	ioperm_noc = IOPTE_WRITE \| IOPTE_VALID;
	445	}
	446	}