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sparse-vmemmap: specify vmemmap population range in bytes
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / sparc / mm / init_64.c
CommitLineData
b00dc837 1/*
1da177e4
LT		 2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
c4bce90e 8#include <linux/module.h>
1da177e4
LT		 9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/string.h>
12#include <linux/init.h>
13#include <linux/bootmem.h>
14#include <linux/mm.h>
15#include <linux/hugetlb.h>
1da177e4
LT		 16#include <linux/initrd.h>
17#include <linux/swap.h>
18#include <linux/pagemap.h>
c9cf5528 19#include <linux/poison.h>
1da177e4
LT		 20#include <linux/fs.h>
21#include <linux/seq_file.h>
05e14cb3 22#include <linux/kprobes.h>
1ac4f5eb 23#include <linux/cache.h>
13edad7a 24#include <linux/sort.h>
5cbc3073 25#include <linux/percpu.h>
95f72d1e 26#include <linux/memblock.h>
919ee677 27#include <linux/mmzone.h>
5a0e3ad6 28#include <linux/gfp.h>
1da177e4
LT		 29
30#include <asm/head.h>
1da177e4
LT		 31#include <asm/page.h>
32#include <asm/pgalloc.h>
33#include <asm/pgtable.h>
34#include <asm/oplib.h>
35#include <asm/iommu.h>
36#include <asm/io.h>
37#include <asm/uaccess.h>
38#include <asm/mmu_context.h>
39#include <asm/tlbflush.h>
40#include <asm/dma.h>
41#include <asm/starfire.h>
42#include <asm/tlb.h>
43#include <asm/spitfire.h>
44#include <asm/sections.h>
517af332 45#include <asm/tsb.h>
481295f9 46#include <asm/hypervisor.h>
372b07bb 47#include <asm/prom.h>
5cbc3073 48#include <asm/mdesc.h>
3d5ae6b6 49#include <asm/cpudata.h>
4f70f7a9 50#include <asm/irq.h>
1da177e4 51
27137e52 52#include "init_64.h"
9cc3a1ac 53
4f93d21d 54unsigned long kern_linear_pte_xor[4] __read_mostly;
9cc3a1ac 55
4f93d21d
DM		 56/* A bitmap, two bits for every 256MB of physical memory. These two
57 * bits determine what page size we use for kernel linear
58 * translations. They form an index into kern_linear_pte_xor[]. The
59 * value in the indexed slot is XOR'd with the TLB miss virtual
60 * address to form the resulting TTE. The mapping is:
61 *
62 * 0 ==> 4MB
63 * 1 ==> 256MB
64 * 2 ==> 2GB
65 * 3 ==> 16GB
66 *
67 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
68 * support 2GB pages, and hopefully future cpus will support the 16GB
69 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
70 * if these larger page sizes are not supported by the cpu.
71 *
72 * It would be nice to determine this from the machine description
73 * 'cpu' properties, but we need to have this table setup before the
74 * MDESC is initialized.
9cc3a1ac
DM		 75 */
76unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
77
d1acb421 78#ifndef CONFIG_DEBUG_PAGEALLOC
4f93d21d
DM		 79/* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
80 * Space is allocated for this right after the trap table in
81 * arch/sparc64/kernel/head.S
2d9e2763
DM		 82 */
83extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
d1acb421 84#endif
d7744a09 85
ce33fdc5
DM		 86static unsigned long cpu_pgsz_mask;
87
13edad7a
DM		 88#define MAX_BANKS 32
89
7c9503b8
GKH		 90static struct linux_prom64_registers pavail[MAX_BANKS];
91static int pavail_ents;
13edad7a
DM		 92
93static int cmp_p64(const void *a, const void *b)
94{
95 const struct linux_prom64_registers *x = a, *y = b;
96
97 if (x->phys_addr > y->phys_addr)
98 return 1;
99 if (x->phys_addr < y->phys_addr)
100 return -1;
101 return 0;
102}
103
104static void __init read_obp_memory(const char *property,
105 struct linux_prom64_registers *regs,
106 int *num_ents)
107{
8d125562 108 phandle node = prom_finddevice("/memory");
13edad7a
DM		 109 int prop_size = prom_getproplen(node, property);
110 int ents, ret, i;
111
112 ents = prop_size / sizeof(struct linux_prom64_registers);
113 if (ents > MAX_BANKS) {
114 prom_printf("The machine has more %s property entries than "
115 "this kernel can support (%d).\n",
116 property, MAX_BANKS);
117 prom_halt();
118 }
119
120 ret = prom_getproperty(node, property, (char *) regs, prop_size);
121 if (ret == -1) {
5da444aa
AM		 122 prom_printf("Couldn't get %s property from /memory.\n",
123 property);
13edad7a
DM		 124 prom_halt();
125 }
126
13edad7a
DM		 127 /* Sanitize what we got from the firmware, by page aligning
128 * everything.
129 */
130 for (i = 0; i < ents; i++) {
131 unsigned long base, size;
132
133 base = regs[i].phys_addr;
134 size = regs[i].reg_size;
10147570 135
13edad7a
DM		 136 size &= PAGE_MASK;
137 if (base & ~PAGE_MASK) {
138 unsigned long new_base = PAGE_ALIGN(base);
139
140 size -= new_base - base;
141 if ((long) size < 0L)
142 size = 0UL;
143 base = new_base;
144 }
0015d3d6
DM		 145 if (size == 0UL) {
146 /* If it is empty, simply get rid of it.
147 * This simplifies the logic of the other
148 * functions that process these arrays.
149 */
150 memmove(&regs[i], &regs[i + 1],
151 (ents - i - 1) * sizeof(regs[0]));
486ad10a 152 i--;
0015d3d6
DM		 153 ents--;
154 continue;
486ad10a 155 }
0015d3d6
DM		 156 regs[i].phys_addr = base;
157 regs[i].reg_size = size;
486ad10a
DM		 158 }
159
160 *num_ents = ents;
161
c9c10830 162 sort(regs, ents, sizeof(struct linux_prom64_registers),
13edad7a
DM		 163 cmp_p64, NULL);
164}
1da177e4 165
d8ed1d43
DM		 166unsigned long sparc64_valid_addr_bitmap[VALID_ADDR_BITMAP_BYTES /
167 sizeof(unsigned long)];
917c3660 168EXPORT_SYMBOL(sparc64_valid_addr_bitmap);
1da177e4 169
d1112018 170/* Kernel physical address base and size in bytes. */
1ac4f5eb
DM		 171unsigned long kern_base __read_mostly;
172unsigned long kern_size __read_mostly;
1da177e4 173
1da177e4
LT		 174/* Initial ramdisk setup */
175extern unsigned long sparc_ramdisk_image64;
176extern unsigned int sparc_ramdisk_image;
177extern unsigned int sparc_ramdisk_size;
178
1ac4f5eb 179struct page *mem_map_zero __read_mostly;
35802c0b 180EXPORT_SYMBOL(mem_map_zero);
1da177e4 181
0835ae0f
DM		 182unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
183
184unsigned long sparc64_kern_pri_context __read_mostly;
185unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
186unsigned long sparc64_kern_sec_context __read_mostly;
187
64658743 188int num_kernel_image_mappings;
1da177e4 189
1da177e4
LT		 190#ifdef CONFIG_DEBUG_DCFLUSH
191atomic_t dcpage_flushes = ATOMIC_INIT(0);
192#ifdef CONFIG_SMP
193atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
194#endif
195#endif
196
7a591cfe 197inline void flush_dcache_page_impl(struct page *page)
1da177e4 198{
7a591cfe 199 BUG_ON(tlb_type == hypervisor);
1da177e4
LT		 200#ifdef CONFIG_DEBUG_DCFLUSH
201 atomic_inc(&dcpage_flushes);
202#endif
203
204#ifdef DCACHE_ALIASING_POSSIBLE
205 __flush_dcache_page(page_address(page),
206 ((tlb_type == spitfire) &&
207 page_mapping(page) != NULL));
208#else
209 if (page_mapping(page) != NULL &&
210 tlb_type == spitfire)
211 __flush_icache_page(__pa(page_address(page)));
212#endif
213}
214
215#define PG_dcache_dirty PG_arch_1
22adb358
DM		 216#define PG_dcache_cpu_shift 32UL
217#define PG_dcache_cpu_mask \
218 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
1da177e4
LT		 219
220#define dcache_dirty_cpu(page) \
48b0e548 221 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
1da177e4 222
d979f179 223static inline void set_dcache_dirty(struct page *page, int this_cpu)
1da177e4
LT		 224{
225 unsigned long mask = this_cpu;
48b0e548
DM		 226 unsigned long non_cpu_bits;
227
228 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
229 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
230
1da177e4
LT		 231 __asm__ __volatile__("1:\n\t"
232 "ldx [%2], %%g7\n\t"
233 "and %%g7, %1, %%g1\n\t"
234 "or %%g1, %0, %%g1\n\t"
235 "casx [%2], %%g7, %%g1\n\t"
236 "cmp %%g7, %%g1\n\t"
237 "bne,pn %%xcc, 1b\n\t"
b445e26c 238 " nop"
1da177e4
LT		 239 : /* no outputs */
240 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
241 : "g1", "g7");
242}
243
d979f179 244static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
1da177e4
LT		 245{
246 unsigned long mask = (1UL << PG_dcache_dirty);
247
248 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
249 "1:\n\t"
250 "ldx [%2], %%g7\n\t"
48b0e548 251 "srlx %%g7, %4, %%g1\n\t"
1da177e4
LT		 252 "and %%g1, %3, %%g1\n\t"
253 "cmp %%g1, %0\n\t"
254 "bne,pn %%icc, 2f\n\t"
255 " andn %%g7, %1, %%g1\n\t"
256 "casx [%2], %%g7, %%g1\n\t"
257 "cmp %%g7, %%g1\n\t"
258 "bne,pn %%xcc, 1b\n\t"
b445e26c 259 " nop\n"
1da177e4
LT		 260 "2:"
261 : /* no outputs */
262 : "r" (cpu), "r" (mask), "r" (&page->flags),
48b0e548
DM		 263 "i" (PG_dcache_cpu_mask),
264 "i" (PG_dcache_cpu_shift)
1da177e4
LT		 265 : "g1", "g7");
266}
267
517af332
DM		 268static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
269{
270 unsigned long tsb_addr = (unsigned long) ent;
271
3b3ab2eb 272 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
517af332
DM		 273 tsb_addr = __pa(tsb_addr);
274
275 __tsb_insert(tsb_addr, tag, pte);
276}
277
c4bce90e 278unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
c4bce90e 279
ff9aefbf 280static void flush_dcache(unsigned long pfn)
1da177e4 281{
ff9aefbf 282 struct page *page;
7a591cfe 283
ff9aefbf 284 page = pfn_to_page(pfn);
1a78cedb 285 if (page) {
7a591cfe 286 unsigned long pg_flags;
7a591cfe 287
ff9aefbf
SR		 288 pg_flags = page->flags;
289 if (pg_flags & (1UL << PG_dcache_dirty)) {
7a591cfe
DM		 290 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
291 PG_dcache_cpu_mask);
292 int this_cpu = get_cpu();
293
294 /* This is just to optimize away some function calls
295 * in the SMP case.
296 */
297 if (cpu == this_cpu)
298 flush_dcache_page_impl(page);
299 else
300 smp_flush_dcache_page_impl(page, cpu);
301
302 clear_dcache_dirty_cpu(page, cpu);
303
304 put_cpu();
305 }
1da177e4 306 }
ff9aefbf
SR		 307}
308
9e695d2e
DM		 309/* mm->context.lock must be held */
310static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
311 unsigned long tsb_hash_shift, unsigned long address,
312 unsigned long tte)
313{
314 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
315 unsigned long tag;
316
bcd896ba
DM		 317 if (unlikely(!tsb))
318 return;
319
9e695d2e
DM		 320 tsb += ((address >> tsb_hash_shift) &
321 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
322 tag = (address >> 22UL);
323 tsb_insert(tsb, tag, tte);
324}
325
bcd896ba
DM		 326#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
327static inline bool is_hugetlb_pte(pte_t pte)
328{
329 if ((tlb_type == hypervisor &&
330 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
331 (tlb_type != hypervisor &&
332 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U))
333 return true;
334 return false;
335}
336#endif
337
4b3073e1 338void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
ff9aefbf
SR		 339{
340 struct mm_struct *mm;
bcd896ba 341 unsigned long flags;
4b3073e1 342 pte_t pte = *ptep;
ff9aefbf
SR		 343
344 if (tlb_type != hypervisor) {
345 unsigned long pfn = pte_pfn(pte);
346
347 if (pfn_valid(pfn))
348 flush_dcache(pfn);
349 }
bd40791e
DM		 350
351 mm = vma->vm_mm;
7a1ac526
DM		 352
353 spin_lock_irqsave(&mm->context.lock, flags);
354
9e695d2e 355#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
bcd896ba
DM		 356 if (mm->context.huge_pte_count && is_hugetlb_pte(pte))
357 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, HPAGE_SHIFT,
358 address, pte_val(pte));
359 else
dcc1e8dd 360#endif
bcd896ba
DM		 361 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
362 address, pte_val(pte));
7a1ac526
DM		 363
364 spin_unlock_irqrestore(&mm->context.lock, flags);
1da177e4
LT		 365}
366
367void flush_dcache_page(struct page *page)
368{
a9546f59
DM		 369 struct address_space *mapping;
370 int this_cpu;
1da177e4 371
7a591cfe
DM		 372 if (tlb_type == hypervisor)
373 return;
374
a9546f59
DM		 375 /* Do not bother with the expensive D-cache flush if it
376 * is merely the zero page. The 'bigcore' testcase in GDB
377 * causes this case to run millions of times.
378 */
379 if (page == ZERO_PAGE(0))
380 return;
381
382 this_cpu = get_cpu();
383
384 mapping = page_mapping(page);
1da177e4 385 if (mapping && !mapping_mapped(mapping)) {
a9546f59 386 int dirty = test_bit(PG_dcache_dirty, &page->flags);
1da177e4 387 if (dirty) {
a9546f59
DM		 388 int dirty_cpu = dcache_dirty_cpu(page);
389
1da177e4
LT		 390 if (dirty_cpu == this_cpu)
391 goto out;
392 smp_flush_dcache_page_impl(page, dirty_cpu);
393 }
394 set_dcache_dirty(page, this_cpu);
395 } else {
396 /* We could delay the flush for the !page_mapping
397 * case too. But that case is for exec env/arg
398 * pages and those are %99 certainly going to get
399 * faulted into the tlb (and thus flushed) anyways.
400 */
401 flush_dcache_page_impl(page);
402 }
403
404out:
405 put_cpu();
406}
917c3660 407EXPORT_SYMBOL(flush_dcache_page);
1da177e4 408
05e14cb3 409void __kprobes flush_icache_range(unsigned long start, unsigned long end)
1da177e4 410{
a43fe0e7 411 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
1da177e4
LT		 412 if (tlb_type == spitfire) {
413 unsigned long kaddr;
414
a94aa253
DM		 415 /* This code only runs on Spitfire cpus so this is
416 * why we can assume _PAGE_PADDR_4U.
417 */
418 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
419 unsigned long paddr, mask = _PAGE_PADDR_4U;
420
421 if (kaddr >= PAGE_OFFSET)
422 paddr = kaddr & mask;
423 else {
424 pgd_t *pgdp = pgd_offset_k(kaddr);
425 pud_t *pudp = pud_offset(pgdp, kaddr);
426 pmd_t *pmdp = pmd_offset(pudp, kaddr);
427 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
428
429 paddr = pte_val(*ptep) & mask;
430 }
431 __flush_icache_page(paddr);
432 }
1da177e4
LT		 433 }
434}
917c3660 435EXPORT_SYMBOL(flush_icache_range);
1da177e4 436
1da177e4
LT		 437void mmu_info(struct seq_file *m)
438{
ce33fdc5
DM		 439 static const char *pgsz_strings[] = {
440 "8K", "64K", "512K", "4MB", "32MB",
441 "256MB", "2GB", "16GB",
442 };
443 int i, printed;
444
1da177e4
LT		 445 if (tlb_type == cheetah)
446 seq_printf(m, "MMU Type\t: Cheetah\n");
447 else if (tlb_type == cheetah_plus)
448 seq_printf(m, "MMU Type\t: Cheetah+\n");
449 else if (tlb_type == spitfire)
450 seq_printf(m, "MMU Type\t: Spitfire\n");
a43fe0e7
DM		 451 else if (tlb_type == hypervisor)
452 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
1da177e4
LT		 453 else
454 seq_printf(m, "MMU Type\t: ???\n");
455
ce33fdc5
DM		 456 seq_printf(m, "MMU PGSZs\t: ");
457 printed = 0;
458 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
459 if (cpu_pgsz_mask & (1UL << i)) {
460 seq_printf(m, "%s%s",
461 printed ? "," : "", pgsz_strings[i]);
462 printed++;
463 }
464 }
465 seq_putc(m, '\n');
466
1da177e4
LT		 467#ifdef CONFIG_DEBUG_DCFLUSH
468 seq_printf(m, "DCPageFlushes\t: %d\n",
469 atomic_read(&dcpage_flushes));
470#ifdef CONFIG_SMP
471 seq_printf(m, "DCPageFlushesXC\t: %d\n",
472 atomic_read(&dcpage_flushes_xcall));
473#endif /* CONFIG_SMP */
474#endif /* CONFIG_DEBUG_DCFLUSH */
475}
476
a94aa253
DM		 477struct linux_prom_translation prom_trans[512] __read_mostly;
478unsigned int prom_trans_ents __read_mostly;
479
1da177e4
LT		 480unsigned long kern_locked_tte_data;
481
c9c10830
DM		 482/* The obp translations are saved based on 8k pagesize, since obp can
483 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
74bf4312 484 * HI_OBP_ADDRESS range are handled in ktlb.S.
c9c10830 485 */
5085b4a5
DM		 486static inline int in_obp_range(unsigned long vaddr)
487{
488 return (vaddr >= LOW_OBP_ADDRESS &&
489 vaddr < HI_OBP_ADDRESS);
490}
491
c9c10830 492static int cmp_ptrans(const void *a, const void *b)
405599bd 493{
c9c10830 494 const struct linux_prom_translation *x = a, *y = b;
405599bd 495
c9c10830
DM		 496 if (x->virt > y->virt)
497 return 1;
498 if (x->virt < y->virt)
499 return -1;
500 return 0;
405599bd
DM		 501}
502
c9c10830 503/* Read OBP translations property into 'prom_trans[]'. */
9ad98c5b 504static void __init read_obp_translations(void)
405599bd 505{
c9c10830 506 int n, node, ents, first, last, i;
1da177e4
LT		 507
508 node = prom_finddevice("/virtual-memory");
509 n = prom_getproplen(node, "translations");
405599bd 510 if (unlikely(n == 0 || n == -1)) {
b206fc4c 511 prom_printf("prom_mappings: Couldn't get size.\n");
1da177e4
LT		 512 prom_halt();
513 }
405599bd 514 if (unlikely(n > sizeof(prom_trans))) {
5da444aa 515 prom_printf("prom_mappings: Size %d is too big.\n", n);
1da177e4
LT		 516 prom_halt();
517 }
405599bd 518
b206fc4c 519 if ((n = prom_getproperty(node, "translations",
405599bd
DM		 520 (char *)&prom_trans[0],
521 sizeof(prom_trans))) == -1) {
b206fc4c 522 prom_printf("prom_mappings: Couldn't get property.\n");
1da177e4
LT		 523 prom_halt();
524 }
9ad98c5b 525
b206fc4c 526 n = n / sizeof(struct linux_prom_translation);
9ad98c5b 527
c9c10830
DM		 528 ents = n;
529
530 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
531 cmp_ptrans, NULL);
532
533 /* Now kick out all the non-OBP entries. */
534 for (i = 0; i < ents; i++) {
535 if (in_obp_range(prom_trans[i].virt))
536 break;
537 }
538 first = i;
539 for (; i < ents; i++) {
540 if (!in_obp_range(prom_trans[i].virt))
541 break;
542 }
543 last = i;
544
545 for (i = 0; i < (last - first); i++) {
546 struct linux_prom_translation *src = &prom_trans[i + first];
547 struct linux_prom_translation *dest = &prom_trans[i];
548
549 *dest = *src;
550 }
551 for (; i < ents; i++) {
552 struct linux_prom_translation *dest = &prom_trans[i];
553 dest->virt = dest->size = dest->data = 0x0UL;
554 }
555
556 prom_trans_ents = last - first;
557
558 if (tlb_type == spitfire) {
559 /* Clear diag TTE bits. */
560 for (i = 0; i < prom_trans_ents; i++)
561 prom_trans[i].data &= ~0x0003fe0000000000UL;
562 }
f4142cba
DM		 563
564 /* Force execute bit on. */
565 for (i = 0; i < prom_trans_ents; i++)
566 prom_trans[i].data |= (tlb_type == hypervisor ?
567 _PAGE_EXEC_4V : _PAGE_EXEC_4U);
405599bd 568}
1da177e4 569
d82ace7d
DM		 570static void __init hypervisor_tlb_lock(unsigned long vaddr,
571 unsigned long pte,
572 unsigned long mmu)
573{
7db35f31
DM		 574 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
575
576 if (ret != 0) {
5da444aa 577 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
7db35f31 578 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
12e126ad
DM		 579 prom_halt();
580 }
d82ace7d
DM		 581}
582
c4bce90e
DM		 583static unsigned long kern_large_tte(unsigned long paddr);
584
898cf0ec 585static void __init remap_kernel(void)
405599bd
DM		 586{
587 unsigned long phys_page, tte_vaddr, tte_data;
64658743 588 int i, tlb_ent = sparc64_highest_locked_tlbent();
405599bd 589
1da177e4 590 tte_vaddr = (unsigned long) KERNBASE;
bff06d55 591 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
c4bce90e 592 tte_data = kern_large_tte(phys_page);
1da177e4
LT		 593
594 kern_locked_tte_data = tte_data;
595
d82ace7d
DM		 596 /* Now lock us into the TLBs via Hypervisor or OBP. */
597 if (tlb_type == hypervisor) {
64658743 598 for (i = 0; i < num_kernel_image_mappings; i++) {
d82ace7d
DM		 599 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
600 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
64658743
DM		 601 tte_vaddr += 0x400000;
602 tte_data += 0x400000;
d82ace7d
DM		 603 }
604 } else {
64658743
DM		 605 for (i = 0; i < num_kernel_image_mappings; i++) {
606 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
607 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
608 tte_vaddr += 0x400000;
609 tte_data += 0x400000;
d82ace7d 610 }
64658743 611 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
1da177e4 612 }
0835ae0f
DM		 613 if (tlb_type == cheetah_plus) {
614 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
615 CTX_CHEETAH_PLUS_NUC);
616 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
617 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
618 }
405599bd 619}
1da177e4 620
405599bd 621
c9c10830 622static void __init inherit_prom_mappings(void)
9ad98c5b 623{
405599bd 624 /* Now fixup OBP's idea about where we really are mapped. */
3c62a2d3 625 printk("Remapping the kernel... ");
405599bd 626 remap_kernel();
3c62a2d3 627 printk("done.\n");
1da177e4
LT		 628}
629
1da177e4
LT		 630void prom_world(int enter)
631{
1da177e4 632 if (!enter)
dff933da 633 set_fs(get_fs());
1da177e4 634
3487d1d4 635 __asm__ __volatile__("flushw");
1da177e4
LT		 636}
637
1da177e4
LT		 638void __flush_dcache_range(unsigned long start, unsigned long end)
639{
640 unsigned long va;
641
642 if (tlb_type == spitfire) {
643 int n = 0;
644
645 for (va = start; va < end; va += 32) {
646 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
647 if (++n >= 512)
648 break;
649 }
a43fe0e7 650 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1da177e4
LT		 651 start = __pa(start);
652 end = __pa(end);
653 for (va = start; va < end; va += 32)
654 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
655 "membar #Sync"
656 : /* no outputs */
657 : "r" (va),
658 "i" (ASI_DCACHE_INVALIDATE));
659 }
660}
917c3660 661EXPORT_SYMBOL(__flush_dcache_range);
1da177e4 662
85f1e1f6
DM		 663/* get_new_mmu_context() uses "cache + 1". */
664DEFINE_SPINLOCK(ctx_alloc_lock);
665unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
666#define MAX_CTX_NR (1UL << CTX_NR_BITS)
667#define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
668DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
669
1da177e4
LT		 670/* Caller does TLB context flushing on local CPU if necessary.
671 * The caller also ensures that CTX_VALID(mm->context) is false.
672 *
673 * We must be careful about boundary cases so that we never
674 * let the user have CTX 0 (nucleus) or we ever use a CTX
675 * version of zero (and thus NO_CONTEXT would not be caught
676 * by version mis-match tests in mmu_context.h).
a0663a79
DM		 677 *
678 * Always invoked with interrupts disabled.
1da177e4
LT		 679 */
680void get_new_mmu_context(struct mm_struct *mm)
681{
682 unsigned long ctx, new_ctx;
683 unsigned long orig_pgsz_bits;
a77754b4 684 unsigned long flags;
a0663a79 685 int new_version;
1da177e4 686
a77754b4 687 spin_lock_irqsave(&ctx_alloc_lock, flags);
1da177e4
LT		 688 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
689 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
690 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
a0663a79 691 new_version = 0;
1da177e4
LT		 692 if (new_ctx >= (1 << CTX_NR_BITS)) {
693 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
694 if (new_ctx >= ctx) {
695 int i;
696 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
697 CTX_FIRST_VERSION;
698 if (new_ctx == 1)
699 new_ctx = CTX_FIRST_VERSION;
700
701 /* Don't call memset, for 16 entries that's just
702 * plain silly...
703 */
704 mmu_context_bmap[0] = 3;
705 mmu_context_bmap[1] = 0;
706 mmu_context_bmap[2] = 0;
707 mmu_context_bmap[3] = 0;
708 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
709 mmu_context_bmap[i + 0] = 0;
710 mmu_context_bmap[i + 1] = 0;
711 mmu_context_bmap[i + 2] = 0;
712 mmu_context_bmap[i + 3] = 0;
713 }
a0663a79 714 new_version = 1;
1da177e4
LT		 715 goto out;
716 }
717 }
718 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
719 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
720out:
721 tlb_context_cache = new_ctx;
722 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
a77754b4 723 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
a0663a79
DM		 724
725 if (unlikely(new_version))
726 smp_new_mmu_context_version();
1da177e4
LT		 727}
728
919ee677
DM		 729static int numa_enabled = 1;
730static int numa_debug;
731
732static int __init early_numa(char *p)
1da177e4 733{
919ee677
DM		 734 if (!p)
735 return 0;
736
737 if (strstr(p, "off"))
738 numa_enabled = 0;
d1112018 739
919ee677
DM		 740 if (strstr(p, "debug"))
741 numa_debug = 1;
d1112018 742
919ee677 743 return 0;
d1112018 744}
919ee677
DM		 745early_param("numa", early_numa);
746
747#define numadbg(f, a...) \
748do { if (numa_debug) \
749 printk(KERN_INFO f, ## a); \
750} while (0)
d1112018 751
4e82c9a6
DM		 752static void __init find_ramdisk(unsigned long phys_base)
753{
754#ifdef CONFIG_BLK_DEV_INITRD
755 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
756 unsigned long ramdisk_image;
757
758 /* Older versions of the bootloader only supported a
759 * 32-bit physical address for the ramdisk image
760 * location, stored at sparc_ramdisk_image. Newer
761 * SILO versions set sparc_ramdisk_image to zero and
762 * provide a full 64-bit physical address at
763 * sparc_ramdisk_image64.
764 */
765 ramdisk_image = sparc_ramdisk_image;
766 if (!ramdisk_image)
767 ramdisk_image = sparc_ramdisk_image64;
768
769 /* Another bootloader quirk. The bootloader normalizes
770 * the physical address to KERNBASE, so we have to
771 * factor that back out and add in the lowest valid
772 * physical page address to get the true physical address.
773 */
774 ramdisk_image -= KERNBASE;
775 ramdisk_image += phys_base;
776
919ee677
DM		 777 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
778 ramdisk_image, sparc_ramdisk_size);
779
4e82c9a6
DM		 780 initrd_start = ramdisk_image;
781 initrd_end = ramdisk_image + sparc_ramdisk_size;
3b2a7e23 782
95f72d1e 783 memblock_reserve(initrd_start, sparc_ramdisk_size);
d45100f7
DM		 784
785 initrd_start += PAGE_OFFSET;
786 initrd_end += PAGE_OFFSET;
4e82c9a6
DM		 787 }
788#endif
789}
790
919ee677
DM		 791struct node_mem_mask {
792 unsigned long mask;
793 unsigned long val;
919ee677
DM		 794};
795static struct node_mem_mask node_masks[MAX_NUMNODES];
796static int num_node_masks;
797
798int numa_cpu_lookup_table[NR_CPUS];
799cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
800
801#ifdef CONFIG_NEED_MULTIPLE_NODES
919ee677
DM		 802
803struct mdesc_mblock {
804 u64 base;
805 u64 size;
806 u64 offset; /* RA-to-PA */
807};
808static struct mdesc_mblock *mblocks;
809static int num_mblocks;
810
811static unsigned long ra_to_pa(unsigned long addr)
812{
813 int i;
814
815 for (i = 0; i < num_mblocks; i++) {
816 struct mdesc_mblock *m = &mblocks[i];
817
818 if (addr >= m->base &&
819 addr < (m->base + m->size)) {
820 addr += m->offset;
821 break;
822 }
823 }
824 return addr;
825}
826
827static int find_node(unsigned long addr)
828{
829 int i;
830
831 addr = ra_to_pa(addr);
832 for (i = 0; i < num_node_masks; i++) {
833 struct node_mem_mask *p = &node_masks[i];
834
835 if ((addr & p->mask) == p->val)
836 return i;
837 }
838 return -1;
839}
840
f9b18db3 841static u64 memblock_nid_range(u64 start, u64 end, int *nid)
919ee677
DM		 842{
843 *nid = find_node(start);
844 start += PAGE_SIZE;
845 while (start < end) {
846 int n = find_node(start);
847
848 if (n != *nid)
849 break;
850 start += PAGE_SIZE;
851 }
852
c918dcce
DM		 853 if (start > end)
854 start = end;
855
919ee677
DM		 856 return start;
857}
919ee677
DM		 858#endif
859
860/* This must be invoked after performing all of the necessary
2a4814df 861 * memblock_set_node() calls for 'nid'. We need to be able to get
919ee677 862 * correct data from get_pfn_range_for_nid().
f1cfdb55 863 */
919ee677
DM		 864static void __init allocate_node_data(int nid)
865{
919ee677 866 struct pglist_data *p;
aa6f0790 867 unsigned long start_pfn, end_pfn;
919ee677 868#ifdef CONFIG_NEED_MULTIPLE_NODES
aa6f0790
PG		 869 unsigned long paddr;
870
9d1e2492 871 paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
919ee677
DM		 872 if (!paddr) {
873 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
874 prom_halt();
875 }
876 NODE_DATA(nid) = __va(paddr);
877 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
878
625d693e 879 NODE_DATA(nid)->node_id = nid;
919ee677
DM		 880#endif
881
882 p = NODE_DATA(nid);
883
884 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
885 p->node_start_pfn = start_pfn;
886 p->node_spanned_pages = end_pfn - start_pfn;
919ee677
DM		 887}
888
889static void init_node_masks_nonnuma(void)
d1112018 890{
1da177e4
LT		 891 int i;
892
919ee677 893 numadbg("Initializing tables for non-numa.\n");
6fc5bae7 894
919ee677
DM		 895 node_masks[0].mask = node_masks[0].val = 0;
896 num_node_masks = 1;
d1112018 897
919ee677
DM		 898 for (i = 0; i < NR_CPUS; i++)
899 numa_cpu_lookup_table[i] = 0;
1da177e4 900
fb1fece5 901 cpumask_setall(&numa_cpumask_lookup_table[0]);
919ee677
DM		 902}
903
904#ifdef CONFIG_NEED_MULTIPLE_NODES
905struct pglist_data *node_data[MAX_NUMNODES];
906
907EXPORT_SYMBOL(numa_cpu_lookup_table);
908EXPORT_SYMBOL(numa_cpumask_lookup_table);
909EXPORT_SYMBOL(node_data);
910
911struct mdesc_mlgroup {
912 u64 node;
913 u64 latency;
914 u64 match;
915 u64 mask;
916};
917static struct mdesc_mlgroup *mlgroups;
918static int num_mlgroups;
919
920static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
921 u32 cfg_handle)
922{
923 u64 arc;
924
925 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
926 u64 target = mdesc_arc_target(md, arc);
927 const u64 *val;
928
929 val = mdesc_get_property(md, target,
930 "cfg-handle", NULL);
931 if (val && *val == cfg_handle)
932 return 0;
933 }
934 return -ENODEV;
935}
936
937static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
938 u32 cfg_handle)
939{
940 u64 arc, candidate, best_latency = ~(u64)0;
941
942 candidate = MDESC_NODE_NULL;
943 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
944 u64 target = mdesc_arc_target(md, arc);
945 const char *name = mdesc_node_name(md, target);
946 const u64 *val;
947
948 if (strcmp(name, "pio-latency-group"))
949 continue;
950
951 val = mdesc_get_property(md, target, "latency", NULL);
952 if (!val)
953 continue;
954
955 if (*val < best_latency) {
956 candidate = target;
957 best_latency = *val;
958 }
959 }
960
961 if (candidate == MDESC_NODE_NULL)
962 return -ENODEV;
963
964 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
965}
966
967int of_node_to_nid(struct device_node *dp)
968{
969 const struct linux_prom64_registers *regs;
970 struct mdesc_handle *md;
971 u32 cfg_handle;
972 int count, nid;
973 u64 grp;
974
072bd413
DM		 975 /* This is the right thing to do on currently supported
976 * SUN4U NUMA platforms as well, as the PCI controller does
977 * not sit behind any particular memory controller.
978 */
919ee677
DM		 979 if (!mlgroups)
980 return -1;
981
982 regs = of_get_property(dp, "reg", NULL);
983 if (!regs)
984 return -1;
985
986 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
987
988 md = mdesc_grab();
989
990 count = 0;
991 nid = -1;
992 mdesc_for_each_node_by_name(md, grp, "group") {
993 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
994 nid = count;
995 break;
996 }
997 count++;
998 }
999
1000 mdesc_release(md);
1001
1002 return nid;
1003}
1004
01c45381 1005static void __init add_node_ranges(void)
919ee677 1006{
08b84798 1007 struct memblock_region *reg;
919ee677 1008
08b84798
BH		 1009 for_each_memblock(memory, reg) {
1010 unsigned long size = reg->size;
919ee677
DM		 1011 unsigned long start, end;
1012
08b84798 1013 start = reg->base;
919ee677
DM		 1014 end = start + size;
1015 while (start < end) {
1016 unsigned long this_end;
1017 int nid;
1018
35a1f0bd 1019 this_end = memblock_nid_range(start, end, &nid);
919ee677 1020
2a4814df 1021 numadbg("Setting memblock NUMA node nid[%d] "
919ee677
DM		 1022 "start[%lx] end[%lx]\n",
1023 nid, start, this_end);
1024
2a4814df 1025 memblock_set_node(start, this_end - start, nid);
919ee677
DM		 1026 start = this_end;
1027 }
1028 }
1029}
1030
1031static int __init grab_mlgroups(struct mdesc_handle *md)
1032{
1033 unsigned long paddr;
1034 int count = 0;
1035 u64 node;
1036
1037 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1038 count++;
1039 if (!count)
1040 return -ENOENT;
1041
95f72d1e 1042 paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
919ee677
DM		 1043 SMP_CACHE_BYTES);
1044 if (!paddr)
1045 return -ENOMEM;
1046
1047 mlgroups = __va(paddr);
1048 num_mlgroups = count;
1049
1050 count = 0;
1051 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1052 struct mdesc_mlgroup *m = &mlgroups[count++];
1053 const u64 *val;
1054
1055 m->node = node;
1056
1057 val = mdesc_get_property(md, node, "latency", NULL);
1058 m->latency = *val;
1059 val = mdesc_get_property(md, node, "address-match", NULL);
1060 m->match = *val;
1061 val = mdesc_get_property(md, node, "address-mask", NULL);
1062 m->mask = *val;
1063
90181136
SR		 1064 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1065 "match[%llx] mask[%llx]\n",
919ee677
DM		 1066 count - 1, m->node, m->latency, m->match, m->mask);
1067 }
1068
1069 return 0;
1070}
1071
1072static int __init grab_mblocks(struct mdesc_handle *md)
1073{
1074 unsigned long paddr;
1075 int count = 0;
1076 u64 node;
1077
1078 mdesc_for_each_node_by_name(md, node, "mblock")
1079 count++;
1080 if (!count)
1081 return -ENOENT;
1082
95f72d1e 1083 paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
919ee677
DM		 1084 SMP_CACHE_BYTES);
1085 if (!paddr)
1086 return -ENOMEM;
1087
1088 mblocks = __va(paddr);
1089 num_mblocks = count;
1090
1091 count = 0;
1092 mdesc_for_each_node_by_name(md, node, "mblock") {
1093 struct mdesc_mblock *m = &mblocks[count++];
1094 const u64 *val;
1095
1096 val = mdesc_get_property(md, node, "base", NULL);
1097 m->base = *val;
1098 val = mdesc_get_property(md, node, "size", NULL);
1099 m->size = *val;
1100 val = mdesc_get_property(md, node,
1101 "address-congruence-offset", NULL);
1102 m->offset = *val;
1103
90181136 1104 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
919ee677
DM		 1105 count - 1, m->base, m->size, m->offset);
1106 }
1107
1108 return 0;
1109}
1110
1111static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1112 u64 grp, cpumask_t *mask)
1113{
1114 u64 arc;
1115
fb1fece5 1116 cpumask_clear(mask);
919ee677
DM		 1117
1118 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1119 u64 target = mdesc_arc_target(md, arc);
1120 const char *name = mdesc_node_name(md, target);
1121 const u64 *id;
1122
1123 if (strcmp(name, "cpu"))
1124 continue;
1125 id = mdesc_get_property(md, target, "id", NULL);
e305cb8f 1126 if (*id < nr_cpu_ids)
fb1fece5 1127 cpumask_set_cpu(*id, mask);
919ee677
DM		 1128 }
1129}
1130
1131static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1132{
1133 int i;
1134
1135 for (i = 0; i < num_mlgroups; i++) {
1136 struct mdesc_mlgroup *m = &mlgroups[i];
1137 if (m->node == node)
1138 return m;
1139 }
1140 return NULL;
1141}
1142
1143static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1144 int index)
1145{
1146 struct mdesc_mlgroup *candidate = NULL;
1147 u64 arc, best_latency = ~(u64)0;
1148 struct node_mem_mask *n;
1149
1150 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1151 u64 target = mdesc_arc_target(md, arc);
1152 struct mdesc_mlgroup *m = find_mlgroup(target);
1153 if (!m)
1154 continue;
1155 if (m->latency < best_latency) {
1156 candidate = m;
1157 best_latency = m->latency;
1158 }
1159 }
1160 if (!candidate)
1161 return -ENOENT;
1162
1163 if (num_node_masks != index) {
1164 printk(KERN_ERR "Inconsistent NUMA state, "
1165 "index[%d] != num_node_masks[%d]\n",
1166 index, num_node_masks);
1167 return -EINVAL;
1168 }
1169
1170 n = &node_masks[num_node_masks++];
1171
1172 n->mask = candidate->mask;
1173 n->val = candidate->match;
1da177e4 1174
90181136 1175 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
919ee677 1176 index, n->mask, n->val, candidate->latency);
1da177e4 1177
919ee677
DM		 1178 return 0;
1179}
1180
1181static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1182 int index)
1183{
1184 cpumask_t mask;
1185 int cpu;
1186
1187 numa_parse_mdesc_group_cpus(md, grp, &mask);
1188
fb1fece5 1189 for_each_cpu(cpu, &mask)
919ee677 1190 numa_cpu_lookup_table[cpu] = index;
fb1fece5 1191 cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
919ee677
DM		 1192
1193 if (numa_debug) {
1194 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
fb1fece5 1195 for_each_cpu(cpu, &mask)
919ee677
DM		 1196 printk("%d ", cpu);
1197 printk("]\n");
1198 }
1199
1200 return numa_attach_mlgroup(md, grp, index);
1201}
1202
1203static int __init numa_parse_mdesc(void)
1204{
1205 struct mdesc_handle *md = mdesc_grab();
1206 int i, err, count;
1207 u64 node;
1208
1209 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1210 if (node == MDESC_NODE_NULL) {
1211 mdesc_release(md);
1212 return -ENOENT;
1213 }
1214
1215 err = grab_mblocks(md);
1216 if (err < 0)
1217 goto out;
1218
1219 err = grab_mlgroups(md);
1220 if (err < 0)
1221 goto out;
1222
1223 count = 0;
1224 mdesc_for_each_node_by_name(md, node, "group") {
1225 err = numa_parse_mdesc_group(md, node, count);
1226 if (err < 0)
1227 break;
1228 count++;
1229 }
1230
1231 add_node_ranges();
1232
1233 for (i = 0; i < num_node_masks; i++) {
1234 allocate_node_data(i);
1235 node_set_online(i);
1236 }
1237
1238 err = 0;
1239out:
1240 mdesc_release(md);
1241 return err;
1242}
1243
072bd413
DM		 1244static int __init numa_parse_jbus(void)
1245{
1246 unsigned long cpu, index;
1247
1248 /* NUMA node id is encoded in bits 36 and higher, and there is
1249 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1250 */
1251 index = 0;
1252 for_each_present_cpu(cpu) {
1253 numa_cpu_lookup_table[cpu] = index;
fb1fece5 1254 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
072bd413
DM		 1255 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1256 node_masks[index].val = cpu << 36UL;
1257
1258 index++;
1259 }
1260 num_node_masks = index;
1261
1262 add_node_ranges();
1263
1264 for (index = 0; index < num_node_masks; index++) {
1265 allocate_node_data(index);
1266 node_set_online(index);
1267 }
1268
1269 return 0;
1270}
1271
919ee677
DM		 1272static int __init numa_parse_sun4u(void)
1273{
072bd413
DM		 1274 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1275 unsigned long ver;
1276
1277 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1278 if ((ver >> 32UL) == __JALAPENO_ID ||
1279 (ver >> 32UL) == __SERRANO_ID)
1280 return numa_parse_jbus();
1281 }
919ee677
DM		 1282 return -1;
1283}
1284
1285static int __init bootmem_init_numa(void)
1286{
1287 int err = -1;
1288
1289 numadbg("bootmem_init_numa()\n");
1290
1291 if (numa_enabled) {
1292 if (tlb_type == hypervisor)
1293 err = numa_parse_mdesc();
1294 else
1295 err = numa_parse_sun4u();
1296 }
1297 return err;
1298}
1299
1300#else
1da177e4 1301
919ee677
DM		 1302static int bootmem_init_numa(void)
1303{
1304 return -1;
1305}
1306
1307#endif
1308
1309static void __init bootmem_init_nonnuma(void)
1310{
95f72d1e
YL		 1311 unsigned long top_of_ram = memblock_end_of_DRAM();
1312 unsigned long total_ram = memblock_phys_mem_size();
919ee677
DM		 1313
1314 numadbg("bootmem_init_nonnuma()\n");
1315
1316 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1317 top_of_ram, total_ram);
1318 printk(KERN_INFO "Memory hole size: %ldMB\n",
1319 (top_of_ram - total_ram) >> 20);
1320
1321 init_node_masks_nonnuma();
2a4814df 1322 memblock_set_node(0, (phys_addr_t)ULLONG_MAX, 0);
919ee677 1323 allocate_node_data(0);
919ee677
DM		 1324 node_set_online(0);
1325}
1326
919ee677
DM		 1327static unsigned long __init bootmem_init(unsigned long phys_base)
1328{
1329 unsigned long end_pfn;
919ee677 1330
95f72d1e 1331 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
919ee677
DM		 1332 max_pfn = max_low_pfn = end_pfn;
1333 min_low_pfn = (phys_base >> PAGE_SHIFT);
1334
1335 if (bootmem_init_numa() < 0)
1336 bootmem_init_nonnuma();
1337
625d693e
DM		 1338 /* Dump memblock with node info. */
1339 memblock_dump_all();
919ee677 1340
625d693e 1341 /* XXX cpu notifier XXX */
d1112018 1342
625d693e 1343 sparse_memory_present_with_active_regions(MAX_NUMNODES);
d1112018
DM		 1344 sparse_init();
1345
1da177e4
LT		 1346 return end_pfn;
1347}
1348
9cc3a1ac
DM		 1349static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1350static int pall_ents __initdata;
1351
56425306 1352#ifdef CONFIG_DEBUG_PAGEALLOC
896aef43
SR		 1353static unsigned long __ref kernel_map_range(unsigned long pstart,
1354 unsigned long pend, pgprot_t prot)
56425306
DM		 1355{
1356 unsigned long vstart = PAGE_OFFSET + pstart;
1357 unsigned long vend = PAGE_OFFSET + pend;
1358 unsigned long alloc_bytes = 0UL;
1359
1360 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
13edad7a 1361 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
56425306
DM		 1362 vstart, vend);
1363 prom_halt();
1364 }
1365
1366 while (vstart < vend) {
1367 unsigned long this_end, paddr = __pa(vstart);
1368 pgd_t *pgd = pgd_offset_k(vstart);
1369 pud_t *pud;
1370 pmd_t *pmd;
1371 pte_t *pte;
1372
1373 pud = pud_offset(pgd, vstart);
1374 if (pud_none(*pud)) {
1375 pmd_t *new;
1376
1377 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1378 alloc_bytes += PAGE_SIZE;
1379 pud_populate(&init_mm, pud, new);
1380 }
1381
1382 pmd = pmd_offset(pud, vstart);
1383 if (!pmd_present(*pmd)) {
1384 pte_t *new;
1385
1386 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1387 alloc_bytes += PAGE_SIZE;
1388 pmd_populate_kernel(&init_mm, pmd, new);
1389 }
1390
1391 pte = pte_offset_kernel(pmd, vstart);
1392 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1393 if (this_end > vend)
1394 this_end = vend;
1395
1396 while (vstart < this_end) {
1397 pte_val(*pte) = (paddr | pgprot_val(prot));
1398
1399 vstart += PAGE_SIZE;
1400 paddr += PAGE_SIZE;
1401 pte++;
1402 }
1403 }
1404
1405 return alloc_bytes;
1406}
1407
56425306 1408extern unsigned int kvmap_linear_patch[1];
9cc3a1ac
DM		 1409#endif /* CONFIG_DEBUG_PAGEALLOC */
1410
4f93d21d 1411static void __init kpte_set_val(unsigned long index, unsigned long val)
9cc3a1ac 1412{
4f93d21d 1413 unsigned long *ptr = kpte_linear_bitmap;
9cc3a1ac 1414
4f93d21d
DM		 1415 val <<= ((index % (BITS_PER_LONG / 2)) * 2);
1416 ptr += (index / (BITS_PER_LONG / 2));
9cc3a1ac 1417
4f93d21d
DM		 1418 *ptr |= val;
1419}
f7c00338 1420
4f93d21d
DM		 1421static const unsigned long kpte_shift_min = 28; /* 256MB */
1422static const unsigned long kpte_shift_max = 34; /* 16GB */
1423static const unsigned long kpte_shift_incr = 3;
9cc3a1ac 1424
4f93d21d
DM		 1425static unsigned long kpte_mark_using_shift(unsigned long start, unsigned long end,
1426 unsigned long shift)
1427{
1428 unsigned long size = (1UL << shift);
1429 unsigned long mask = (size - 1UL);
1430 unsigned long remains = end - start;
1431 unsigned long val;
9cc3a1ac 1432
4f93d21d
DM		 1433 if (remains < size || (start & mask))
1434 return start;
9cc3a1ac 1435
4f93d21d
DM		 1436 /* VAL maps:
1437 *
1438 * shift 28 --> kern_linear_pte_xor index 1
1439 * shift 31 --> kern_linear_pte_xor index 2
1440 * shift 34 --> kern_linear_pte_xor index 3
1441 */
1442 val = ((shift - kpte_shift_min) / kpte_shift_incr) + 1;
1443
1444 remains &= ~mask;
1445 if (shift != kpte_shift_max)
1446 remains = size;
1447
1448 while (remains) {
1449 unsigned long index = start >> kpte_shift_min;
1450
1451 kpte_set_val(index, val);
1452
1453 start += 1UL << kpte_shift_min;
1454 remains -= 1UL << kpte_shift_min;
1455 }
1456
1457 return start;
1458}
1459
1460static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1461{
1462 unsigned long smallest_size, smallest_mask;
1463 unsigned long s;
1464
1465 smallest_size = (1UL << kpte_shift_min);
1466 smallest_mask = (smallest_size - 1UL);
1467
1468 while (start < end) {
1469 unsigned long orig_start = start;
1470
1471 for (s = kpte_shift_max; s >= kpte_shift_min; s -= kpte_shift_incr) {
1472 start = kpte_mark_using_shift(start, end, s);
1473
1474 if (start != orig_start)
1475 break;
9cc3a1ac 1476 }
4f93d21d
DM		 1477
1478 if (start == orig_start)
1479 start = (start + smallest_size) & ~smallest_mask;
9cc3a1ac
DM		 1480 }
1481}
56425306 1482
8f361453 1483static void __init init_kpte_bitmap(void)
56425306 1484{
9cc3a1ac 1485 unsigned long i;
13edad7a
DM		 1486
1487 for (i = 0; i < pall_ents; i++) {
56425306
DM		 1488 unsigned long phys_start, phys_end;
1489
13edad7a
DM		 1490 phys_start = pall[i].phys_addr;
1491 phys_end = phys_start + pall[i].reg_size;
9cc3a1ac
DM		 1492
1493 mark_kpte_bitmap(phys_start, phys_end);
8f361453
DM		 1494 }
1495}
9cc3a1ac 1496
8f361453
DM		 1497static void __init kernel_physical_mapping_init(void)
1498{
9cc3a1ac 1499#ifdef CONFIG_DEBUG_PAGEALLOC
8f361453
DM		 1500 unsigned long i, mem_alloced = 0UL;
1501
1502 for (i = 0; i < pall_ents; i++) {
1503 unsigned long phys_start, phys_end;
1504
1505 phys_start = pall[i].phys_addr;
1506 phys_end = phys_start + pall[i].reg_size;
1507
56425306
DM		 1508 mem_alloced += kernel_map_range(phys_start, phys_end,
1509 PAGE_KERNEL);
56425306
DM		 1510 }
1511
1512 printk("Allocated %ld bytes for kernel page tables.\n",
1513 mem_alloced);
1514
1515 kvmap_linear_patch[0] = 0x01000000; /* nop */
1516 flushi(&kvmap_linear_patch[0]);
1517
1518 __flush_tlb_all();
9cc3a1ac 1519#endif
56425306
DM		 1520}
1521
9cc3a1ac 1522#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 1523void kernel_map_pages(struct page *page, int numpages, int enable)
1524{
1525 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1526 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1527
1528 kernel_map_range(phys_start, phys_end,
1529 (enable ? PAGE_KERNEL : __pgprot(0)));
1530
74bf4312
DM		 1531 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1532 PAGE_OFFSET + phys_end);
1533
56425306
DM		 1534 /* we should perform an IPI and flush all tlbs,
1535 * but that can deadlock->flush only current cpu.
1536 */
1537 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1538 PAGE_OFFSET + phys_end);
1539}
1540#endif
1541
10147570
DM		 1542unsigned long __init find_ecache_flush_span(unsigned long size)
1543{
0836a0eb
DM		 1544 int i;
1545
13edad7a
DM		 1546 for (i = 0; i < pavail_ents; i++) {
1547 if (pavail[i].reg_size >= size)
1548 return pavail[i].phys_addr;
0836a0eb
DM		 1549 }
1550
13edad7a 1551 return ~0UL;
0836a0eb
DM		 1552}
1553
517af332
DM		 1554static void __init tsb_phys_patch(void)
1555{
d257d5da 1556 struct tsb_ldquad_phys_patch_entry *pquad;
517af332
DM		 1557 struct tsb_phys_patch_entry *p;
1558
d257d5da
DM		 1559 pquad = &__tsb_ldquad_phys_patch;
1560 while (pquad < &__tsb_ldquad_phys_patch_end) {
1561 unsigned long addr = pquad->addr;
1562
1563 if (tlb_type == hypervisor)
1564 *(unsigned int *) addr = pquad->sun4v_insn;
1565 else
1566 *(unsigned int *) addr = pquad->sun4u_insn;
1567 wmb();
1568 __asm__ __volatile__("flush %0"
1569 : /* no outputs */
1570 : "r" (addr));
1571
1572 pquad++;
1573 }
1574
517af332
DM		 1575 p = &__tsb_phys_patch;
1576 while (p < &__tsb_phys_patch_end) {
1577 unsigned long addr = p->addr;
1578
1579 *(unsigned int *) addr = p->insn;
1580 wmb();
1581 __asm__ __volatile__("flush %0"
1582 : /* no outputs */
1583 : "r" (addr));
1584
1585 p++;
1586 }
1587}
1588
490384e7 1589/* Don't mark as init, we give this to the Hypervisor. */
d1acb421
DM		 1590#ifndef CONFIG_DEBUG_PAGEALLOC
1591#define NUM_KTSB_DESCR 2
1592#else
1593#define NUM_KTSB_DESCR 1
1594#endif
1595static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
490384e7
DM		 1596extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1597
9076d0e7
DM		 1598static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
1599{
1600 pa >>= KTSB_PHYS_SHIFT;
1601
1602 while (start < end) {
1603 unsigned int *ia = (unsigned int *)(unsigned long)*start;
1604
1605 ia[0] = (ia[0] & ~0x3fffff) | (pa >> 10);
1606 __asm__ __volatile__("flush %0" : : "r" (ia));
1607
1608 ia[1] = (ia[1] & ~0x3ff) | (pa & 0x3ff);
1609 __asm__ __volatile__("flush %0" : : "r" (ia + 1));
1610
1611 start++;
1612 }
1613}
1614
1615static void ktsb_phys_patch(void)
1616{
1617 extern unsigned int __swapper_tsb_phys_patch;
1618 extern unsigned int __swapper_tsb_phys_patch_end;
9076d0e7
DM		 1619 unsigned long ktsb_pa;
1620
1621 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1622 patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
1623 &__swapper_tsb_phys_patch_end, ktsb_pa);
1624#ifndef CONFIG_DEBUG_PAGEALLOC
0785a8e8
DM		 1625 {
1626 extern unsigned int __swapper_4m_tsb_phys_patch;
1627 extern unsigned int __swapper_4m_tsb_phys_patch_end;
9076d0e7
DM		 1628 ktsb_pa = (kern_base +
1629 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1630 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
1631 &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
0785a8e8 1632 }
9076d0e7
DM		 1633#endif
1634}
1635
490384e7
DM		 1636static void __init sun4v_ktsb_init(void)
1637{
1638 unsigned long ktsb_pa;
1639
d7744a09 1640 /* First KTSB for PAGE_SIZE mappings. */
490384e7
DM		 1641 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1642
1643 switch (PAGE_SIZE) {
1644 case 8 * 1024:
1645 default:
1646 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1647 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1648 break;
1649
1650 case 64 * 1024:
1651 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1652 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1653 break;
1654
1655 case 512 * 1024:
1656 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1657 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1658 break;
1659
1660 case 4 * 1024 * 1024:
1661 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1662 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1663 break;
6cb79b3f 1664 }
490384e7 1665
3f19a84e 1666 ktsb_descr[0].assoc = 1;
490384e7
DM		 1667 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1668 ktsb_descr[0].ctx_idx = 0;
1669 ktsb_descr[0].tsb_base = ktsb_pa;
1670 ktsb_descr[0].resv = 0;
1671
d1acb421 1672#ifndef CONFIG_DEBUG_PAGEALLOC
4f93d21d 1673 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
d7744a09
DM		 1674 ktsb_pa = (kern_base +
1675 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1676
1677 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
c69ad0a3
DM		 1678 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
1679 HV_PGSZ_MASK_256MB |
1680 HV_PGSZ_MASK_2GB |
1681 HV_PGSZ_MASK_16GB) &
1682 cpu_pgsz_mask);
d7744a09
DM		 1683 ktsb_descr[1].assoc = 1;
1684 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1685 ktsb_descr[1].ctx_idx = 0;
1686 ktsb_descr[1].tsb_base = ktsb_pa;
1687 ktsb_descr[1].resv = 0;
d1acb421 1688#endif
490384e7
DM		 1689}
1690
1691void __cpuinit sun4v_ktsb_register(void)
1692{
7db35f31 1693 unsigned long pa, ret;
490384e7
DM		 1694
1695 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1696
7db35f31
DM		 1697 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1698 if (ret != 0) {
1699 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1700 "errors with %lx\n", pa, ret);
1701 prom_halt();
1702 }
490384e7
DM		 1703}
1704
c69ad0a3
DM		 1705static void __init sun4u_linear_pte_xor_finalize(void)
1706{
1707#ifndef CONFIG_DEBUG_PAGEALLOC
1708 /* This is where we would add Panther support for
1709 * 32MB and 256MB pages.
1710 */
1711#endif
1712}
1713
1714static void __init sun4v_linear_pte_xor_finalize(void)
1715{
1716#ifndef CONFIG_DEBUG_PAGEALLOC
1717 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
1718 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1719 0xfffff80000000000UL;
1720 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1721 _PAGE_P_4V | _PAGE_W_4V);
1722 } else {
1723 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1724 }
1725
1726 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
1727 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
1728 0xfffff80000000000UL;
1729 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1730 _PAGE_P_4V | _PAGE_W_4V);
1731 } else {
1732 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
1733 }
1734
1735 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
1736 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
1737 0xfffff80000000000UL;
1738 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1739 _PAGE_P_4V | _PAGE_W_4V);
1740 } else {
1741 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
1742 }
1743#endif
1744}
1745
1da177e4
LT		 1746/* paging_init() sets up the page tables */
1747
1da177e4 1748static unsigned long last_valid_pfn;
56425306 1749pgd_t swapper_pg_dir[2048];
1da177e4 1750
c4bce90e
DM		 1751static void sun4u_pgprot_init(void);
1752static void sun4v_pgprot_init(void);
1753
1da177e4
LT		 1754void __init paging_init(void)
1755{
919ee677 1756 unsigned long end_pfn, shift, phys_base;
0836a0eb 1757 unsigned long real_end, i;
aa6f0790 1758 int node;
0836a0eb 1759
22adb358
DM		 1760 /* These build time checkes make sure that the dcache_dirty_cpu()
1761 * page->flags usage will work.
1762 *
1763 * When a page gets marked as dcache-dirty, we store the
1764 * cpu number starting at bit 32 in the page->flags. Also,
1765 * functions like clear_dcache_dirty_cpu use the cpu mask
1766 * in 13-bit signed-immediate instruction fields.
1767 */
9223b419
CL		 1768
1769 /*
1770 * Page flags must not reach into upper 32 bits that are used
1771 * for the cpu number
1772 */
1773 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1774
1775 /*
1776 * The bit fields placed in the high range must not reach below
1777 * the 32 bit boundary. Otherwise we cannot place the cpu field
1778 * at the 32 bit boundary.
1779 */
22adb358 1780 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
9223b419
CL		 1781 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1782
22adb358
DM		 1783 BUILD_BUG_ON(NR_CPUS > 4096);
1784
481295f9
DM		 1785 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1786 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1787
d7744a09 1788 /* Invalidate both kernel TSBs. */
8b234274 1789 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
d1acb421 1790#ifndef CONFIG_DEBUG_PAGEALLOC
d7744a09 1791 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
d1acb421 1792#endif
8b234274 1793
c4bce90e
DM		 1794 if (tlb_type == hypervisor)
1795 sun4v_pgprot_init();
1796 else
1797 sun4u_pgprot_init();
1798
d257d5da 1799 if (tlb_type == cheetah_plus ||
9076d0e7 1800 tlb_type == hypervisor) {
517af332 1801 tsb_phys_patch();
9076d0e7
DM		 1802 ktsb_phys_patch();
1803 }
517af332 1804
c69ad0a3 1805 if (tlb_type == hypervisor)
d257d5da
DM		 1806 sun4v_patch_tlb_handlers();
1807
a94a172d
DM		 1808 /* Find available physical memory...
1809 *
1810 * Read it twice in order to work around a bug in openfirmware.
1811 * The call to grab this table itself can cause openfirmware to
1812 * allocate memory, which in turn can take away some space from
1813 * the list of available memory. Reading it twice makes sure
1814 * we really do get the final value.
1815 */
1816 read_obp_translations();
1817 read_obp_memory("reg", &pall[0], &pall_ents);
1818 read_obp_memory("available", &pavail[0], &pavail_ents);
13edad7a 1819 read_obp_memory("available", &pavail[0], &pavail_ents);
0836a0eb
DM		 1820
1821 phys_base = 0xffffffffffffffffUL;
3b2a7e23 1822 for (i = 0; i < pavail_ents; i++) {
13edad7a 1823 phys_base = min(phys_base, pavail[i].phys_addr);
95f72d1e 1824 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
3b2a7e23
DM		 1825 }
1826
95f72d1e 1827 memblock_reserve(kern_base, kern_size);
0836a0eb 1828
4e82c9a6
DM		 1829 find_ramdisk(phys_base);
1830
95f72d1e 1831 memblock_enforce_memory_limit(cmdline_memory_size);
25b0c659 1832
1aadc056 1833 memblock_allow_resize();
95f72d1e 1834 memblock_dump_all();
3b2a7e23 1835
1da177e4
LT		 1836 set_bit(0, mmu_context_bmap);
1837
2bdb3cb2
DM		 1838 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1839
1da177e4 1840 real_end = (unsigned long)_end;
64658743
DM		 1841 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1842 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1843 num_kernel_image_mappings);
2bdb3cb2
DM		 1844
1845 /* Set kernel pgd to upper alias so physical page computations
1da177e4
LT		 1846 * work.
1847 */
1848 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1849
56425306 1850 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1da177e4
LT		 1851
1852 /* Now can init the kernel/bad page tables. */
1853 pud_set(pud_offset(&swapper_pg_dir[0], 0),
56425306 1854 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1da177e4 1855
c9c10830 1856 inherit_prom_mappings();
5085b4a5 1857
8f361453
DM		 1858 init_kpte_bitmap();
1859
a8b900d8
DM		 1860 /* Ok, we can use our TLB miss and window trap handlers safely. */
1861 setup_tba();
1da177e4 1862
c9c10830 1863 __flush_tlb_all();
9ad98c5b 1864
ad072004 1865 prom_build_devicetree();
b696fdc2 1866 of_populate_present_mask();
b99c6ebe
DM		 1867#ifndef CONFIG_SMP
1868 of_fill_in_cpu_data();
1869#endif
ad072004 1870
890db403 1871 if (tlb_type == hypervisor) {
4a283339 1872 sun4v_mdesc_init();
6ac5c610 1873 mdesc_populate_present_mask(cpu_all_mask);
b99c6ebe
DM		 1874#ifndef CONFIG_SMP
1875 mdesc_fill_in_cpu_data(cpu_all_mask);
1876#endif
ce33fdc5 1877 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
c69ad0a3
DM		 1878
1879 sun4v_linear_pte_xor_finalize();
1880
1881 sun4v_ktsb_init();
1882 sun4v_ktsb_register();
ce33fdc5
DM		 1883 } else {
1884 unsigned long impl, ver;
1885
1886 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
1887 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
1888
1889 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
1890 impl = ((ver >> 32) & 0xffff);
1891 if (impl == PANTHER_IMPL)
1892 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
1893 HV_PGSZ_MASK_256MB);
c69ad0a3
DM		 1894
1895 sun4u_linear_pte_xor_finalize();
890db403 1896 }
4a283339 1897
c69ad0a3
DM		 1898 /* Flush the TLBs and the 4M TSB so that the updated linear
1899 * pte XOR settings are realized for all mappings.
1900 */
1901 __flush_tlb_all();
1902#ifndef CONFIG_DEBUG_PAGEALLOC
1903 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1904#endif
1905 __flush_tlb_all();
1906
5ed56f1a
DM		 1907 /* Setup bootmem... */
1908 last_valid_pfn = end_pfn = bootmem_init(phys_base);
1909
4f70f7a9
DM		 1910 /* Once the OF device tree and MDESC have been setup, we know
1911 * the list of possible cpus. Therefore we can allocate the
1912 * IRQ stacks.
1913 */
1914 for_each_possible_cpu(i) {
aa6f0790 1915 node = cpu_to_node(i);
5ed56f1a
DM		 1916
1917 softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
1918 THREAD_SIZE,
1919 THREAD_SIZE, 0);
1920 hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
1921 THREAD_SIZE,
1922 THREAD_SIZE, 0);
4f70f7a9
DM		 1923 }
1924
56425306 1925 kernel_physical_mapping_init();
56425306 1926
1da177e4 1927 {
919ee677 1928 unsigned long max_zone_pfns[MAX_NR_ZONES];
1da177e4 1929
919ee677 1930 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1da177e4 1931
919ee677 1932 max_zone_pfns[ZONE_NORMAL] = end_pfn;
1da177e4 1933
919ee677 1934 free_area_init_nodes(max_zone_pfns);
1da177e4
LT		 1935 }
1936
3c62a2d3 1937 printk("Booting Linux...\n");
1da177e4
LT		 1938}
1939
7c9503b8 1940int page_in_phys_avail(unsigned long paddr)
919ee677
DM		 1941{
1942 int i;
1943
1944 paddr &= PAGE_MASK;
1945
1946 for (i = 0; i < pavail_ents; i++) {
1947 unsigned long start, end;
1948
1949 start = pavail[i].phys_addr;
1950 end = start + pavail[i].reg_size;
1951
1952 if (paddr >= start && paddr < end)
1953 return 1;
1954 }
1955 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1956 return 1;
1957#ifdef CONFIG_BLK_DEV_INITRD
1958 if (paddr >= __pa(initrd_start) &&
1959 paddr < __pa(PAGE_ALIGN(initrd_end)))
1960 return 1;
1961#endif
1962
1963 return 0;
1964}
1965
1966static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
1967static int pavail_rescan_ents __initdata;
1968
1969/* Certain OBP calls, such as fetching "available" properties, can
1970 * claim physical memory. So, along with initializing the valid
1971 * address bitmap, what we do here is refetch the physical available
1972 * memory list again, and make sure it provides at least as much
1973 * memory as 'pavail' does.
1974 */
d8ed1d43 1975static void __init setup_valid_addr_bitmap_from_pavail(unsigned long *bitmap)
1da177e4 1976{
1da177e4
LT		 1977 int i;
1978
13edad7a 1979 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1da177e4 1980
13edad7a 1981 for (i = 0; i < pavail_ents; i++) {
1da177e4
LT		 1982 unsigned long old_start, old_end;
1983
13edad7a 1984 old_start = pavail[i].phys_addr;
919ee677 1985 old_end = old_start + pavail[i].reg_size;
1da177e4
LT		 1986 while (old_start < old_end) {
1987 int n;
1988
c2a5a46b 1989 for (n = 0; n < pavail_rescan_ents; n++) {
1da177e4
LT		 1990 unsigned long new_start, new_end;
1991
13edad7a
DM		 1992 new_start = pavail_rescan[n].phys_addr;
1993 new_end = new_start +
1994 pavail_rescan[n].reg_size;
1da177e4
LT		 1995
1996 if (new_start <= old_start &&
1997 new_end >= (old_start + PAGE_SIZE)) {
d8ed1d43 1998 set_bit(old_start >> 22, bitmap);
1da177e4
LT		 1999 goto do_next_page;
2000 }
2001 }
919ee677
DM		 2002
2003 prom_printf("mem_init: Lost memory in pavail\n");
2004 prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
2005 pavail[i].phys_addr,
2006 pavail[i].reg_size);
2007 prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
2008 pavail_rescan[i].phys_addr,
2009 pavail_rescan[i].reg_size);
2010 prom_printf("mem_init: Cannot continue, aborting.\n");
2011 prom_halt();
1da177e4
LT		 2012
2013 do_next_page:
2014 old_start += PAGE_SIZE;
2015 }
2016 }
2017}
2018
d8ed1d43
DM		 2019static void __init patch_tlb_miss_handler_bitmap(void)
2020{
2021 extern unsigned int valid_addr_bitmap_insn[];
2022 extern unsigned int valid_addr_bitmap_patch[];
2023
2024 valid_addr_bitmap_insn[1] = valid_addr_bitmap_patch[1];
2025 mb();
2026 valid_addr_bitmap_insn[0] = valid_addr_bitmap_patch[0];
2027 flushi(&valid_addr_bitmap_insn[0]);
2028}
2029
961f8fa0
YL		 2030static void __init register_page_bootmem_info(void)
2031{
2032#ifdef CONFIG_NEED_MULTIPLE_NODES
2033 int i;
2034
2035 for_each_online_node(i)
2036 if (NODE_DATA(i)->node_spanned_pages)
2037 register_page_bootmem_info_node(NODE_DATA(i));
2038#endif
2039}
1da177e4
LT		 2040void __init mem_init(void)
2041{
2042 unsigned long codepages, datapages, initpages;
2043 unsigned long addr, last;
1da177e4
LT		 2044
2045 addr = PAGE_OFFSET + kern_base;
2046 last = PAGE_ALIGN(kern_size) + addr;
2047 while (addr < last) {
2048 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
2049 addr += PAGE_SIZE;
2050 }
2051
d8ed1d43
DM		 2052 setup_valid_addr_bitmap_from_pavail(sparc64_valid_addr_bitmap);
2053 patch_tlb_miss_handler_bitmap();
1da177e4 2054
1da177e4
LT		 2055 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2056
961f8fa0 2057 register_page_bootmem_info();
919ee677 2058 totalram_pages = free_all_bootmem();
919ee677 2059
f1cfdb55
DM		 2060 /* We subtract one to account for the mem_map_zero page
2061 * allocated below.
2062 */
919ee677
DM		 2063 totalram_pages -= 1;
2064 num_physpages = totalram_pages;
1da177e4
LT		 2065
2066 /*
2067 * Set up the zero page, mark it reserved, so that page count
2068 * is not manipulated when freeing the page from user ptes.
2069 */
2070 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2071 if (mem_map_zero == NULL) {
2072 prom_printf("paging_init: Cannot alloc zero page.\n");
2073 prom_halt();
2074 }
2075 SetPageReserved(mem_map_zero);
2076
2077 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
2078 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
2079 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
2080 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
2081 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
2082 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
2083
96177299 2084 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1da177e4
LT		 2085 nr_free_pages() << (PAGE_SHIFT-10),
2086 codepages << (PAGE_SHIFT-10),
2087 datapages << (PAGE_SHIFT-10),
2088 initpages << (PAGE_SHIFT-10),
2089 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
2090
2091 if (tlb_type == cheetah || tlb_type == cheetah_plus)
2092 cheetah_ecache_flush_init();
2093}
2094
898cf0ec 2095void free_initmem(void)
1da177e4
LT		 2096{
2097 unsigned long addr, initend;
f2b60794
DM		 2098 int do_free = 1;
2099
2100 /* If the physical memory maps were trimmed by kernel command
2101 * line options, don't even try freeing this initmem stuff up.
2102 * The kernel image could have been in the trimmed out region
2103 * and if so the freeing below will free invalid page structs.
2104 */
2105 if (cmdline_memory_size)
2106 do_free = 0;
1da177e4
LT		 2107
2108 /*
2109 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2110 */
2111 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2112 initend = (unsigned long)(__init_end) & PAGE_MASK;
2113 for (; addr < initend; addr += PAGE_SIZE) {
2114 unsigned long page;
2115 struct page *p;
2116
2117 page = (addr +
2118 ((unsigned long) __va(kern_base)) -
2119 ((unsigned long) KERNBASE));
c9cf5528 2120 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
1da177e4 2121
f2b60794
DM		 2122 if (do_free) {
2123 p = virt_to_page(page);
2124
2125 ClearPageReserved(p);
2126 init_page_count(p);
2127 __free_page(p);
2128 num_physpages++;
2129 totalram_pages++;
2130 }
1da177e4
LT		 2131 }
2132}
2133
2134#ifdef CONFIG_BLK_DEV_INITRD
2135void free_initrd_mem(unsigned long start, unsigned long end)
2136{
2137 if (start < end)
2138 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
2139 for (; start < end; start += PAGE_SIZE) {
2140 struct page *p = virt_to_page(start);
2141
2142 ClearPageReserved(p);
7835e98b 2143 init_page_count(p);
1da177e4
LT		 2144 __free_page(p);
2145 num_physpages++;
2146 totalram_pages++;
2147 }
2148}
2149#endif
c4bce90e 2150
c4bce90e
DM		 2151#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2152#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2153#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2154#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2155#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2156#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2157
2158pgprot_t PAGE_KERNEL __read_mostly;
2159EXPORT_SYMBOL(PAGE_KERNEL);
2160
2161pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2162pgprot_t PAGE_COPY __read_mostly;
0f15952a
DM		 2163
2164pgprot_t PAGE_SHARED __read_mostly;
2165EXPORT_SYMBOL(PAGE_SHARED);
2166
c4bce90e
DM		 2167unsigned long pg_iobits __read_mostly;
2168
2169unsigned long _PAGE_IE __read_mostly;
987c74fc 2170EXPORT_SYMBOL(_PAGE_IE);
b2bef442 2171
c4bce90e 2172unsigned long _PAGE_E __read_mostly;
b2bef442
DM		 2173EXPORT_SYMBOL(_PAGE_E);
2174
c4bce90e 2175unsigned long _PAGE_CACHE __read_mostly;
b2bef442 2176EXPORT_SYMBOL(_PAGE_CACHE);
c4bce90e 2177
46644c24 2178#ifdef CONFIG_SPARSEMEM_VMEMMAP
46644c24
DM		 2179unsigned long vmemmap_table[VMEMMAP_SIZE];
2180
2856cc2e
DM		 2181static long __meminitdata addr_start, addr_end;
2182static int __meminitdata node_start;
2183
0aad818b
JW		 2184int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2185 int node)
46644c24 2186{
46644c24
DM		 2187 unsigned long phys_start = (vstart - VMEMMAP_BASE);
2188 unsigned long phys_end = (vend - VMEMMAP_BASE);
2189 unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
2190 unsigned long end = VMEMMAP_ALIGN(phys_end);
2191 unsigned long pte_base;
2192
2193 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2194 _PAGE_CP_4U | _PAGE_CV_4U |
2195 _PAGE_P_4U | _PAGE_W_4U);
2196 if (tlb_type == hypervisor)
2197 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2198 _PAGE_CP_4V | _PAGE_CV_4V |
2199 _PAGE_P_4V | _PAGE_W_4V);
2200
2201 for (; addr < end; addr += VMEMMAP_CHUNK) {
2202 unsigned long *vmem_pp =
2203 vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
2204 void *block;
2205
2206 if (!(*vmem_pp & _PAGE_VALID)) {
2207 block = vmemmap_alloc_block(1UL << 22, node);
2208 if (!block)
2209 return -ENOMEM;
2210
2211 *vmem_pp = pte_base | __pa(block);
2212
2856cc2e
DM		 2213 /* check to see if we have contiguous blocks */
2214 if (addr_end != addr || node_start != node) {
2215 if (addr_start)
2216 printk(KERN_DEBUG " [%lx-%lx] on node %d\n",
2217 addr_start, addr_end-1, node_start);
2218 addr_start = addr;
2219 node_start = node;
2220 }
2221 addr_end = addr + VMEMMAP_CHUNK;
46644c24
DM		 2222 }
2223 }
2224 return 0;
2225}
2856cc2e
DM		 2226
2227void __meminit vmemmap_populate_print_last(void)
2228{
2229 if (addr_start) {
2230 printk(KERN_DEBUG " [%lx-%lx] on node %d\n",
2231 addr_start, addr_end-1, node_start);
2232 addr_start = 0;
2233 addr_end = 0;
2234 node_start = 0;
2235 }
2236}
46723bfa 2237
0aad818b 2238void vmemmap_free(unsigned long start, unsigned long end)
0197518c
TC		 2239{
2240}
2241
46644c24
DM		 2242#endif /* CONFIG_SPARSEMEM_VMEMMAP */
2243
c4bce90e
DM		 2244static void prot_init_common(unsigned long page_none,
2245 unsigned long page_shared,
2246 unsigned long page_copy,
2247 unsigned long page_readonly,
2248 unsigned long page_exec_bit)
2249{
2250 PAGE_COPY = __pgprot(page_copy);
0f15952a 2251 PAGE_SHARED = __pgprot(page_shared);
c4bce90e
DM		 2252
2253 protection_map[0x0] = __pgprot(page_none);
2254 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2255 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2256 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2257 protection_map[0x4] = __pgprot(page_readonly);
2258 protection_map[0x5] = __pgprot(page_readonly);
2259 protection_map[0x6] = __pgprot(page_copy);
2260 protection_map[0x7] = __pgprot(page_copy);
2261 protection_map[0x8] = __pgprot(page_none);
2262 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2263 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2264 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2265 protection_map[0xc] = __pgprot(page_readonly);
2266 protection_map[0xd] = __pgprot(page_readonly);
2267 protection_map[0xe] = __pgprot(page_shared);
2268 protection_map[0xf] = __pgprot(page_shared);
2269}
2270
2271static void __init sun4u_pgprot_init(void)
2272{
2273 unsigned long page_none, page_shared, page_copy, page_readonly;
2274 unsigned long page_exec_bit;
4f93d21d 2275 int i;
c4bce90e
DM		 2276
2277 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2278 _PAGE_CACHE_4U | _PAGE_P_4U |
2279 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2280 _PAGE_EXEC_4U);
2281 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2282 _PAGE_CACHE_4U | _PAGE_P_4U |
2283 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2284 _PAGE_EXEC_4U | _PAGE_L_4U);
c4bce90e
DM		 2285
2286 _PAGE_IE = _PAGE_IE_4U;
2287 _PAGE_E = _PAGE_E_4U;
2288 _PAGE_CACHE = _PAGE_CACHE_4U;
2289
2290 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2291 __ACCESS_BITS_4U | _PAGE_E_4U);
2292
d1acb421 2293#ifdef CONFIG_DEBUG_PAGEALLOC
15b9350a 2294 kern_linear_pte_xor[0] = _PAGE_VALID ^ 0xfffff80000000000UL;
d1acb421 2295#else
9cc3a1ac 2296 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
af1ee569 2297 0xfffff80000000000UL;
d1acb421 2298#endif
9cc3a1ac
DM		 2299 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2300 _PAGE_P_4U | _PAGE_W_4U);
2301
4f93d21d
DM		 2302 for (i = 1; i < 4; i++)
2303 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
c4bce90e 2304
c4bce90e
DM		 2305 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2306 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2307 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2308
2309
2310 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2311 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2312 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2313 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2314 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2315 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2316 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2317
2318 page_exec_bit = _PAGE_EXEC_4U;
2319
2320 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2321 page_exec_bit);
2322}
2323
2324static void __init sun4v_pgprot_init(void)
2325{
2326 unsigned long page_none, page_shared, page_copy, page_readonly;
2327 unsigned long page_exec_bit;
4f93d21d 2328 int i;
c4bce90e
DM		 2329
2330 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2331 _PAGE_CACHE_4V | _PAGE_P_4V |
2332 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2333 _PAGE_EXEC_4V);
2334 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
c4bce90e
DM		 2335
2336 _PAGE_IE = _PAGE_IE_4V;
2337 _PAGE_E = _PAGE_E_4V;
2338 _PAGE_CACHE = _PAGE_CACHE_4V;
2339
d1acb421 2340#ifdef CONFIG_DEBUG_PAGEALLOC
15b9350a 2341 kern_linear_pte_xor[0] = _PAGE_VALID ^ 0xfffff80000000000UL;
d1acb421 2342#else
9cc3a1ac 2343 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
af1ee569 2344 0xfffff80000000000UL;
d1acb421 2345#endif
9cc3a1ac
DM		 2346 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2347 _PAGE_P_4V | _PAGE_W_4V);
2348
c69ad0a3
DM		 2349 for (i = 1; i < 4; i++)
2350 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
4f93d21d 2351
c4bce90e
DM		 2352 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2353 __ACCESS_BITS_4V | _PAGE_E_4V);
2354
c4bce90e
DM		 2355 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2356 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2357 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2358 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2359
2360 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2361 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2362 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2363 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2364 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2365 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2366 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2367
2368 page_exec_bit = _PAGE_EXEC_4V;
2369
2370 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2371 page_exec_bit);
2372}
2373
2374unsigned long pte_sz_bits(unsigned long sz)
2375{
2376 if (tlb_type == hypervisor) {
2377 switch (sz) {
2378 case 8 * 1024:
2379 default:
2380 return _PAGE_SZ8K_4V;
2381 case 64 * 1024:
2382 return _PAGE_SZ64K_4V;
2383 case 512 * 1024:
2384 return _PAGE_SZ512K_4V;
2385 case 4 * 1024 * 1024:
2386 return _PAGE_SZ4MB_4V;
6cb79b3f 2387 }
c4bce90e
DM		 2388 } else {
2389 switch (sz) {
2390 case 8 * 1024:
2391 default:
2392 return _PAGE_SZ8K_4U;
2393 case 64 * 1024:
2394 return _PAGE_SZ64K_4U;
2395 case 512 * 1024:
2396 return _PAGE_SZ512K_4U;
2397 case 4 * 1024 * 1024:
2398 return _PAGE_SZ4MB_4U;
6cb79b3f 2399 }
c4bce90e
DM		 2400 }
2401}
2402
2403pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2404{
2405 pte_t pte;
cf627156
DM		 2406
2407 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
c4bce90e
DM		 2408 pte_val(pte) |= (((unsigned long)space) << 32);
2409 pte_val(pte) |= pte_sz_bits(page_size);
c4bce90e 2410
cf627156 2411 return pte;
c4bce90e
DM		 2412}
2413
2414static unsigned long kern_large_tte(unsigned long paddr)
2415{
2416 unsigned long val;
2417
2418 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2419 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2420 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2421 if (tlb_type == hypervisor)
2422 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2423 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2424 _PAGE_EXEC_4V | _PAGE_W_4V);
2425
2426 return val | paddr;
2427}
2428
c4bce90e
DM		 2429/* If not locked, zap it. */
2430void __flush_tlb_all(void)
2431{
2432 unsigned long pstate;
2433 int i;
2434
2435 __asm__ __volatile__("flushw\n\t"
2436 "rdpr %%pstate, %0\n\t"
2437 "wrpr %0, %1, %%pstate"
2438 : "=r" (pstate)
2439 : "i" (PSTATE_IE));
8f361453
DM		 2440 if (tlb_type == hypervisor) {
2441 sun4v_mmu_demap_all();
2442 } else if (tlb_type == spitfire) {
c4bce90e
DM		 2443 for (i = 0; i < 64; i++) {
2444 /* Spitfire Errata #32 workaround */
2445 /* NOTE: Always runs on spitfire, so no
2446 * cheetah+ page size encodings.
2447 */
2448 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2449 "flush %%g6"
2450 : /* No outputs */
2451 : "r" (0),
2452 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2453
2454 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2455 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2456 "membar #Sync"
2457 : /* no outputs */
2458 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2459 spitfire_put_dtlb_data(i, 0x0UL);
2460 }
2461
2462 /* Spitfire Errata #32 workaround */
2463 /* NOTE: Always runs on spitfire, so no
2464 * cheetah+ page size encodings.
2465 */
2466 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2467 "flush %%g6"
2468 : /* No outputs */
2469 : "r" (0),
2470 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2471
2472 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2473 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2474 "membar #Sync"
2475 : /* no outputs */
2476 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2477 spitfire_put_itlb_data(i, 0x0UL);
2478 }
2479 }
2480 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2481 cheetah_flush_dtlb_all();
2482 cheetah_flush_itlb_all();
2483 }
2484 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2485 : : "r" (pstate));
2486}
c460bec7
DM		 2487
2488static pte_t *get_from_cache(struct mm_struct *mm)
2489{
2490 struct page *page;
2491 pte_t *ret;
2492
2493 spin_lock(&mm->page_table_lock);
2494 page = mm->context.pgtable_page;
2495 ret = NULL;
2496 if (page) {
2497 void *p = page_address(page);
2498
2499 mm->context.pgtable_page = NULL;
2500
2501 ret = (pte_t *) (p + (PAGE_SIZE / 2));
2502 }
2503 spin_unlock(&mm->page_table_lock);
2504
2505 return ret;
2506}
2507
2508static struct page *__alloc_for_cache(struct mm_struct *mm)
2509{
2510 struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2511 __GFP_REPEAT | __GFP_ZERO);
2512
2513 if (page) {
2514 spin_lock(&mm->page_table_lock);
2515 if (!mm->context.pgtable_page) {
2516 atomic_set(&page->_count, 2);
2517 mm->context.pgtable_page = page;
2518 }
2519 spin_unlock(&mm->page_table_lock);
2520 }
2521 return page;
2522}
2523
2524pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
2525 unsigned long address)
2526{
2527 struct page *page;
2528 pte_t *pte;
2529
2530 pte = get_from_cache(mm);
2531 if (pte)
2532 return pte;
2533
2534 page = __alloc_for_cache(mm);
2535 if (page)
2536 pte = (pte_t *) page_address(page);
2537
2538 return pte;
2539}
2540
2541pgtable_t pte_alloc_one(struct mm_struct *mm,
2542 unsigned long address)
2543{
2544 struct page *page;
2545 pte_t *pte;
2546
2547 pte = get_from_cache(mm);
2548 if (pte)
2549 return pte;
2550
2551 page = __alloc_for_cache(mm);
2552 if (page) {
2553 pgtable_page_ctor(page);
2554 pte = (pte_t *) page_address(page);
2555 }
2556
2557 return pte;
2558}
2559
2560void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2561{
2562 struct page *page = virt_to_page(pte);
2563 if (put_page_testzero(page))
2564 free_hot_cold_page(page, 0);
2565}
2566
2567static void __pte_free(pgtable_t pte)
2568{
2569 struct page *page = virt_to_page(pte);
2570 if (put_page_testzero(page)) {
2571 pgtable_page_dtor(page);
2572 free_hot_cold_page(page, 0);
2573 }
2574}
2575
2576void pte_free(struct mm_struct *mm, pgtable_t pte)
2577{
2578 __pte_free(pte);
2579}
2580
2581void pgtable_free(void *table, bool is_page)
2582{
2583 if (is_page)
2584 __pte_free(table);
2585 else
2586 kmem_cache_free(pgtable_cache, table);
2587}
9e695d2e
DM		 2588
2589#ifdef CONFIG_TRANSPARENT_HUGEPAGE
2590static pmd_t pmd_set_protbits(pmd_t pmd, pgprot_t pgprot, bool for_modify)
2591{
2592 if (pgprot_val(pgprot) & _PAGE_VALID)
2593 pmd_val(pmd) |= PMD_HUGE_PRESENT;
2594 if (tlb_type == hypervisor) {
2595 if (pgprot_val(pgprot) & _PAGE_WRITE_4V)
2596 pmd_val(pmd) |= PMD_HUGE_WRITE;
2597 if (pgprot_val(pgprot) & _PAGE_EXEC_4V)
2598 pmd_val(pmd) |= PMD_HUGE_EXEC;
2599
2600 if (!for_modify) {
2601 if (pgprot_val(pgprot) & _PAGE_ACCESSED_4V)
2602 pmd_val(pmd) |= PMD_HUGE_ACCESSED;
2603 if (pgprot_val(pgprot) & _PAGE_MODIFIED_4V)
2604 pmd_val(pmd) |= PMD_HUGE_DIRTY;
2605 }
2606 } else {
2607 if (pgprot_val(pgprot) & _PAGE_WRITE_4U)
2608 pmd_val(pmd) |= PMD_HUGE_WRITE;
2609 if (pgprot_val(pgprot) & _PAGE_EXEC_4U)
2610 pmd_val(pmd) |= PMD_HUGE_EXEC;
2611
2612 if (!for_modify) {
2613 if (pgprot_val(pgprot) & _PAGE_ACCESSED_4U)
2614 pmd_val(pmd) |= PMD_HUGE_ACCESSED;
2615 if (pgprot_val(pgprot) & _PAGE_MODIFIED_4U)
2616 pmd_val(pmd) |= PMD_HUGE_DIRTY;
2617 }
2618 }
2619
2620 return pmd;
2621}
2622
2623pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
2624{
2625 pmd_t pmd;
2626
2627 pmd_val(pmd) = (page_nr << ((PAGE_SHIFT - PMD_PADDR_SHIFT)));
2628 pmd_val(pmd) |= PMD_ISHUGE;
2629 pmd = pmd_set_protbits(pmd, pgprot, false);
2630 return pmd;
2631}
2632
2633pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
2634{
2635 pmd_val(pmd) &= ~(PMD_HUGE_PRESENT |
2636 PMD_HUGE_WRITE |
2637 PMD_HUGE_EXEC);
2638 pmd = pmd_set_protbits(pmd, newprot, true);
2639 return pmd;
2640}
2641
2642pgprot_t pmd_pgprot(pmd_t entry)
2643{
2644 unsigned long pte = 0;
2645
2646 if (pmd_val(entry) & PMD_HUGE_PRESENT)
2647 pte |= _PAGE_VALID;
2648
2649 if (tlb_type == hypervisor) {
2650 if (pmd_val(entry) & PMD_HUGE_PRESENT)
2651 pte |= _PAGE_PRESENT_4V;
2652 if (pmd_val(entry) & PMD_HUGE_EXEC)
2653 pte |= _PAGE_EXEC_4V;
2654 if (pmd_val(entry) & PMD_HUGE_WRITE)
2655 pte |= _PAGE_W_4V;
2656 if (pmd_val(entry) & PMD_HUGE_ACCESSED)
2657 pte |= _PAGE_ACCESSED_4V;
2658 if (pmd_val(entry) & PMD_HUGE_DIRTY)
2659 pte |= _PAGE_MODIFIED_4V;
2660 pte |= _PAGE_CP_4V|_PAGE_CV_4V;
2661 } else {
2662 if (pmd_val(entry) & PMD_HUGE_PRESENT)
2663 pte |= _PAGE_PRESENT_4U;
2664 if (pmd_val(entry) & PMD_HUGE_EXEC)
2665 pte |= _PAGE_EXEC_4U;
2666 if (pmd_val(entry) & PMD_HUGE_WRITE)
2667 pte |= _PAGE_W_4U;
2668 if (pmd_val(entry) & PMD_HUGE_ACCESSED)
2669 pte |= _PAGE_ACCESSED_4U;
2670 if (pmd_val(entry) & PMD_HUGE_DIRTY)
2671 pte |= _PAGE_MODIFIED_4U;
2672 pte |= _PAGE_CP_4U|_PAGE_CV_4U;
2673 }
2674
2675 return __pgprot(pte);
2676}
2677
2678void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2679 pmd_t *pmd)
2680{
2681 unsigned long pte, flags;
2682 struct mm_struct *mm;
2683 pmd_t entry = *pmd;
2684 pgprot_t prot;
2685
2686 if (!pmd_large(entry) || !pmd_young(entry))
2687 return;
2688
2689 pte = (pmd_val(entry) & ~PMD_HUGE_PROTBITS);
2690 pte <<= PMD_PADDR_SHIFT;
2691 pte |= _PAGE_VALID;
2692
2693 prot = pmd_pgprot(entry);
2694
2695 if (tlb_type == hypervisor)
2696 pgprot_val(prot) |= _PAGE_SZHUGE_4V;
2697 else
2698 pgprot_val(prot) |= _PAGE_SZHUGE_4U;
2699
2700 pte |= pgprot_val(prot);
2701
2702 mm = vma->vm_mm;
2703
2704 spin_lock_irqsave(&mm->context.lock, flags);
2705
2706 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2707 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, HPAGE_SHIFT,
2708 addr, pte);
2709
2710 spin_unlock_irqrestore(&mm->context.lock, flags);
2711}
2712#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2713
2714#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2715static void context_reload(void *__data)
2716{
2717 struct mm_struct *mm = __data;
2718
2719 if (mm == current->mm)
2720 load_secondary_context(mm);
2721}
2722
0fbebed6 2723void hugetlb_setup(struct pt_regs *regs)
9e695d2e 2724{
0fbebed6
DM		 2725 struct mm_struct *mm = current->mm;
2726 struct tsb_config *tp;
9e695d2e 2727
0fbebed6
DM		 2728 if (in_atomic() || !mm) {
2729 const struct exception_table_entry *entry;
2730
2731 entry = search_exception_tables(regs->tpc);
2732 if (entry) {
2733 regs->tpc = entry->fixup;
2734 regs->tnpc = regs->tpc + 4;
2735 return;
2736 }
2737 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2738 die_if_kernel("HugeTSB in atomic", regs);
2739 }
2740
2741 tp = &mm->context.tsb_block[MM_TSB_HUGE];
2742 if (likely(tp->tsb == NULL))
2743 tsb_grow(mm, MM_TSB_HUGE, 0);
9e695d2e 2744
9e695d2e
DM		 2745 tsb_context_switch(mm);
2746 smp_tsb_sync(mm);
2747
2748 /* On UltraSPARC-III+ and later, configure the second half of
2749 * the Data-TLB for huge pages.
2750 */
2751 if (tlb_type == cheetah_plus) {
2752 unsigned long ctx;
2753
2754 spin_lock(&ctx_alloc_lock);
2755 ctx = mm->context.sparc64_ctx_val;
2756 ctx &= ~CTX_PGSZ_MASK;
2757 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
2758 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
2759
2760 if (ctx != mm->context.sparc64_ctx_val) {
2761 /* When changing the page size fields, we
2762 * must perform a context flush so that no
2763 * stale entries match. This flush must
2764 * occur with the original context register
2765 * settings.
2766 */
2767 do_flush_tlb_mm(mm);
2768
2769 /* Reload the context register of all processors
2770 * also executing in this address space.
2771 */
2772 mm->context.sparc64_ctx_val = ctx;
2773 on_each_cpu(context_reload, mm, 0);
2774 }
2775 spin_unlock(&ctx_alloc_lock);
2776 }
2777}
2778#endif
kernel source for telekom puls (alcatel/mediatek)