Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
8b646bd7 | 2 | * SMP related functions |
1da177e4 | 3 | * |
a53c8fab | 4 | * Copyright IBM Corp. 1999, 2012 |
8b646bd7 MS |
5 | * Author(s): Denis Joseph Barrow, |
6 | * Martin Schwidefsky <schwidefsky@de.ibm.com>, | |
7 | * Heiko Carstens <heiko.carstens@de.ibm.com>, | |
1da177e4 | 8 | * |
39ce010d | 9 | * based on other smp stuff by |
1da177e4 LT |
10 | * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net> |
11 | * (c) 1998 Ingo Molnar | |
12 | * | |
8b646bd7 MS |
13 | * The code outside of smp.c uses logical cpu numbers, only smp.c does |
14 | * the translation of logical to physical cpu ids. All new code that | |
15 | * operates on physical cpu numbers needs to go into smp.c. | |
1da177e4 LT |
16 | */ |
17 | ||
395d31d4 MS |
18 | #define KMSG_COMPONENT "cpu" |
19 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
20 | ||
f230886b | 21 | #include <linux/workqueue.h> |
1da177e4 LT |
22 | #include <linux/module.h> |
23 | #include <linux/init.h> | |
1da177e4 | 24 | #include <linux/mm.h> |
4e950f6f | 25 | #include <linux/err.h> |
1da177e4 LT |
26 | #include <linux/spinlock.h> |
27 | #include <linux/kernel_stat.h> | |
1da177e4 | 28 | #include <linux/delay.h> |
1da177e4 | 29 | #include <linux/interrupt.h> |
3324e60a | 30 | #include <linux/irqflags.h> |
1da177e4 | 31 | #include <linux/cpu.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
60a0c68d | 33 | #include <linux/crash_dump.h> |
cbb870c8 | 34 | #include <asm/asm-offsets.h> |
1e3cab2f HC |
35 | #include <asm/switch_to.h> |
36 | #include <asm/facility.h> | |
46b05d26 | 37 | #include <asm/ipl.h> |
2b67fc46 | 38 | #include <asm/setup.h> |
1da177e4 | 39 | #include <asm/irq.h> |
1da177e4 | 40 | #include <asm/tlbflush.h> |
27f6b416 | 41 | #include <asm/vtimer.h> |
411ed322 | 42 | #include <asm/lowcore.h> |
08d07968 | 43 | #include <asm/sclp.h> |
c742b31c | 44 | #include <asm/vdso.h> |
3ab121ab | 45 | #include <asm/debug.h> |
4857d4bb | 46 | #include <asm/os_info.h> |
a9ae32c3 | 47 | #include <asm/sigp.h> |
a806170e | 48 | #include "entry.h" |
1da177e4 | 49 | |
8b646bd7 MS |
50 | enum { |
51 | ec_schedule = 0, | |
52 | ec_call_function, | |
53 | ec_call_function_single, | |
54 | ec_stop_cpu, | |
55 | }; | |
08d07968 | 56 | |
8b646bd7 | 57 | enum { |
08d07968 HC |
58 | CPU_STATE_STANDBY, |
59 | CPU_STATE_CONFIGURED, | |
60 | }; | |
61 | ||
8b646bd7 MS |
62 | struct pcpu { |
63 | struct cpu cpu; | |
8b646bd7 MS |
64 | struct _lowcore *lowcore; /* lowcore page(s) for the cpu */ |
65 | unsigned long async_stack; /* async stack for the cpu */ | |
66 | unsigned long panic_stack; /* panic stack for the cpu */ | |
67 | unsigned long ec_mask; /* bit mask for ec_xxx functions */ | |
68 | int state; /* physical cpu state */ | |
50ab9a9a | 69 | int polarization; /* physical polarization */ |
8b646bd7 MS |
70 | u16 address; /* physical cpu address */ |
71 | }; | |
72 | ||
73 | static u8 boot_cpu_type; | |
74 | static u16 boot_cpu_address; | |
75 | static struct pcpu pcpu_devices[NR_CPUS]; | |
76 | ||
50ab9a9a HC |
77 | /* |
78 | * The smp_cpu_state_mutex must be held when changing the state or polarization | |
79 | * member of a pcpu data structure within the pcpu_devices arreay. | |
80 | */ | |
dbd70fb4 | 81 | DEFINE_MUTEX(smp_cpu_state_mutex); |
08d07968 | 82 | |
8b646bd7 MS |
83 | /* |
84 | * Signal processor helper functions. | |
85 | */ | |
86 | static inline int __pcpu_sigp(u16 addr, u8 order, u32 parm, u32 *status) | |
87 | { | |
88 | register unsigned int reg1 asm ("1") = parm; | |
89 | int cc; | |
08d07968 | 90 | |
8b646bd7 MS |
91 | asm volatile( |
92 | " sigp %1,%2,0(%3)\n" | |
93 | " ipm %0\n" | |
94 | " srl %0,28\n" | |
95 | : "=d" (cc), "+d" (reg1) : "d" (addr), "a" (order) : "cc"); | |
96 | if (status && cc == 1) | |
97 | *status = reg1; | |
98 | return cc; | |
99 | } | |
1da177e4 | 100 | |
8b646bd7 | 101 | static inline int __pcpu_sigp_relax(u16 addr, u8 order, u32 parm, u32 *status) |
5c0b912e | 102 | { |
8b646bd7 | 103 | int cc; |
5c0b912e | 104 | |
8b646bd7 | 105 | while (1) { |
c5e3acd6 | 106 | cc = __pcpu_sigp(addr, order, parm, NULL); |
a9ae32c3 | 107 | if (cc != SIGP_CC_BUSY) |
8b646bd7 MS |
108 | return cc; |
109 | cpu_relax(); | |
5c0b912e | 110 | } |
5c0b912e HC |
111 | } |
112 | ||
8b646bd7 | 113 | static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm) |
a93b8ec1 | 114 | { |
8b646bd7 MS |
115 | int cc, retry; |
116 | ||
117 | for (retry = 0; ; retry++) { | |
c5e3acd6 | 118 | cc = __pcpu_sigp(pcpu->address, order, parm, NULL); |
a9ae32c3 | 119 | if (cc != SIGP_CC_BUSY) |
8b646bd7 MS |
120 | break; |
121 | if (retry >= 3) | |
122 | udelay(10); | |
123 | } | |
124 | return cc; | |
125 | } | |
126 | ||
127 | static inline int pcpu_stopped(struct pcpu *pcpu) | |
128 | { | |
41459d36 | 129 | u32 uninitialized_var(status); |
c5e3acd6 | 130 | |
a9ae32c3 | 131 | if (__pcpu_sigp(pcpu->address, SIGP_SENSE, |
c5e3acd6 | 132 | 0, &status) != SIGP_CC_STATUS_STORED) |
8b646bd7 | 133 | return 0; |
c5e3acd6 | 134 | return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED)); |
8b646bd7 MS |
135 | } |
136 | ||
137 | static inline int pcpu_running(struct pcpu *pcpu) | |
a93b8ec1 | 138 | { |
a9ae32c3 | 139 | if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING, |
c5e3acd6 | 140 | 0, NULL) != SIGP_CC_STATUS_STORED) |
8b646bd7 | 141 | return 1; |
524b24ad HC |
142 | /* Status stored condition code is equivalent to cpu not running. */ |
143 | return 0; | |
a93b8ec1 HC |
144 | } |
145 | ||
1943f53c | 146 | /* |
8b646bd7 | 147 | * Find struct pcpu by cpu address. |
1943f53c | 148 | */ |
8b646bd7 | 149 | static struct pcpu *pcpu_find_address(const struct cpumask *mask, int address) |
1943f53c MH |
150 | { |
151 | int cpu; | |
152 | ||
8b646bd7 MS |
153 | for_each_cpu(cpu, mask) |
154 | if (pcpu_devices[cpu].address == address) | |
155 | return pcpu_devices + cpu; | |
156 | return NULL; | |
157 | } | |
158 | ||
159 | static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit) | |
160 | { | |
161 | int order; | |
162 | ||
163 | set_bit(ec_bit, &pcpu->ec_mask); | |
164 | order = pcpu_running(pcpu) ? | |
a9ae32c3 | 165 | SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL; |
8b646bd7 MS |
166 | pcpu_sigp_retry(pcpu, order, 0); |
167 | } | |
168 | ||
169 | static int __cpuinit pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu) | |
170 | { | |
171 | struct _lowcore *lc; | |
172 | ||
173 | if (pcpu != &pcpu_devices[0]) { | |
174 | pcpu->lowcore = (struct _lowcore *) | |
175 | __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); | |
176 | pcpu->async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER); | |
177 | pcpu->panic_stack = __get_free_page(GFP_KERNEL); | |
178 | if (!pcpu->lowcore || !pcpu->panic_stack || !pcpu->async_stack) | |
179 | goto out; | |
1943f53c | 180 | } |
8b646bd7 MS |
181 | lc = pcpu->lowcore; |
182 | memcpy(lc, &S390_lowcore, 512); | |
183 | memset((char *) lc + 512, 0, sizeof(*lc) - 512); | |
dc7ee00d MS |
184 | lc->async_stack = pcpu->async_stack + ASYNC_SIZE |
185 | - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs); | |
186 | lc->panic_stack = pcpu->panic_stack + PAGE_SIZE | |
187 | - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs); | |
8b646bd7 MS |
188 | lc->cpu_nr = cpu; |
189 | #ifndef CONFIG_64BIT | |
190 | if (MACHINE_HAS_IEEE) { | |
191 | lc->extended_save_area_addr = get_zeroed_page(GFP_KERNEL); | |
192 | if (!lc->extended_save_area_addr) | |
193 | goto out; | |
194 | } | |
195 | #else | |
196 | if (vdso_alloc_per_cpu(lc)) | |
197 | goto out; | |
198 | #endif | |
199 | lowcore_ptr[cpu] = lc; | |
a9ae32c3 | 200 | pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc); |
8b646bd7 MS |
201 | return 0; |
202 | out: | |
203 | if (pcpu != &pcpu_devices[0]) { | |
204 | free_page(pcpu->panic_stack); | |
205 | free_pages(pcpu->async_stack, ASYNC_ORDER); | |
206 | free_pages((unsigned long) pcpu->lowcore, LC_ORDER); | |
207 | } | |
208 | return -ENOMEM; | |
1943f53c MH |
209 | } |
210 | ||
9d0f46af HC |
211 | #ifdef CONFIG_HOTPLUG_CPU |
212 | ||
8b646bd7 | 213 | static void pcpu_free_lowcore(struct pcpu *pcpu) |
2c2df118 | 214 | { |
a9ae32c3 | 215 | pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0); |
8b646bd7 MS |
216 | lowcore_ptr[pcpu - pcpu_devices] = NULL; |
217 | #ifndef CONFIG_64BIT | |
218 | if (MACHINE_HAS_IEEE) { | |
219 | struct _lowcore *lc = pcpu->lowcore; | |
220 | ||
221 | free_page((unsigned long) lc->extended_save_area_addr); | |
222 | lc->extended_save_area_addr = 0; | |
223 | } | |
224 | #else | |
225 | vdso_free_per_cpu(pcpu->lowcore); | |
226 | #endif | |
227 | if (pcpu != &pcpu_devices[0]) { | |
228 | free_page(pcpu->panic_stack); | |
229 | free_pages(pcpu->async_stack, ASYNC_ORDER); | |
230 | free_pages((unsigned long) pcpu->lowcore, LC_ORDER); | |
231 | } | |
232 | } | |
233 | ||
9d0f46af HC |
234 | #endif /* CONFIG_HOTPLUG_CPU */ |
235 | ||
8b646bd7 MS |
236 | static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu) |
237 | { | |
238 | struct _lowcore *lc = pcpu->lowcore; | |
239 | ||
240 | atomic_inc(&init_mm.context.attach_count); | |
241 | lc->cpu_nr = cpu; | |
242 | lc->percpu_offset = __per_cpu_offset[cpu]; | |
243 | lc->kernel_asce = S390_lowcore.kernel_asce; | |
244 | lc->machine_flags = S390_lowcore.machine_flags; | |
245 | lc->ftrace_func = S390_lowcore.ftrace_func; | |
246 | lc->user_timer = lc->system_timer = lc->steal_timer = 0; | |
247 | __ctl_store(lc->cregs_save_area, 0, 15); | |
248 | save_access_regs((unsigned int *) lc->access_regs_save_area); | |
249 | memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list, | |
250 | MAX_FACILITY_BIT/8); | |
251 | } | |
252 | ||
253 | static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk) | |
254 | { | |
255 | struct _lowcore *lc = pcpu->lowcore; | |
256 | struct thread_info *ti = task_thread_info(tsk); | |
257 | ||
dc7ee00d MS |
258 | lc->kernel_stack = (unsigned long) task_stack_page(tsk) |
259 | + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs); | |
8b646bd7 MS |
260 | lc->thread_info = (unsigned long) task_thread_info(tsk); |
261 | lc->current_task = (unsigned long) tsk; | |
262 | lc->user_timer = ti->user_timer; | |
263 | lc->system_timer = ti->system_timer; | |
264 | lc->steal_timer = 0; | |
265 | } | |
266 | ||
267 | static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data) | |
268 | { | |
269 | struct _lowcore *lc = pcpu->lowcore; | |
270 | ||
271 | lc->restart_stack = lc->kernel_stack; | |
272 | lc->restart_fn = (unsigned long) func; | |
273 | lc->restart_data = (unsigned long) data; | |
274 | lc->restart_source = -1UL; | |
a9ae32c3 | 275 | pcpu_sigp_retry(pcpu, SIGP_RESTART, 0); |
8b646bd7 MS |
276 | } |
277 | ||
278 | /* | |
279 | * Call function via PSW restart on pcpu and stop the current cpu. | |
280 | */ | |
281 | static void pcpu_delegate(struct pcpu *pcpu, void (*func)(void *), | |
282 | void *data, unsigned long stack) | |
283 | { | |
061da3df | 284 | struct _lowcore *lc = lowcore_ptr[pcpu - pcpu_devices]; |
fbe76568 | 285 | unsigned long source_cpu = stap(); |
8b646bd7 MS |
286 | |
287 | __load_psw_mask(psw_kernel_bits); | |
fbe76568 | 288 | if (pcpu->address == source_cpu) |
8b646bd7 MS |
289 | func(data); /* should not return */ |
290 | /* Stop target cpu (if func returns this stops the current cpu). */ | |
a9ae32c3 | 291 | pcpu_sigp_retry(pcpu, SIGP_STOP, 0); |
8b646bd7 | 292 | /* Restart func on the target cpu and stop the current cpu. */ |
fbe76568 HC |
293 | mem_assign_absolute(lc->restart_stack, stack); |
294 | mem_assign_absolute(lc->restart_fn, (unsigned long) func); | |
295 | mem_assign_absolute(lc->restart_data, (unsigned long) data); | |
296 | mem_assign_absolute(lc->restart_source, source_cpu); | |
8b646bd7 | 297 | asm volatile( |
eb546195 | 298 | "0: sigp 0,%0,%2 # sigp restart to target cpu\n" |
8b646bd7 | 299 | " brc 2,0b # busy, try again\n" |
eb546195 | 300 | "1: sigp 0,%1,%3 # sigp stop to current cpu\n" |
8b646bd7 | 301 | " brc 2,1b # busy, try again\n" |
fbe76568 | 302 | : : "d" (pcpu->address), "d" (source_cpu), |
eb546195 HC |
303 | "K" (SIGP_RESTART), "K" (SIGP_STOP) |
304 | : "0", "1", "cc"); | |
8b646bd7 MS |
305 | for (;;) ; |
306 | } | |
307 | ||
308 | /* | |
309 | * Call function on an online CPU. | |
310 | */ | |
311 | void smp_call_online_cpu(void (*func)(void *), void *data) | |
312 | { | |
313 | struct pcpu *pcpu; | |
314 | ||
315 | /* Use the current cpu if it is online. */ | |
316 | pcpu = pcpu_find_address(cpu_online_mask, stap()); | |
317 | if (!pcpu) | |
318 | /* Use the first online cpu. */ | |
319 | pcpu = pcpu_devices + cpumask_first(cpu_online_mask); | |
320 | pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack); | |
321 | } | |
322 | ||
323 | /* | |
324 | * Call function on the ipl CPU. | |
325 | */ | |
326 | void smp_call_ipl_cpu(void (*func)(void *), void *data) | |
327 | { | |
c6da39f2 MH |
328 | pcpu_delegate(&pcpu_devices[0], func, data, |
329 | pcpu_devices->panic_stack + PAGE_SIZE); | |
8b646bd7 MS |
330 | } |
331 | ||
332 | int smp_find_processor_id(u16 address) | |
333 | { | |
334 | int cpu; | |
335 | ||
336 | for_each_present_cpu(cpu) | |
337 | if (pcpu_devices[cpu].address == address) | |
338 | return cpu; | |
339 | return -1; | |
2c2df118 HC |
340 | } |
341 | ||
8b646bd7 | 342 | int smp_vcpu_scheduled(int cpu) |
85ac7ca5 | 343 | { |
8b646bd7 MS |
344 | return pcpu_running(pcpu_devices + cpu); |
345 | } | |
346 | ||
347 | void smp_yield(void) | |
348 | { | |
349 | if (MACHINE_HAS_DIAG44) | |
350 | asm volatile("diag 0,0,0x44"); | |
2c2df118 HC |
351 | } |
352 | ||
8b646bd7 | 353 | void smp_yield_cpu(int cpu) |
85ac7ca5 | 354 | { |
8b646bd7 MS |
355 | if (MACHINE_HAS_DIAG9C) |
356 | asm volatile("diag %0,0,0x9c" | |
357 | : : "d" (pcpu_devices[cpu].address)); | |
358 | else if (MACHINE_HAS_DIAG44) | |
359 | asm volatile("diag 0,0,0x44"); | |
360 | } | |
361 | ||
362 | /* | |
363 | * Send cpus emergency shutdown signal. This gives the cpus the | |
364 | * opportunity to complete outstanding interrupts. | |
365 | */ | |
366 | void smp_emergency_stop(cpumask_t *cpumask) | |
367 | { | |
368 | u64 end; | |
369 | int cpu; | |
370 | ||
1aae0560 | 371 | end = get_tod_clock() + (1000000UL << 12); |
8b646bd7 MS |
372 | for_each_cpu(cpu, cpumask) { |
373 | struct pcpu *pcpu = pcpu_devices + cpu; | |
374 | set_bit(ec_stop_cpu, &pcpu->ec_mask); | |
a9ae32c3 HC |
375 | while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL, |
376 | 0, NULL) == SIGP_CC_BUSY && | |
1aae0560 | 377 | get_tod_clock() < end) |
8b646bd7 MS |
378 | cpu_relax(); |
379 | } | |
1aae0560 | 380 | while (get_tod_clock() < end) { |
8b646bd7 MS |
381 | for_each_cpu(cpu, cpumask) |
382 | if (pcpu_stopped(pcpu_devices + cpu)) | |
383 | cpumask_clear_cpu(cpu, cpumask); | |
384 | if (cpumask_empty(cpumask)) | |
385 | break; | |
85ac7ca5 | 386 | cpu_relax(); |
8b646bd7 | 387 | } |
85ac7ca5 MS |
388 | } |
389 | ||
8b646bd7 MS |
390 | /* |
391 | * Stop all cpus but the current one. | |
392 | */ | |
677d7623 | 393 | void smp_send_stop(void) |
1da177e4 | 394 | { |
85ac7ca5 MS |
395 | cpumask_t cpumask; |
396 | int cpu; | |
1da177e4 | 397 | |
677d7623 | 398 | /* Disable all interrupts/machine checks */ |
b50511e4 | 399 | __load_psw_mask(psw_kernel_bits | PSW_MASK_DAT); |
3324e60a | 400 | trace_hardirqs_off(); |
1da177e4 | 401 | |
3ab121ab | 402 | debug_set_critical(); |
85ac7ca5 MS |
403 | cpumask_copy(&cpumask, cpu_online_mask); |
404 | cpumask_clear_cpu(smp_processor_id(), &cpumask); | |
405 | ||
8b646bd7 MS |
406 | if (oops_in_progress) |
407 | smp_emergency_stop(&cpumask); | |
1da177e4 | 408 | |
85ac7ca5 MS |
409 | /* stop all processors */ |
410 | for_each_cpu(cpu, &cpumask) { | |
8b646bd7 | 411 | struct pcpu *pcpu = pcpu_devices + cpu; |
a9ae32c3 | 412 | pcpu_sigp_retry(pcpu, SIGP_STOP, 0); |
8b646bd7 | 413 | while (!pcpu_stopped(pcpu)) |
c6b5b847 HC |
414 | cpu_relax(); |
415 | } | |
416 | } | |
417 | ||
8b646bd7 MS |
418 | /* |
419 | * Stop the current cpu. | |
420 | */ | |
421 | void smp_stop_cpu(void) | |
422 | { | |
a9ae32c3 | 423 | pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0); |
8b646bd7 MS |
424 | for (;;) ; |
425 | } | |
426 | ||
1da177e4 LT |
427 | /* |
428 | * This is the main routine where commands issued by other | |
429 | * cpus are handled. | |
430 | */ | |
fde15c3a | 431 | static void do_ext_call_interrupt(struct ext_code ext_code, |
f6649a7e | 432 | unsigned int param32, unsigned long param64) |
1da177e4 | 433 | { |
39ce010d | 434 | unsigned long bits; |
8b646bd7 | 435 | int cpu; |
1da177e4 | 436 | |
8b646bd7 | 437 | cpu = smp_processor_id(); |
fde15c3a | 438 | if (ext_code.code == 0x1202) |
420f42ec | 439 | inc_irq_stat(IRQEXT_EXC); |
2a3a2d66 | 440 | else |
420f42ec | 441 | inc_irq_stat(IRQEXT_EMS); |
39ce010d HC |
442 | /* |
443 | * handle bit signal external calls | |
39ce010d | 444 | */ |
8b646bd7 | 445 | bits = xchg(&pcpu_devices[cpu].ec_mask, 0); |
1da177e4 | 446 | |
85ac7ca5 MS |
447 | if (test_bit(ec_stop_cpu, &bits)) |
448 | smp_stop_cpu(); | |
449 | ||
184748cc PZ |
450 | if (test_bit(ec_schedule, &bits)) |
451 | scheduler_ipi(); | |
452 | ||
39ce010d | 453 | if (test_bit(ec_call_function, &bits)) |
ca9fc75a HC |
454 | generic_smp_call_function_interrupt(); |
455 | ||
456 | if (test_bit(ec_call_function_single, &bits)) | |
457 | generic_smp_call_function_single_interrupt(); | |
85ac7ca5 | 458 | |
1da177e4 LT |
459 | } |
460 | ||
630cd046 | 461 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
ca9fc75a HC |
462 | { |
463 | int cpu; | |
464 | ||
630cd046 | 465 | for_each_cpu(cpu, mask) |
8b646bd7 | 466 | pcpu_ec_call(pcpu_devices + cpu, ec_call_function); |
ca9fc75a HC |
467 | } |
468 | ||
469 | void arch_send_call_function_single_ipi(int cpu) | |
470 | { | |
8b646bd7 | 471 | pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single); |
ca9fc75a HC |
472 | } |
473 | ||
347a8dc3 | 474 | #ifndef CONFIG_64BIT |
1da177e4 LT |
475 | /* |
476 | * this function sends a 'purge tlb' signal to another CPU. | |
477 | */ | |
a806170e | 478 | static void smp_ptlb_callback(void *info) |
1da177e4 | 479 | { |
ba8a9229 | 480 | __tlb_flush_local(); |
1da177e4 LT |
481 | } |
482 | ||
483 | void smp_ptlb_all(void) | |
484 | { | |
15c8b6c1 | 485 | on_each_cpu(smp_ptlb_callback, NULL, 1); |
1da177e4 LT |
486 | } |
487 | EXPORT_SYMBOL(smp_ptlb_all); | |
347a8dc3 | 488 | #endif /* ! CONFIG_64BIT */ |
1da177e4 LT |
489 | |
490 | /* | |
491 | * this function sends a 'reschedule' IPI to another CPU. | |
492 | * it goes straight through and wastes no time serializing | |
493 | * anything. Worst case is that we lose a reschedule ... | |
494 | */ | |
495 | void smp_send_reschedule(int cpu) | |
496 | { | |
8b646bd7 | 497 | pcpu_ec_call(pcpu_devices + cpu, ec_schedule); |
1da177e4 LT |
498 | } |
499 | ||
500 | /* | |
501 | * parameter area for the set/clear control bit callbacks | |
502 | */ | |
94c12cc7 | 503 | struct ec_creg_mask_parms { |
8b646bd7 MS |
504 | unsigned long orval; |
505 | unsigned long andval; | |
506 | int cr; | |
94c12cc7 | 507 | }; |
1da177e4 LT |
508 | |
509 | /* | |
510 | * callback for setting/clearing control bits | |
511 | */ | |
39ce010d HC |
512 | static void smp_ctl_bit_callback(void *info) |
513 | { | |
94c12cc7 | 514 | struct ec_creg_mask_parms *pp = info; |
1da177e4 | 515 | unsigned long cregs[16]; |
39ce010d | 516 | |
94c12cc7 | 517 | __ctl_store(cregs, 0, 15); |
8b646bd7 | 518 | cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval; |
94c12cc7 | 519 | __ctl_load(cregs, 0, 15); |
1da177e4 LT |
520 | } |
521 | ||
522 | /* | |
523 | * Set a bit in a control register of all cpus | |
524 | */ | |
94c12cc7 MS |
525 | void smp_ctl_set_bit(int cr, int bit) |
526 | { | |
8b646bd7 | 527 | struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr }; |
1da177e4 | 528 | |
15c8b6c1 | 529 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 530 | } |
39ce010d | 531 | EXPORT_SYMBOL(smp_ctl_set_bit); |
1da177e4 LT |
532 | |
533 | /* | |
534 | * Clear a bit in a control register of all cpus | |
535 | */ | |
94c12cc7 MS |
536 | void smp_ctl_clear_bit(int cr, int bit) |
537 | { | |
8b646bd7 | 538 | struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr }; |
1da177e4 | 539 | |
15c8b6c1 | 540 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 541 | } |
39ce010d | 542 | EXPORT_SYMBOL(smp_ctl_clear_bit); |
1da177e4 | 543 | |
60a0c68d | 544 | #if defined(CONFIG_ZFCPDUMP) || defined(CONFIG_CRASH_DUMP) |
411ed322 | 545 | |
8b646bd7 MS |
546 | struct save_area *zfcpdump_save_areas[NR_CPUS + 1]; |
547 | EXPORT_SYMBOL_GPL(zfcpdump_save_areas); | |
548 | ||
549 | static void __init smp_get_save_area(int cpu, u16 address) | |
411ed322 | 550 | { |
8b646bd7 MS |
551 | void *lc = pcpu_devices[0].lowcore; |
552 | struct save_area *save_area; | |
553 | ||
60a0c68d | 554 | if (is_kdump_kernel()) |
411ed322 | 555 | return; |
8b646bd7 MS |
556 | if (!OLDMEM_BASE && (address == boot_cpu_address || |
557 | ipl_info.type != IPL_TYPE_FCP_DUMP)) | |
558 | return; | |
285f6722 | 559 | if (cpu >= NR_CPUS) { |
8b646bd7 MS |
560 | pr_warning("CPU %i exceeds the maximum %i and is excluded " |
561 | "from the dump\n", cpu, NR_CPUS - 1); | |
285f6722 | 562 | return; |
411ed322 | 563 | } |
8b646bd7 MS |
564 | save_area = kmalloc(sizeof(struct save_area), GFP_KERNEL); |
565 | if (!save_area) | |
566 | panic("could not allocate memory for save area\n"); | |
567 | zfcpdump_save_areas[cpu] = save_area; | |
568 | #ifdef CONFIG_CRASH_DUMP | |
569 | if (address == boot_cpu_address) { | |
570 | /* Copy the registers of the boot cpu. */ | |
571 | copy_oldmem_page(1, (void *) save_area, sizeof(*save_area), | |
572 | SAVE_AREA_BASE - PAGE_SIZE, 0); | |
573 | return; | |
574 | } | |
575 | #endif | |
576 | /* Get the registers of a non-boot cpu. */ | |
a9ae32c3 | 577 | __pcpu_sigp_relax(address, SIGP_STOP_AND_STORE_STATUS, 0, NULL); |
8b646bd7 | 578 | memcpy_real(save_area, lc + SAVE_AREA_BASE, sizeof(*save_area)); |
411ed322 MH |
579 | } |
580 | ||
8b646bd7 | 581 | int smp_store_status(int cpu) |
08d07968 | 582 | { |
8b646bd7 | 583 | struct pcpu *pcpu; |
08d07968 | 584 | |
8b646bd7 | 585 | pcpu = pcpu_devices + cpu; |
a9ae32c3 HC |
586 | if (__pcpu_sigp_relax(pcpu->address, SIGP_STOP_AND_STORE_STATUS, |
587 | 0, NULL) != SIGP_CC_ORDER_CODE_ACCEPTED) | |
8b646bd7 | 588 | return -EIO; |
08d07968 HC |
589 | return 0; |
590 | } | |
591 | ||
8b646bd7 | 592 | #else /* CONFIG_ZFCPDUMP || CONFIG_CRASH_DUMP */ |
08d07968 | 593 | |
8b646bd7 | 594 | static inline void smp_get_save_area(int cpu, u16 address) { } |
08d07968 | 595 | |
8b646bd7 | 596 | #endif /* CONFIG_ZFCPDUMP || CONFIG_CRASH_DUMP */ |
08d07968 | 597 | |
50ab9a9a HC |
598 | void smp_cpu_set_polarization(int cpu, int val) |
599 | { | |
600 | pcpu_devices[cpu].polarization = val; | |
601 | } | |
602 | ||
603 | int smp_cpu_get_polarization(int cpu) | |
604 | { | |
605 | return pcpu_devices[cpu].polarization; | |
606 | } | |
607 | ||
8b646bd7 | 608 | static struct sclp_cpu_info *smp_get_cpu_info(void) |
08d07968 | 609 | { |
8b646bd7 | 610 | static int use_sigp_detection; |
08d07968 | 611 | struct sclp_cpu_info *info; |
8b646bd7 MS |
612 | int address; |
613 | ||
614 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
615 | if (info && (use_sigp_detection || sclp_get_cpu_info(info))) { | |
616 | use_sigp_detection = 1; | |
617 | for (address = 0; address <= MAX_CPU_ADDRESS; address++) { | |
a9ae32c3 HC |
618 | if (__pcpu_sigp_relax(address, SIGP_SENSE, 0, NULL) == |
619 | SIGP_CC_NOT_OPERATIONAL) | |
8b646bd7 MS |
620 | continue; |
621 | info->cpu[info->configured].address = address; | |
622 | info->configured++; | |
623 | } | |
624 | info->combined = info->configured; | |
08d07968 | 625 | } |
8b646bd7 | 626 | return info; |
08d07968 HC |
627 | } |
628 | ||
eba61970 | 629 | static int __cpuinit smp_add_present_cpu(int cpu); |
8b646bd7 | 630 | |
eba61970 HC |
631 | static int __cpuinit __smp_rescan_cpus(struct sclp_cpu_info *info, |
632 | int sysfs_add) | |
08d07968 | 633 | { |
8b646bd7 | 634 | struct pcpu *pcpu; |
08d07968 | 635 | cpumask_t avail; |
8b646bd7 | 636 | int cpu, nr, i; |
08d07968 | 637 | |
8b646bd7 | 638 | nr = 0; |
0f1959f5 | 639 | cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask); |
8b646bd7 MS |
640 | cpu = cpumask_first(&avail); |
641 | for (i = 0; (i < info->combined) && (cpu < nr_cpu_ids); i++) { | |
642 | if (info->has_cpu_type && info->cpu[i].type != boot_cpu_type) | |
643 | continue; | |
644 | if (pcpu_find_address(cpu_present_mask, info->cpu[i].address)) | |
645 | continue; | |
646 | pcpu = pcpu_devices + cpu; | |
647 | pcpu->address = info->cpu[i].address; | |
a4eeea4e | 648 | pcpu->state = (i >= info->configured) ? |
8b646bd7 | 649 | CPU_STATE_STANDBY : CPU_STATE_CONFIGURED; |
50ab9a9a | 650 | smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); |
8b646bd7 MS |
651 | set_cpu_present(cpu, true); |
652 | if (sysfs_add && smp_add_present_cpu(cpu) != 0) | |
653 | set_cpu_present(cpu, false); | |
654 | else | |
655 | nr++; | |
656 | cpu = cpumask_next(cpu, &avail); | |
657 | } | |
658 | return nr; | |
1da177e4 LT |
659 | } |
660 | ||
48483b32 HC |
661 | static void __init smp_detect_cpus(void) |
662 | { | |
663 | unsigned int cpu, c_cpus, s_cpus; | |
664 | struct sclp_cpu_info *info; | |
48483b32 | 665 | |
8b646bd7 | 666 | info = smp_get_cpu_info(); |
48483b32 HC |
667 | if (!info) |
668 | panic("smp_detect_cpus failed to allocate memory\n"); | |
48483b32 HC |
669 | if (info->has_cpu_type) { |
670 | for (cpu = 0; cpu < info->combined; cpu++) { | |
8b646bd7 MS |
671 | if (info->cpu[cpu].address != boot_cpu_address) |
672 | continue; | |
673 | /* The boot cpu dictates the cpu type. */ | |
674 | boot_cpu_type = info->cpu[cpu].type; | |
675 | break; | |
48483b32 HC |
676 | } |
677 | } | |
8b646bd7 | 678 | c_cpus = s_cpus = 0; |
48483b32 | 679 | for (cpu = 0; cpu < info->combined; cpu++) { |
8b646bd7 | 680 | if (info->has_cpu_type && info->cpu[cpu].type != boot_cpu_type) |
48483b32 | 681 | continue; |
8b646bd7 MS |
682 | if (cpu < info->configured) { |
683 | smp_get_save_area(c_cpus, info->cpu[cpu].address); | |
684 | c_cpus++; | |
685 | } else | |
48483b32 | 686 | s_cpus++; |
48483b32 | 687 | } |
395d31d4 | 688 | pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus); |
9d40d2e3 | 689 | get_online_cpus(); |
8b646bd7 | 690 | __smp_rescan_cpus(info, 0); |
9d40d2e3 | 691 | put_online_cpus(); |
8b646bd7 | 692 | kfree(info); |
48483b32 HC |
693 | } |
694 | ||
1da177e4 | 695 | /* |
39ce010d | 696 | * Activate a secondary processor. |
1da177e4 | 697 | */ |
8b646bd7 | 698 | static void __cpuinit smp_start_secondary(void *cpuvoid) |
1da177e4 | 699 | { |
1aae0560 | 700 | S390_lowcore.last_update_clock = get_tod_clock(); |
8b646bd7 MS |
701 | S390_lowcore.restart_stack = (unsigned long) restart_stack; |
702 | S390_lowcore.restart_fn = (unsigned long) do_restart; | |
703 | S390_lowcore.restart_data = 0; | |
704 | S390_lowcore.restart_source = -1UL; | |
705 | restore_access_regs(S390_lowcore.access_regs_save_area); | |
706 | __ctl_load(S390_lowcore.cregs_save_area, 0, 15); | |
707 | __load_psw_mask(psw_kernel_bits | PSW_MASK_DAT); | |
39ce010d | 708 | cpu_init(); |
5bfb5d69 | 709 | preempt_disable(); |
39ce010d | 710 | init_cpu_timer(); |
39ce010d | 711 | init_cpu_vtimer(); |
29b08d2b | 712 | pfault_init(); |
e545a614 | 713 | notify_cpu_starting(smp_processor_id()); |
0f1959f5 | 714 | set_cpu_online(smp_processor_id(), true); |
93f3b2ee | 715 | inc_irq_stat(CPU_RST); |
1da177e4 | 716 | local_irq_enable(); |
52c00659 | 717 | cpu_startup_entry(CPUHP_ONLINE); |
1da177e4 LT |
718 | } |
719 | ||
1da177e4 | 720 | /* Upping and downing of CPUs */ |
8239c25f | 721 | int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 722 | { |
8b646bd7 MS |
723 | struct pcpu *pcpu; |
724 | int rc; | |
1da177e4 | 725 | |
8b646bd7 MS |
726 | pcpu = pcpu_devices + cpu; |
727 | if (pcpu->state != CPU_STATE_CONFIGURED) | |
08d07968 | 728 | return -EIO; |
a9ae32c3 HC |
729 | if (pcpu_sigp_retry(pcpu, SIGP_INITIAL_CPU_RESET, 0) != |
730 | SIGP_CC_ORDER_CODE_ACCEPTED) | |
08d07968 | 731 | return -EIO; |
e80e7813 | 732 | |
8b646bd7 MS |
733 | rc = pcpu_alloc_lowcore(pcpu, cpu); |
734 | if (rc) | |
735 | return rc; | |
736 | pcpu_prepare_secondary(pcpu, cpu); | |
e80e7813 | 737 | pcpu_attach_task(pcpu, tidle); |
8b646bd7 | 738 | pcpu_start_fn(pcpu, smp_start_secondary, NULL); |
1da177e4 LT |
739 | while (!cpu_online(cpu)) |
740 | cpu_relax(); | |
741 | return 0; | |
742 | } | |
743 | ||
48483b32 | 744 | static int __init setup_possible_cpus(char *s) |
255acee7 | 745 | { |
8b646bd7 | 746 | int max, cpu; |
255acee7 | 747 | |
8b646bd7 MS |
748 | if (kstrtoint(s, 0, &max) < 0) |
749 | return 0; | |
88e01285 | 750 | init_cpu_possible(cpumask_of(0)); |
8b646bd7 | 751 | for (cpu = 1; cpu < max && cpu < nr_cpu_ids; cpu++) |
def6cfb7 | 752 | set_cpu_possible(cpu, true); |
37a33026 HC |
753 | return 0; |
754 | } | |
755 | early_param("possible_cpus", setup_possible_cpus); | |
756 | ||
48483b32 HC |
757 | #ifdef CONFIG_HOTPLUG_CPU |
758 | ||
39ce010d | 759 | int __cpu_disable(void) |
1da177e4 | 760 | { |
8b646bd7 | 761 | unsigned long cregs[16]; |
1da177e4 | 762 | |
8b646bd7 MS |
763 | set_cpu_online(smp_processor_id(), false); |
764 | /* Disable pseudo page faults on this cpu. */ | |
29b08d2b | 765 | pfault_fini(); |
8b646bd7 MS |
766 | /* Disable interrupt sources via control register. */ |
767 | __ctl_store(cregs, 0, 15); | |
768 | cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */ | |
769 | cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */ | |
770 | cregs[14] &= ~0x1f000000UL; /* disable most machine checks */ | |
771 | __ctl_load(cregs, 0, 15); | |
1da177e4 LT |
772 | return 0; |
773 | } | |
774 | ||
39ce010d | 775 | void __cpu_die(unsigned int cpu) |
1da177e4 | 776 | { |
8b646bd7 MS |
777 | struct pcpu *pcpu; |
778 | ||
1da177e4 | 779 | /* Wait until target cpu is down */ |
8b646bd7 MS |
780 | pcpu = pcpu_devices + cpu; |
781 | while (!pcpu_stopped(pcpu)) | |
1da177e4 | 782 | cpu_relax(); |
8b646bd7 | 783 | pcpu_free_lowcore(pcpu); |
050eef36 | 784 | atomic_dec(&init_mm.context.attach_count); |
1da177e4 LT |
785 | } |
786 | ||
b456d94a | 787 | void __noreturn cpu_die(void) |
1da177e4 LT |
788 | { |
789 | idle_task_exit(); | |
a9ae32c3 | 790 | pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0); |
8b646bd7 | 791 | for (;;) ; |
1da177e4 LT |
792 | } |
793 | ||
255acee7 HC |
794 | #endif /* CONFIG_HOTPLUG_CPU */ |
795 | ||
1da177e4 LT |
796 | void __init smp_prepare_cpus(unsigned int max_cpus) |
797 | { | |
39ce010d HC |
798 | /* request the 0x1201 emergency signal external interrupt */ |
799 | if (register_external_interrupt(0x1201, do_ext_call_interrupt) != 0) | |
800 | panic("Couldn't request external interrupt 0x1201"); | |
d98e19cc MS |
801 | /* request the 0x1202 external call external interrupt */ |
802 | if (register_external_interrupt(0x1202, do_ext_call_interrupt) != 0) | |
803 | panic("Couldn't request external interrupt 0x1202"); | |
8b646bd7 | 804 | smp_detect_cpus(); |
1da177e4 LT |
805 | } |
806 | ||
ea1f4eec | 807 | void __init smp_prepare_boot_cpu(void) |
1da177e4 | 808 | { |
8b646bd7 MS |
809 | struct pcpu *pcpu = pcpu_devices; |
810 | ||
811 | boot_cpu_address = stap(); | |
8b646bd7 MS |
812 | pcpu->state = CPU_STATE_CONFIGURED; |
813 | pcpu->address = boot_cpu_address; | |
814 | pcpu->lowcore = (struct _lowcore *)(unsigned long) store_prefix(); | |
dc7ee00d MS |
815 | pcpu->async_stack = S390_lowcore.async_stack - ASYNC_SIZE |
816 | + STACK_FRAME_OVERHEAD + sizeof(struct pt_regs); | |
817 | pcpu->panic_stack = S390_lowcore.panic_stack - PAGE_SIZE | |
818 | + STACK_FRAME_OVERHEAD + sizeof(struct pt_regs); | |
1da177e4 | 819 | S390_lowcore.percpu_offset = __per_cpu_offset[0]; |
50ab9a9a | 820 | smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN); |
8b646bd7 MS |
821 | set_cpu_present(0, true); |
822 | set_cpu_online(0, true); | |
1da177e4 LT |
823 | } |
824 | ||
ea1f4eec | 825 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 826 | { |
1da177e4 LT |
827 | } |
828 | ||
02beaccc HC |
829 | void __init smp_setup_processor_id(void) |
830 | { | |
831 | S390_lowcore.cpu_nr = 0; | |
02beaccc HC |
832 | } |
833 | ||
1da177e4 LT |
834 | /* |
835 | * the frequency of the profiling timer can be changed | |
836 | * by writing a multiplier value into /proc/profile. | |
837 | * | |
838 | * usually you want to run this on all CPUs ;) | |
839 | */ | |
840 | int setup_profiling_timer(unsigned int multiplier) | |
841 | { | |
39ce010d | 842 | return 0; |
1da177e4 LT |
843 | } |
844 | ||
08d07968 | 845 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd | 846 | static ssize_t cpu_configure_show(struct device *dev, |
8b646bd7 | 847 | struct device_attribute *attr, char *buf) |
08d07968 HC |
848 | { |
849 | ssize_t count; | |
850 | ||
851 | mutex_lock(&smp_cpu_state_mutex); | |
8b646bd7 | 852 | count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state); |
08d07968 HC |
853 | mutex_unlock(&smp_cpu_state_mutex); |
854 | return count; | |
855 | } | |
856 | ||
8a25a2fd | 857 | static ssize_t cpu_configure_store(struct device *dev, |
8b646bd7 MS |
858 | struct device_attribute *attr, |
859 | const char *buf, size_t count) | |
08d07968 | 860 | { |
8b646bd7 MS |
861 | struct pcpu *pcpu; |
862 | int cpu, val, rc; | |
08d07968 HC |
863 | char delim; |
864 | ||
865 | if (sscanf(buf, "%d %c", &val, &delim) != 1) | |
866 | return -EINVAL; | |
867 | if (val != 0 && val != 1) | |
868 | return -EINVAL; | |
9d40d2e3 | 869 | get_online_cpus(); |
0b18d318 | 870 | mutex_lock(&smp_cpu_state_mutex); |
08d07968 | 871 | rc = -EBUSY; |
2c2df118 | 872 | /* disallow configuration changes of online cpus and cpu 0 */ |
8b646bd7 | 873 | cpu = dev->id; |
2c2df118 | 874 | if (cpu_online(cpu) || cpu == 0) |
08d07968 | 875 | goto out; |
8b646bd7 | 876 | pcpu = pcpu_devices + cpu; |
08d07968 HC |
877 | rc = 0; |
878 | switch (val) { | |
879 | case 0: | |
8b646bd7 MS |
880 | if (pcpu->state != CPU_STATE_CONFIGURED) |
881 | break; | |
882 | rc = sclp_cpu_deconfigure(pcpu->address); | |
883 | if (rc) | |
884 | break; | |
885 | pcpu->state = CPU_STATE_STANDBY; | |
50ab9a9a | 886 | smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); |
8b646bd7 | 887 | topology_expect_change(); |
08d07968 HC |
888 | break; |
889 | case 1: | |
8b646bd7 MS |
890 | if (pcpu->state != CPU_STATE_STANDBY) |
891 | break; | |
892 | rc = sclp_cpu_configure(pcpu->address); | |
893 | if (rc) | |
894 | break; | |
895 | pcpu->state = CPU_STATE_CONFIGURED; | |
50ab9a9a | 896 | smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); |
8b646bd7 | 897 | topology_expect_change(); |
08d07968 HC |
898 | break; |
899 | default: | |
900 | break; | |
901 | } | |
902 | out: | |
08d07968 | 903 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 904 | put_online_cpus(); |
08d07968 HC |
905 | return rc ? rc : count; |
906 | } | |
8a25a2fd | 907 | static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store); |
08d07968 HC |
908 | #endif /* CONFIG_HOTPLUG_CPU */ |
909 | ||
8a25a2fd KS |
910 | static ssize_t show_cpu_address(struct device *dev, |
911 | struct device_attribute *attr, char *buf) | |
08d07968 | 912 | { |
8b646bd7 | 913 | return sprintf(buf, "%d\n", pcpu_devices[dev->id].address); |
08d07968 | 914 | } |
8a25a2fd | 915 | static DEVICE_ATTR(address, 0444, show_cpu_address, NULL); |
08d07968 | 916 | |
08d07968 HC |
917 | static struct attribute *cpu_common_attrs[] = { |
918 | #ifdef CONFIG_HOTPLUG_CPU | |
8a25a2fd | 919 | &dev_attr_configure.attr, |
08d07968 | 920 | #endif |
8a25a2fd | 921 | &dev_attr_address.attr, |
08d07968 HC |
922 | NULL, |
923 | }; | |
924 | ||
925 | static struct attribute_group cpu_common_attr_group = { | |
926 | .attrs = cpu_common_attrs, | |
927 | }; | |
1da177e4 | 928 | |
8a25a2fd KS |
929 | static ssize_t show_idle_count(struct device *dev, |
930 | struct device_attribute *attr, char *buf) | |
fae8b22d | 931 | { |
4c1051e3 | 932 | struct s390_idle_data *idle = &per_cpu(s390_idle, dev->id); |
fae8b22d | 933 | unsigned long long idle_count; |
e98bbaaf | 934 | unsigned int sequence; |
fae8b22d | 935 | |
4c1051e3 MS |
936 | do { |
937 | sequence = ACCESS_ONCE(idle->sequence); | |
938 | idle_count = ACCESS_ONCE(idle->idle_count); | |
27f6b416 | 939 | if (ACCESS_ONCE(idle->clock_idle_enter)) |
4c1051e3 MS |
940 | idle_count++; |
941 | } while ((sequence & 1) || (idle->sequence != sequence)); | |
fae8b22d HC |
942 | return sprintf(buf, "%llu\n", idle_count); |
943 | } | |
8a25a2fd | 944 | static DEVICE_ATTR(idle_count, 0444, show_idle_count, NULL); |
fae8b22d | 945 | |
8a25a2fd KS |
946 | static ssize_t show_idle_time(struct device *dev, |
947 | struct device_attribute *attr, char *buf) | |
fae8b22d | 948 | { |
4c1051e3 MS |
949 | struct s390_idle_data *idle = &per_cpu(s390_idle, dev->id); |
950 | unsigned long long now, idle_time, idle_enter, idle_exit; | |
e98bbaaf | 951 | unsigned int sequence; |
fae8b22d | 952 | |
4c1051e3 | 953 | do { |
1aae0560 | 954 | now = get_tod_clock(); |
4c1051e3 MS |
955 | sequence = ACCESS_ONCE(idle->sequence); |
956 | idle_time = ACCESS_ONCE(idle->idle_time); | |
27f6b416 MS |
957 | idle_enter = ACCESS_ONCE(idle->clock_idle_enter); |
958 | idle_exit = ACCESS_ONCE(idle->clock_idle_exit); | |
4c1051e3 MS |
959 | } while ((sequence & 1) || (idle->sequence != sequence)); |
960 | idle_time += idle_enter ? ((idle_exit ? : now) - idle_enter) : 0; | |
6f430924 | 961 | return sprintf(buf, "%llu\n", idle_time >> 12); |
fae8b22d | 962 | } |
8a25a2fd | 963 | static DEVICE_ATTR(idle_time_us, 0444, show_idle_time, NULL); |
fae8b22d | 964 | |
08d07968 | 965 | static struct attribute *cpu_online_attrs[] = { |
8a25a2fd KS |
966 | &dev_attr_idle_count.attr, |
967 | &dev_attr_idle_time_us.attr, | |
fae8b22d HC |
968 | NULL, |
969 | }; | |
970 | ||
08d07968 HC |
971 | static struct attribute_group cpu_online_attr_group = { |
972 | .attrs = cpu_online_attrs, | |
fae8b22d HC |
973 | }; |
974 | ||
2fc2d1e9 HC |
975 | static int __cpuinit smp_cpu_notify(struct notifier_block *self, |
976 | unsigned long action, void *hcpu) | |
977 | { | |
978 | unsigned int cpu = (unsigned int)(long)hcpu; | |
8b646bd7 | 979 | struct cpu *c = &pcpu_devices[cpu].cpu; |
8a25a2fd | 980 | struct device *s = &c->dev; |
d882ba69 | 981 | int err = 0; |
2fc2d1e9 | 982 | |
1c725922 | 983 | switch (action & ~CPU_TASKS_FROZEN) { |
2fc2d1e9 | 984 | case CPU_ONLINE: |
d882ba69 | 985 | err = sysfs_create_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
986 | break; |
987 | case CPU_DEAD: | |
08d07968 | 988 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
989 | break; |
990 | } | |
d882ba69 | 991 | return notifier_from_errno(err); |
2fc2d1e9 HC |
992 | } |
993 | ||
eba61970 | 994 | static int __cpuinit smp_add_present_cpu(int cpu) |
08d07968 | 995 | { |
8b646bd7 | 996 | struct cpu *c = &pcpu_devices[cpu].cpu; |
8a25a2fd | 997 | struct device *s = &c->dev; |
08d07968 HC |
998 | int rc; |
999 | ||
1000 | c->hotpluggable = 1; | |
1001 | rc = register_cpu(c, cpu); | |
1002 | if (rc) | |
1003 | goto out; | |
1004 | rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group); | |
1005 | if (rc) | |
1006 | goto out_cpu; | |
83a24e32 HC |
1007 | if (cpu_online(cpu)) { |
1008 | rc = sysfs_create_group(&s->kobj, &cpu_online_attr_group); | |
1009 | if (rc) | |
1010 | goto out_online; | |
1011 | } | |
1012 | rc = topology_cpu_init(c); | |
1013 | if (rc) | |
1014 | goto out_topology; | |
1015 | return 0; | |
1016 | ||
1017 | out_topology: | |
1018 | if (cpu_online(cpu)) | |
1019 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); | |
1020 | out_online: | |
08d07968 HC |
1021 | sysfs_remove_group(&s->kobj, &cpu_common_attr_group); |
1022 | out_cpu: | |
1023 | #ifdef CONFIG_HOTPLUG_CPU | |
1024 | unregister_cpu(c); | |
1025 | #endif | |
1026 | out: | |
1027 | return rc; | |
1028 | } | |
1029 | ||
1030 | #ifdef CONFIG_HOTPLUG_CPU | |
1e489518 | 1031 | |
67060d9c | 1032 | int __ref smp_rescan_cpus(void) |
08d07968 | 1033 | { |
8b646bd7 MS |
1034 | struct sclp_cpu_info *info; |
1035 | int nr; | |
08d07968 | 1036 | |
8b646bd7 MS |
1037 | info = smp_get_cpu_info(); |
1038 | if (!info) | |
1039 | return -ENOMEM; | |
9d40d2e3 | 1040 | get_online_cpus(); |
0b18d318 | 1041 | mutex_lock(&smp_cpu_state_mutex); |
8b646bd7 | 1042 | nr = __smp_rescan_cpus(info, 1); |
08d07968 | 1043 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 1044 | put_online_cpus(); |
8b646bd7 MS |
1045 | kfree(info); |
1046 | if (nr) | |
c10fde0d | 1047 | topology_schedule_update(); |
8b646bd7 | 1048 | return 0; |
1e489518 HC |
1049 | } |
1050 | ||
8a25a2fd KS |
1051 | static ssize_t __ref rescan_store(struct device *dev, |
1052 | struct device_attribute *attr, | |
c9be0a36 | 1053 | const char *buf, |
1e489518 HC |
1054 | size_t count) |
1055 | { | |
1056 | int rc; | |
1057 | ||
1058 | rc = smp_rescan_cpus(); | |
08d07968 HC |
1059 | return rc ? rc : count; |
1060 | } | |
8a25a2fd | 1061 | static DEVICE_ATTR(rescan, 0200, NULL, rescan_store); |
08d07968 HC |
1062 | #endif /* CONFIG_HOTPLUG_CPU */ |
1063 | ||
83a24e32 | 1064 | static int __init s390_smp_init(void) |
1da177e4 | 1065 | { |
83a24e32 | 1066 | int cpu, rc; |
2fc2d1e9 | 1067 | |
7755d6b2 | 1068 | hotcpu_notifier(smp_cpu_notify, 0); |
08d07968 | 1069 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd | 1070 | rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan); |
08d07968 HC |
1071 | if (rc) |
1072 | return rc; | |
1073 | #endif | |
1074 | for_each_present_cpu(cpu) { | |
1075 | rc = smp_add_present_cpu(cpu); | |
fae8b22d HC |
1076 | if (rc) |
1077 | return rc; | |
1da177e4 LT |
1078 | } |
1079 | return 0; | |
1080 | } | |
83a24e32 | 1081 | subsys_initcall(s390_smp_init); |