[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / sysdev / mpc8xxx_gpio.c

/*
 * GPIOs on MPC8349/8572/8610 and compatible
 *
 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/gpio.h>
#include <linux/slab.h>

#define MPC8XXX_GPIO_PINS	32

#define GPIO_DIR		0x00
#define GPIO_ODR		0x04
#define GPIO_DAT		0x08
#define GPIO_IER		0x0c
#define GPIO_IMR		0x10
#define GPIO_ICR		0x14

struct mpc8xxx_gpio_chip {
	struct of_mm_gpio_chip mm_gc;
	spinlock_t lock;

	/*
	 * shadowed data register to be able to clear/set output pins in
	 * open drain mode safely
	 */
	u32 data;
};

static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
{
	return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
}

static inline struct mpc8xxx_gpio_chip *
to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
{
	return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
}

static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);

	mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
}

/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
 * defined as output cannot be determined by reading GPDAT register,
 * so we use shadow data register instead. The status of input pins
 * is determined by reading GPDAT register.
 */
static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
	u32 val;
	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);

	val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR);

	return (val | mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio);
}

static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);

	return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
}

static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
	unsigned long flags;

	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);

	if (val)
		mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
	else
		mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);

	out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);

	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
}

static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
	unsigned long flags;

	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);

	clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));

	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);

	return 0;
}

static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
	unsigned long flags;

	mpc8xxx_gpio_set(gc, gpio, val);

	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);

	setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));

	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);

	return 0;
}

static void __init mpc8xxx_add_controller(struct device_node *np)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc;
	struct of_mm_gpio_chip *mm_gc;
	struct of_gpio_chip *of_gc;
	struct gpio_chip *gc;
	int ret;

	mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
	if (!mpc8xxx_gc) {
		ret = -ENOMEM;
		goto err;
	}

	spin_lock_init(&mpc8xxx_gc->lock);

	mm_gc = &mpc8xxx_gc->mm_gc;
	of_gc = &mm_gc->of_gc;
	gc = &of_gc->gc;

	mm_gc->save_regs = mpc8xxx_gpio_save_regs;
	of_gc->gpio_cells = 2;
	gc->ngpio = MPC8XXX_GPIO_PINS;
	gc->direction_input = mpc8xxx_gpio_dir_in;
	gc->direction_output = mpc8xxx_gpio_dir_out;
	if (of_device_is_compatible(np, "fsl,mpc8572-gpio"))
		gc->get = mpc8572_gpio_get;
	else
		gc->get = mpc8xxx_gpio_get;
	gc->set = mpc8xxx_gpio_set;

	ret = of_mm_gpiochip_add(np, mm_gc);
	if (ret)
		goto err;

	return;

err:
	pr_err("%s: registration failed with status %d\n",
	       np->full_name, ret);
	kfree(mpc8xxx_gc);

	return;
}

static int __init mpc8xxx_add_gpiochips(void)
{
	struct device_node *np;

	for_each_compatible_node(np, NULL, "fsl,mpc8349-gpio")
		mpc8xxx_add_controller(np);

	for_each_compatible_node(np, NULL, "fsl,mpc8572-gpio")
		mpc8xxx_add_controller(np);

	for_each_compatible_node(np, NULL, "fsl,mpc8610-gpio")
		mpc8xxx_add_controller(np);

	return 0;
}
arch_initcall(mpc8xxx_add_gpiochips);
Commit	Line	Data
1e16dfc1 PK	1	/*
	2	* GPIOs on MPC8349/8572/8610 and compatible
	3	*
	4	* Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of any
	8	* kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/spinlock.h>
	14	#include <linux/io.h>
	15	#include <linux/of.h>
	16	#include <linux/of_gpio.h>
	17	#include <linux/gpio.h>
5a0e3ad6	18	#include <linux/slab.h>
1e16dfc1 PK	19
	20	#define MPC8XXX_GPIO_PINS 32
	21
	22	#define GPIO_DIR 0x00
	23	#define GPIO_ODR 0x04
	24	#define GPIO_DAT 0x08
	25	#define GPIO_IER 0x0c
	26	#define GPIO_IMR 0x10
	27	#define GPIO_ICR 0x14
	28
	29	struct mpc8xxx_gpio_chip {
	30	struct of_mm_gpio_chip mm_gc;
	31	spinlock_t lock;
	32
	33	/*
	34	* shadowed data register to be able to clear/set output pins in
	35	* open drain mode safely
	36	*/
	37	u32 data;
	38	};
	39
	40	static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
	41	{
	42	return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
	43	}
	44
	45	static inline struct mpc8xxx_gpio_chip *
	46	to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
	47	{
	48	return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
	49	}
	50
	51	static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
	52	{
	53	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
	54
	55	mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
	56	}
	57
c1a676df FR	58	/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
	59	* defined as output cannot be determined by reading GPDAT register,
	60	* so we use shadow data register instead. The status of input pins
	61	* is determined by reading GPDAT register.
	62	*/
	63	static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
	64	{
	65	u32 val;
	66	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
	67	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
	68
	69	val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR);
	70
	71	return (val \| mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio);
	72	}
	73
1e16dfc1 PK	74	static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
	75	{
	76	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
	77
	78	return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
	79	}
	80
	81	static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
	82	{
	83	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
	84	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
	85	unsigned long flags;
	86
	87	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
	88
	89	if (val)
	90	mpc8xxx_gc->data \|= mpc8xxx_gpio2mask(gpio);
	91	else
	92	mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
	93
	94	out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
	95
	96	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
	97	}
	98
	99	static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
	100	{
	101	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
	102	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
	103	unsigned long flags;
	104
	105	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
	106
	107	clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
	108
	109	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
	110
	111	return 0;
	112	}
	113
	114	static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
	115	{
	116	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
	117	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
	118	unsigned long flags;
	119
	120	mpc8xxx_gpio_set(gc, gpio, val);
	121
	122	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
	123
	124	setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
	125
	126	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
	127
	128	return 0;
	129	}
	130
	131	static void __init mpc8xxx_add_controller(struct device_node *np)
	132	{
	133	struct mpc8xxx_gpio_chip *mpc8xxx_gc;
	134	struct of_mm_gpio_chip *mm_gc;
	135	struct of_gpio_chip *of_gc;
	136	struct gpio_chip *gc;
	137	int ret;
138
139	mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
140	if (!mpc8xxx_gc) {
141	ret = -ENOMEM;
142	goto err;
143	}
144
145	spin_lock_init(&mpc8xxx_gc->lock);
146
147	mm_gc = &mpc8xxx_gc->mm_gc;
148	of_gc = &mm_gc->of_gc;
149	gc = &of_gc->gc;
150
151	mm_gc->save_regs = mpc8xxx_gpio_save_regs;
152	of_gc->gpio_cells = 2;
153	gc->ngpio = MPC8XXX_GPIO_PINS;
154	gc->direction_input = mpc8xxx_gpio_dir_in;
155	gc->direction_output = mpc8xxx_gpio_dir_out;
c1a676df FR	156	if (of_device_is_compatible(np, "fsl,mpc8572-gpio"))
	157	gc->get = mpc8572_gpio_get;
	158	else
	159	gc->get = mpc8xxx_gpio_get;
1e16dfc1 PK	160	gc->set = mpc8xxx_gpio_set;
	161
	162	ret = of_mm_gpiochip_add(np, mm_gc);
	163	if (ret)
	164	goto err;
	165
	166	return;
	167
	168	err:
	169	pr_err("%s: registration failed with status %d\n",
	170	np->full_name, ret);
	171	kfree(mpc8xxx_gc);
	172
	173	return;
	174	}
	175
	176	static int __init mpc8xxx_add_gpiochips(void)
	177	{
	178	struct device_node *np;
	179
	180	for_each_compatible_node(np, NULL, "fsl,mpc8349-gpio")
	181	mpc8xxx_add_controller(np);
	182
	183	for_each_compatible_node(np, NULL, "fsl,mpc8572-gpio")
	184	mpc8xxx_add_controller(np);
	185
	186	for_each_compatible_node(np, NULL, "fsl,mpc8610-gpio")
	187	mpc8xxx_add_controller(np);
	188
	189	return 0;
	190	}
	191	arch_initcall(mpc8xxx_add_gpiochips);