Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * eeh.c | |
3c8c90ab LV |
3 | * Copyright IBM Corporation 2001, 2005, 2006 |
4 | * Copyright Dave Engebretsen & Todd Inglett 2001 | |
5 | * Copyright Linas Vepstas 2005, 2006 | |
69376502 | 6 | * |
1da177e4 LT |
7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
69376502 | 11 | * |
1da177e4 LT |
12 | * This program is distributed in the hope that it will be useful, |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
69376502 | 16 | * |
1da177e4 LT |
17 | * You should have received a copy of the GNU General Public License |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
3c8c90ab LV |
20 | * |
21 | * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com> | |
1da177e4 LT |
22 | */ |
23 | ||
6dee3fb9 | 24 | #include <linux/delay.h> |
1da177e4 LT |
25 | #include <linux/init.h> |
26 | #include <linux/list.h> | |
1da177e4 LT |
27 | #include <linux/pci.h> |
28 | #include <linux/proc_fs.h> | |
29 | #include <linux/rbtree.h> | |
30 | #include <linux/seq_file.h> | |
31 | #include <linux/spinlock.h> | |
acaa6176 SR |
32 | #include <linux/of.h> |
33 | ||
60063497 | 34 | #include <linux/atomic.h> |
1da177e4 | 35 | #include <asm/eeh.h> |
172ca926 | 36 | #include <asm/eeh_event.h> |
1da177e4 LT |
37 | #include <asm/io.h> |
38 | #include <asm/machdep.h> | |
172ca926 | 39 | #include <asm/ppc-pci.h> |
1da177e4 | 40 | #include <asm/rtas.h> |
1da177e4 | 41 | |
1da177e4 LT |
42 | |
43 | /** Overview: | |
44 | * EEH, or "Extended Error Handling" is a PCI bridge technology for | |
45 | * dealing with PCI bus errors that can't be dealt with within the | |
46 | * usual PCI framework, except by check-stopping the CPU. Systems | |
47 | * that are designed for high-availability/reliability cannot afford | |
48 | * to crash due to a "mere" PCI error, thus the need for EEH. | |
49 | * An EEH-capable bridge operates by converting a detected error | |
50 | * into a "slot freeze", taking the PCI adapter off-line, making | |
51 | * the slot behave, from the OS'es point of view, as if the slot | |
52 | * were "empty": all reads return 0xff's and all writes are silently | |
53 | * ignored. EEH slot isolation events can be triggered by parity | |
54 | * errors on the address or data busses (e.g. during posted writes), | |
69376502 LV |
55 | * which in turn might be caused by low voltage on the bus, dust, |
56 | * vibration, humidity, radioactivity or plain-old failed hardware. | |
1da177e4 LT |
57 | * |
58 | * Note, however, that one of the leading causes of EEH slot | |
59 | * freeze events are buggy device drivers, buggy device microcode, | |
60 | * or buggy device hardware. This is because any attempt by the | |
61 | * device to bus-master data to a memory address that is not | |
62 | * assigned to the device will trigger a slot freeze. (The idea | |
63 | * is to prevent devices-gone-wild from corrupting system memory). | |
64 | * Buggy hardware/drivers will have a miserable time co-existing | |
65 | * with EEH. | |
66 | * | |
67 | * Ideally, a PCI device driver, when suspecting that an isolation | |
25985edc | 68 | * event has occurred (e.g. by reading 0xff's), will then ask EEH |
1da177e4 LT |
69 | * whether this is the case, and then take appropriate steps to |
70 | * reset the PCI slot, the PCI device, and then resume operations. | |
71 | * However, until that day, the checking is done here, with the | |
72 | * eeh_check_failure() routine embedded in the MMIO macros. If | |
73 | * the slot is found to be isolated, an "EEH Event" is synthesized | |
74 | * and sent out for processing. | |
75 | */ | |
76 | ||
5c1344e9 | 77 | /* If a device driver keeps reading an MMIO register in an interrupt |
f36c5227 MM |
78 | * handler after a slot isolation event, it might be broken. |
79 | * This sets the threshold for how many read attempts we allow | |
80 | * before printing an error message. | |
1da177e4 | 81 | */ |
2fd30be8 | 82 | #define EEH_MAX_FAILS 2100000 |
1da177e4 | 83 | |
17213c3b | 84 | /* Time to wait for a PCI slot to report status, in milliseconds */ |
9c547768 LV |
85 | #define PCI_BUS_RESET_WAIT_MSEC (60*1000) |
86 | ||
1da177e4 LT |
87 | /* RTAS tokens */ |
88 | static int ibm_set_eeh_option; | |
89 | static int ibm_set_slot_reset; | |
90 | static int ibm_read_slot_reset_state; | |
91 | static int ibm_read_slot_reset_state2; | |
92 | static int ibm_slot_error_detail; | |
25e591f6 | 93 | static int ibm_get_config_addr_info; |
147d6a37 | 94 | static int ibm_get_config_addr_info2; |
21e464dd | 95 | static int ibm_configure_bridge; |
65f47f13 | 96 | static int ibm_configure_pe; |
1da177e4 | 97 | |
1e28a7dd DW |
98 | int eeh_subsystem_enabled; |
99 | EXPORT_SYMBOL(eeh_subsystem_enabled); | |
1da177e4 | 100 | |
fd761fd8 | 101 | /* Lock to avoid races due to multiple reports of an error */ |
3d372628 | 102 | static DEFINE_RAW_SPINLOCK(confirm_error_lock); |
fd761fd8 | 103 | |
17213c3b LV |
104 | /* Buffer for reporting slot-error-detail rtas calls. Its here |
105 | * in BSS, and not dynamically alloced, so that it ends up in | |
106 | * RMO where RTAS can access it. | |
107 | */ | |
1da177e4 LT |
108 | static unsigned char slot_errbuf[RTAS_ERROR_LOG_MAX]; |
109 | static DEFINE_SPINLOCK(slot_errbuf_lock); | |
110 | static int eeh_error_buf_size; | |
111 | ||
17213c3b LV |
112 | /* Buffer for reporting pci register dumps. Its here in BSS, and |
113 | * not dynamically alloced, so that it ends up in RMO where RTAS | |
114 | * can access it. | |
115 | */ | |
d99bb1db LV |
116 | #define EEH_PCI_REGS_LOG_LEN 4096 |
117 | static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN]; | |
118 | ||
1da177e4 | 119 | /* System monitoring statistics */ |
257ffc64 LV |
120 | static unsigned long no_device; |
121 | static unsigned long no_dn; | |
122 | static unsigned long no_cfg_addr; | |
123 | static unsigned long ignored_check; | |
124 | static unsigned long total_mmio_ffs; | |
125 | static unsigned long false_positives; | |
257ffc64 | 126 | static unsigned long slot_resets; |
1da177e4 | 127 | |
7684b40c LV |
128 | #define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE) |
129 | ||
1da177e4 | 130 | /* --------------------------------------------------------------- */ |
5d5a0936 | 131 | /* Below lies the EEH event infrastructure */ |
1da177e4 | 132 | |
d99bb1db LV |
133 | static void rtas_slot_error_detail(struct pci_dn *pdn, int severity, |
134 | char *driver_log, size_t loglen) | |
df7242b1 | 135 | { |
fcb7543e | 136 | int config_addr; |
df7242b1 LV |
137 | unsigned long flags; |
138 | int rc; | |
139 | ||
140 | /* Log the error with the rtas logger */ | |
141 | spin_lock_irqsave(&slot_errbuf_lock, flags); | |
142 | memset(slot_errbuf, 0, eeh_error_buf_size); | |
143 | ||
fcb7543e LV |
144 | /* Use PE configuration address, if present */ |
145 | config_addr = pdn->eeh_config_addr; | |
146 | if (pdn->eeh_pe_config_addr) | |
147 | config_addr = pdn->eeh_pe_config_addr; | |
148 | ||
df7242b1 | 149 | rc = rtas_call(ibm_slot_error_detail, |
fcb7543e | 150 | 8, 1, NULL, config_addr, |
df7242b1 | 151 | BUID_HI(pdn->phb->buid), |
d99bb1db LV |
152 | BUID_LO(pdn->phb->buid), |
153 | virt_to_phys(driver_log), loglen, | |
df7242b1 LV |
154 | virt_to_phys(slot_errbuf), |
155 | eeh_error_buf_size, | |
156 | severity); | |
157 | ||
158 | if (rc == 0) | |
159 | log_error(slot_errbuf, ERR_TYPE_RTAS_LOG, 0); | |
160 | spin_unlock_irqrestore(&slot_errbuf_lock, flags); | |
161 | } | |
162 | ||
d99bb1db LV |
163 | /** |
164 | * gather_pci_data - copy assorted PCI config space registers to buff | |
165 | * @pdn: device to report data for | |
166 | * @buf: point to buffer in which to log | |
167 | * @len: amount of room in buffer | |
168 | * | |
169 | * This routine captures assorted PCI configuration space data, | |
170 | * and puts them into a buffer for RTAS error logging. | |
171 | */ | |
172 | static size_t gather_pci_data(struct pci_dn *pdn, char * buf, size_t len) | |
173 | { | |
0b9369f4 | 174 | struct pci_dev *dev = pdn->pcidev; |
d99bb1db | 175 | u32 cfg; |
fcf9892b | 176 | int cap, i; |
d99bb1db LV |
177 | int n = 0; |
178 | ||
fcf9892b LV |
179 | n += scnprintf(buf+n, len-n, "%s\n", pdn->node->full_name); |
180 | printk(KERN_WARNING "EEH: of node=%s\n", pdn->node->full_name); | |
181 | ||
d99bb1db | 182 | rtas_read_config(pdn, PCI_VENDOR_ID, 4, &cfg); |
fcf9892b LV |
183 | n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg); |
184 | printk(KERN_WARNING "EEH: PCI device/vendor: %08x\n", cfg); | |
185 | ||
d99bb1db LV |
186 | rtas_read_config(pdn, PCI_COMMAND, 4, &cfg); |
187 | n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg); | |
fcf9892b LV |
188 | printk(KERN_WARNING "EEH: PCI cmd/status register: %08x\n", cfg); |
189 | ||
b37ceefe LV |
190 | if (!dev) { |
191 | printk(KERN_WARNING "EEH: no PCI device for this of node\n"); | |
192 | return n; | |
193 | } | |
194 | ||
0b9369f4 LV |
195 | /* Gather bridge-specific registers */ |
196 | if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) { | |
197 | rtas_read_config(pdn, PCI_SEC_STATUS, 2, &cfg); | |
198 | n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg); | |
199 | printk(KERN_WARNING "EEH: Bridge secondary status: %04x\n", cfg); | |
200 | ||
201 | rtas_read_config(pdn, PCI_BRIDGE_CONTROL, 2, &cfg); | |
202 | n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg); | |
203 | printk(KERN_WARNING "EEH: Bridge control: %04x\n", cfg); | |
204 | } | |
205 | ||
fcf9892b | 206 | /* Dump out the PCI-X command and status regs */ |
b37ceefe | 207 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
fcf9892b LV |
208 | if (cap) { |
209 | rtas_read_config(pdn, cap, 4, &cfg); | |
210 | n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg); | |
211 | printk(KERN_WARNING "EEH: PCI-X cmd: %08x\n", cfg); | |
212 | ||
213 | rtas_read_config(pdn, cap+4, 4, &cfg); | |
214 | n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg); | |
215 | printk(KERN_WARNING "EEH: PCI-X status: %08x\n", cfg); | |
216 | } | |
217 | ||
218 | /* If PCI-E capable, dump PCI-E cap 10, and the AER */ | |
b37ceefe | 219 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); |
fcf9892b LV |
220 | if (cap) { |
221 | n += scnprintf(buf+n, len-n, "pci-e cap10:\n"); | |
222 | printk(KERN_WARNING | |
223 | "EEH: PCI-E capabilities and status follow:\n"); | |
224 | ||
225 | for (i=0; i<=8; i++) { | |
226 | rtas_read_config(pdn, cap+4*i, 4, &cfg); | |
227 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); | |
228 | printk(KERN_WARNING "EEH: PCI-E %02x: %08x\n", i, cfg); | |
229 | } | |
230 | ||
b37ceefe | 231 | cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); |
fcf9892b LV |
232 | if (cap) { |
233 | n += scnprintf(buf+n, len-n, "pci-e AER:\n"); | |
234 | printk(KERN_WARNING | |
235 | "EEH: PCI-E AER capability register set follows:\n"); | |
236 | ||
237 | for (i=0; i<14; i++) { | |
238 | rtas_read_config(pdn, cap+4*i, 4, &cfg); | |
239 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); | |
240 | printk(KERN_WARNING "EEH: PCI-E AER %02x: %08x\n", i, cfg); | |
241 | } | |
242 | } | |
243 | } | |
0b9369f4 LV |
244 | |
245 | /* Gather status on devices under the bridge */ | |
246 | if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) { | |
acaa6176 SR |
247 | struct device_node *dn; |
248 | ||
249 | for_each_child_of_node(pdn->node, dn) { | |
0b9369f4 LV |
250 | pdn = PCI_DN(dn); |
251 | if (pdn) | |
252 | n += gather_pci_data(pdn, buf+n, len-n); | |
0b9369f4 LV |
253 | } |
254 | } | |
255 | ||
d99bb1db LV |
256 | return n; |
257 | } | |
258 | ||
259 | void eeh_slot_error_detail(struct pci_dn *pdn, int severity) | |
260 | { | |
261 | size_t loglen = 0; | |
17213c3b | 262 | pci_regs_buf[0] = 0; |
d99bb1db LV |
263 | |
264 | rtas_pci_enable(pdn, EEH_THAW_MMIO); | |
65f47f13 RL |
265 | rtas_configure_bridge(pdn); |
266 | eeh_restore_bars(pdn); | |
d99bb1db LV |
267 | loglen = gather_pci_data(pdn, pci_regs_buf, EEH_PCI_REGS_LOG_LEN); |
268 | ||
269 | rtas_slot_error_detail(pdn, severity, pci_regs_buf, loglen); | |
270 | } | |
271 | ||
1da177e4 LT |
272 | /** |
273 | * read_slot_reset_state - Read the reset state of a device node's slot | |
274 | * @dn: device node to read | |
275 | * @rets: array to return results in | |
276 | */ | |
69376502 | 277 | static int read_slot_reset_state(struct pci_dn *pdn, int rets[]) |
1da177e4 LT |
278 | { |
279 | int token, outputs; | |
fcb7543e | 280 | int config_addr; |
1da177e4 LT |
281 | |
282 | if (ibm_read_slot_reset_state2 != RTAS_UNKNOWN_SERVICE) { | |
283 | token = ibm_read_slot_reset_state2; | |
284 | outputs = 4; | |
285 | } else { | |
286 | token = ibm_read_slot_reset_state; | |
69376502 | 287 | rets[2] = 0; /* fake PE Unavailable info */ |
1da177e4 LT |
288 | outputs = 3; |
289 | } | |
290 | ||
fcb7543e LV |
291 | /* Use PE configuration address, if present */ |
292 | config_addr = pdn->eeh_config_addr; | |
293 | if (pdn->eeh_pe_config_addr) | |
294 | config_addr = pdn->eeh_pe_config_addr; | |
295 | ||
296 | return rtas_call(token, 3, outputs, rets, config_addr, | |
1635317f | 297 | BUID_HI(pdn->phb->buid), BUID_LO(pdn->phb->buid)); |
1da177e4 LT |
298 | } |
299 | ||
9c547768 LV |
300 | /** |
301 | * eeh_wait_for_slot_status - returns error status of slot | |
302 | * @pdn pci device node | |
303 | * @max_wait_msecs maximum number to millisecs to wait | |
304 | * | |
305 | * Return negative value if a permanent error, else return | |
306 | * Partition Endpoint (PE) status value. | |
307 | * | |
308 | * If @max_wait_msecs is positive, then this routine will | |
309 | * sleep until a valid status can be obtained, or until | |
310 | * the max allowed wait time is exceeded, in which case | |
311 | * a -2 is returned. | |
312 | */ | |
313 | int | |
314 | eeh_wait_for_slot_status(struct pci_dn *pdn, int max_wait_msecs) | |
315 | { | |
316 | int rc; | |
317 | int rets[3]; | |
318 | int mwait; | |
319 | ||
320 | while (1) { | |
321 | rc = read_slot_reset_state(pdn, rets); | |
322 | if (rc) return rc; | |
323 | if (rets[1] == 0) return -1; /* EEH is not supported */ | |
324 | ||
325 | if (rets[0] != 5) return rets[0]; /* return actual status */ | |
326 | ||
327 | if (rets[2] == 0) return -1; /* permanently unavailable */ | |
328 | ||
2c84b407 | 329 | if (max_wait_msecs <= 0) break; |
9c547768 LV |
330 | |
331 | mwait = rets[2]; | |
332 | if (mwait <= 0) { | |
333 | printk (KERN_WARNING | |
334 | "EEH: Firmware returned bad wait value=%d\n", mwait); | |
335 | mwait = 1000; | |
336 | } else if (mwait > 300*1000) { | |
337 | printk (KERN_WARNING | |
338 | "EEH: Firmware is taking too long, time=%d\n", mwait); | |
339 | mwait = 300*1000; | |
340 | } | |
341 | max_wait_msecs -= mwait; | |
342 | msleep (mwait); | |
343 | } | |
344 | ||
345 | printk(KERN_WARNING "EEH: Timed out waiting for slot status\n"); | |
346 | return -2; | |
347 | } | |
348 | ||
1da177e4 LT |
349 | /** |
350 | * eeh_token_to_phys - convert EEH address token to phys address | |
69376502 | 351 | * @token i/o token, should be address in the form 0xA.... |
1da177e4 LT |
352 | */ |
353 | static inline unsigned long eeh_token_to_phys(unsigned long token) | |
354 | { | |
355 | pte_t *ptep; | |
356 | unsigned long pa; | |
357 | ||
20cee16c | 358 | ptep = find_linux_pte(init_mm.pgd, token); |
1da177e4 LT |
359 | if (!ptep) |
360 | return token; | |
361 | pa = pte_pfn(*ptep) << PAGE_SHIFT; | |
362 | ||
363 | return pa | (token & (PAGE_SIZE-1)); | |
364 | } | |
365 | ||
fd761fd8 LV |
366 | /** |
367 | * Return the "partitionable endpoint" (pe) under which this device lies | |
368 | */ | |
9fb40eb8 | 369 | struct device_node * find_device_pe(struct device_node *dn) |
fd761fd8 LV |
370 | { |
371 | while ((dn->parent) && PCI_DN(dn->parent) && | |
372 | (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) { | |
373 | dn = dn->parent; | |
374 | } | |
375 | return dn; | |
376 | } | |
377 | ||
acaa6176 | 378 | /** Mark all devices that are children of this device as failed. |
fd761fd8 LV |
379 | * Mark the device driver too, so that it can see the failure |
380 | * immediately; this is critical, since some drivers poll | |
381 | * status registers in interrupts ... If a driver is polling, | |
382 | * and the slot is frozen, then the driver can deadlock in | |
383 | * an interrupt context, which is bad. | |
384 | */ | |
385 | ||
acaa6176 | 386 | static void __eeh_mark_slot(struct device_node *parent, int mode_flag) |
fd761fd8 | 387 | { |
acaa6176 SR |
388 | struct device_node *dn; |
389 | ||
390 | for_each_child_of_node(parent, dn) { | |
d9564ad1 | 391 | if (PCI_DN(dn)) { |
77bd7415 LV |
392 | /* Mark the pci device driver too */ |
393 | struct pci_dev *dev = PCI_DN(dn)->pcidev; | |
ea183a95 OJ |
394 | |
395 | PCI_DN(dn)->eeh_mode |= mode_flag; | |
396 | ||
77bd7415 LV |
397 | if (dev && dev->driver) |
398 | dev->error_state = pci_channel_io_frozen; | |
399 | ||
acaa6176 | 400 | __eeh_mark_slot(dn, mode_flag); |
d9564ad1 | 401 | } |
fd761fd8 LV |
402 | } |
403 | } | |
404 | ||
d9564ad1 LV |
405 | void eeh_mark_slot (struct device_node *dn, int mode_flag) |
406 | { | |
022d51b1 | 407 | struct pci_dev *dev; |
d9564ad1 | 408 | dn = find_device_pe (dn); |
3914ac7b LV |
409 | |
410 | /* Back up one, since config addrs might be shared */ | |
4980d5eb | 411 | if (!pcibios_find_pci_bus(dn) && PCI_DN(dn->parent)) |
3914ac7b LV |
412 | dn = dn->parent; |
413 | ||
d9564ad1 | 414 | PCI_DN(dn)->eeh_mode |= mode_flag; |
022d51b1 LV |
415 | |
416 | /* Mark the pci device too */ | |
417 | dev = PCI_DN(dn)->pcidev; | |
418 | if (dev) | |
419 | dev->error_state = pci_channel_io_frozen; | |
420 | ||
acaa6176 | 421 | __eeh_mark_slot(dn, mode_flag); |
d9564ad1 LV |
422 | } |
423 | ||
acaa6176 | 424 | static void __eeh_clear_slot(struct device_node *parent, int mode_flag) |
fd761fd8 | 425 | { |
acaa6176 SR |
426 | struct device_node *dn; |
427 | ||
428 | for_each_child_of_node(parent, dn) { | |
d9564ad1 LV |
429 | if (PCI_DN(dn)) { |
430 | PCI_DN(dn)->eeh_mode &= ~mode_flag; | |
431 | PCI_DN(dn)->eeh_check_count = 0; | |
acaa6176 | 432 | __eeh_clear_slot(dn, mode_flag); |
d9564ad1 | 433 | } |
fd761fd8 LV |
434 | } |
435 | } | |
436 | ||
d9564ad1 | 437 | void eeh_clear_slot (struct device_node *dn, int mode_flag) |
fd761fd8 LV |
438 | { |
439 | unsigned long flags; | |
3d372628 | 440 | raw_spin_lock_irqsave(&confirm_error_lock, flags); |
3914ac7b | 441 | |
d9564ad1 | 442 | dn = find_device_pe (dn); |
3914ac7b LV |
443 | |
444 | /* Back up one, since config addrs might be shared */ | |
4980d5eb | 445 | if (!pcibios_find_pci_bus(dn) && PCI_DN(dn->parent)) |
3914ac7b LV |
446 | dn = dn->parent; |
447 | ||
d9564ad1 LV |
448 | PCI_DN(dn)->eeh_mode &= ~mode_flag; |
449 | PCI_DN(dn)->eeh_check_count = 0; | |
acaa6176 | 450 | __eeh_clear_slot(dn, mode_flag); |
3d372628 | 451 | raw_spin_unlock_irqrestore(&confirm_error_lock, flags); |
fd761fd8 LV |
452 | } |
453 | ||
308fc4f8 RL |
454 | void __eeh_set_pe_freset(struct device_node *parent, unsigned int *freset) |
455 | { | |
456 | struct device_node *dn; | |
457 | ||
458 | for_each_child_of_node(parent, dn) { | |
459 | if (PCI_DN(dn)) { | |
460 | ||
461 | struct pci_dev *dev = PCI_DN(dn)->pcidev; | |
462 | ||
463 | if (dev && dev->driver) | |
464 | *freset |= dev->needs_freset; | |
465 | ||
466 | __eeh_set_pe_freset(dn, freset); | |
467 | } | |
468 | } | |
469 | } | |
470 | ||
471 | void eeh_set_pe_freset(struct device_node *dn, unsigned int *freset) | |
472 | { | |
473 | struct pci_dev *dev; | |
474 | dn = find_device_pe(dn); | |
475 | ||
476 | /* Back up one, since config addrs might be shared */ | |
477 | if (!pcibios_find_pci_bus(dn) && PCI_DN(dn->parent)) | |
478 | dn = dn->parent; | |
479 | ||
480 | dev = PCI_DN(dn)->pcidev; | |
481 | if (dev) | |
482 | *freset |= dev->needs_freset; | |
483 | ||
484 | __eeh_set_pe_freset(dn, freset); | |
485 | } | |
486 | ||
1da177e4 LT |
487 | /** |
488 | * eeh_dn_check_failure - check if all 1's data is due to EEH slot freeze | |
489 | * @dn device node | |
490 | * @dev pci device, if known | |
491 | * | |
492 | * Check for an EEH failure for the given device node. Call this | |
493 | * routine if the result of a read was all 0xff's and you want to | |
494 | * find out if this is due to an EEH slot freeze. This routine | |
495 | * will query firmware for the EEH status. | |
496 | * | |
497 | * Returns 0 if there has not been an EEH error; otherwise returns | |
69376502 | 498 | * a non-zero value and queues up a slot isolation event notification. |
1da177e4 LT |
499 | * |
500 | * It is safe to call this routine in an interrupt context. | |
501 | */ | |
502 | int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev) | |
503 | { | |
504 | int ret; | |
505 | int rets[3]; | |
506 | unsigned long flags; | |
1635317f | 507 | struct pci_dn *pdn; |
fd761fd8 | 508 | int rc = 0; |
f36c5227 | 509 | const char *location; |
1da177e4 | 510 | |
257ffc64 | 511 | total_mmio_ffs++; |
1da177e4 LT |
512 | |
513 | if (!eeh_subsystem_enabled) | |
514 | return 0; | |
515 | ||
177bc936 | 516 | if (!dn) { |
257ffc64 | 517 | no_dn++; |
1da177e4 | 518 | return 0; |
177bc936 | 519 | } |
307d46e8 | 520 | dn = find_device_pe(dn); |
69376502 | 521 | pdn = PCI_DN(dn); |
1da177e4 LT |
522 | |
523 | /* Access to IO BARs might get this far and still not want checking. */ | |
f8632c82 | 524 | if (!(pdn->eeh_mode & EEH_MODE_SUPPORTED) || |
1635317f | 525 | pdn->eeh_mode & EEH_MODE_NOCHECK) { |
257ffc64 | 526 | ignored_check++; |
57b066ff | 527 | pr_debug("EEH: Ignored check (%x) for %s %s\n", |
8d3d50bf | 528 | pdn->eeh_mode, eeh_pci_name(dev), dn->full_name); |
1da177e4 LT |
529 | return 0; |
530 | } | |
531 | ||
fcb7543e | 532 | if (!pdn->eeh_config_addr && !pdn->eeh_pe_config_addr) { |
257ffc64 | 533 | no_cfg_addr++; |
1da177e4 LT |
534 | return 0; |
535 | } | |
536 | ||
fd761fd8 LV |
537 | /* If we already have a pending isolation event for this |
538 | * slot, we know it's bad already, we don't need to check. | |
539 | * Do this checking under a lock; as multiple PCI devices | |
540 | * in one slot might report errors simultaneously, and we | |
541 | * only want one error recovery routine running. | |
1da177e4 | 542 | */ |
3d372628 | 543 | raw_spin_lock_irqsave(&confirm_error_lock, flags); |
fd761fd8 | 544 | rc = 1; |
1635317f | 545 | if (pdn->eeh_mode & EEH_MODE_ISOLATED) { |
5c1344e9 | 546 | pdn->eeh_check_count ++; |
f36c5227 MM |
547 | if (pdn->eeh_check_count % EEH_MAX_FAILS == 0) { |
548 | location = of_get_property(dn, "ibm,loc-code", NULL); | |
549 | printk (KERN_ERR "EEH: %d reads ignored for recovering device at " | |
550 | "location=%s driver=%s pci addr=%s\n", | |
551 | pdn->eeh_check_count, location, | |
8d3d50bf | 552 | dev->driver->name, eeh_pci_name(dev)); |
f36c5227 MM |
553 | printk (KERN_ERR "EEH: Might be infinite loop in %s driver\n", |
554 | dev->driver->name); | |
5c1344e9 | 555 | dump_stack(); |
1da177e4 | 556 | } |
fd761fd8 | 557 | goto dn_unlock; |
1da177e4 LT |
558 | } |
559 | ||
560 | /* | |
561 | * Now test for an EEH failure. This is VERY expensive. | |
562 | * Note that the eeh_config_addr may be a parent device | |
563 | * in the case of a device behind a bridge, or it may be | |
564 | * function zero of a multi-function device. | |
565 | * In any case they must share a common PHB. | |
566 | */ | |
69376502 | 567 | ret = read_slot_reset_state(pdn, rets); |
76e6faf7 LV |
568 | |
569 | /* If the call to firmware failed, punt */ | |
570 | if (ret != 0) { | |
571 | printk(KERN_WARNING "EEH: read_slot_reset_state() failed; rc=%d dn=%s\n", | |
572 | ret, dn->full_name); | |
257ffc64 | 573 | false_positives++; |
858955bd | 574 | pdn->eeh_false_positives ++; |
fd761fd8 LV |
575 | rc = 0; |
576 | goto dn_unlock; | |
76e6faf7 LV |
577 | } |
578 | ||
39d16e29 LV |
579 | /* Note that config-io to empty slots may fail; |
580 | * they are empty when they don't have children. */ | |
c9b65a7d | 581 | if ((rets[0] == 5) && (rets[2] == 0) && (dn->child == NULL)) { |
39d16e29 | 582 | false_positives++; |
858955bd | 583 | pdn->eeh_false_positives ++; |
39d16e29 LV |
584 | rc = 0; |
585 | goto dn_unlock; | |
586 | } | |
587 | ||
76e6faf7 LV |
588 | /* If EEH is not supported on this device, punt. */ |
589 | if (rets[1] != 1) { | |
590 | printk(KERN_WARNING "EEH: event on unsupported device, rc=%d dn=%s\n", | |
591 | ret, dn->full_name); | |
257ffc64 | 592 | false_positives++; |
858955bd | 593 | pdn->eeh_false_positives ++; |
fd761fd8 LV |
594 | rc = 0; |
595 | goto dn_unlock; | |
76e6faf7 LV |
596 | } |
597 | ||
598 | /* If not the kind of error we know about, punt. */ | |
90375f53 | 599 | if (rets[0] != 1 && rets[0] != 2 && rets[0] != 4 && rets[0] != 5) { |
257ffc64 | 600 | false_positives++; |
858955bd | 601 | pdn->eeh_false_positives ++; |
fd761fd8 LV |
602 | rc = 0; |
603 | goto dn_unlock; | |
76e6faf7 LV |
604 | } |
605 | ||
257ffc64 | 606 | slot_resets++; |
fd761fd8 LV |
607 | |
608 | /* Avoid repeated reports of this failure, including problems | |
609 | * with other functions on this device, and functions under | |
610 | * bridges. */ | |
d9564ad1 | 611 | eeh_mark_slot (dn, EEH_MODE_ISOLATED); |
3d372628 | 612 | raw_spin_unlock_irqrestore(&confirm_error_lock, flags); |
1da177e4 | 613 | |
d0ab95ca | 614 | eeh_send_failure_event (dn, dev); |
77bd7415 | 615 | |
1da177e4 LT |
616 | /* Most EEH events are due to device driver bugs. Having |
617 | * a stack trace will help the device-driver authors figure | |
618 | * out what happened. So print that out. */ | |
90375f53 | 619 | dump_stack(); |
fd761fd8 LV |
620 | return 1; |
621 | ||
622 | dn_unlock: | |
3d372628 | 623 | raw_spin_unlock_irqrestore(&confirm_error_lock, flags); |
fd761fd8 | 624 | return rc; |
1da177e4 LT |
625 | } |
626 | ||
fd761fd8 | 627 | EXPORT_SYMBOL_GPL(eeh_dn_check_failure); |
1da177e4 LT |
628 | |
629 | /** | |
630 | * eeh_check_failure - check if all 1's data is due to EEH slot freeze | |
631 | * @token i/o token, should be address in the form 0xA.... | |
632 | * @val value, should be all 1's (XXX why do we need this arg??) | |
633 | * | |
1da177e4 LT |
634 | * Check for an EEH failure at the given token address. Call this |
635 | * routine if the result of a read was all 0xff's and you want to | |
636 | * find out if this is due to an EEH slot freeze event. This routine | |
637 | * will query firmware for the EEH status. | |
638 | * | |
639 | * Note this routine is safe to call in an interrupt context. | |
640 | */ | |
641 | unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val) | |
642 | { | |
643 | unsigned long addr; | |
644 | struct pci_dev *dev; | |
645 | struct device_node *dn; | |
646 | ||
647 | /* Finding the phys addr + pci device; this is pretty quick. */ | |
648 | addr = eeh_token_to_phys((unsigned long __force) token); | |
649 | dev = pci_get_device_by_addr(addr); | |
177bc936 | 650 | if (!dev) { |
257ffc64 | 651 | no_device++; |
1da177e4 | 652 | return val; |
177bc936 | 653 | } |
1da177e4 LT |
654 | |
655 | dn = pci_device_to_OF_node(dev); | |
656 | eeh_dn_check_failure (dn, dev); | |
657 | ||
658 | pci_dev_put(dev); | |
659 | return val; | |
660 | } | |
661 | ||
662 | EXPORT_SYMBOL(eeh_check_failure); | |
663 | ||
6dee3fb9 LV |
664 | /* ------------------------------------------------------------- */ |
665 | /* The code below deals with error recovery */ | |
666 | ||
47b5c838 LV |
667 | /** |
668 | * rtas_pci_enable - enable MMIO or DMA transfers for this slot | |
669 | * @pdn pci device node | |
670 | */ | |
671 | ||
672 | int | |
673 | rtas_pci_enable(struct pci_dn *pdn, int function) | |
674 | { | |
675 | int config_addr; | |
676 | int rc; | |
677 | ||
678 | /* Use PE configuration address, if present */ | |
679 | config_addr = pdn->eeh_config_addr; | |
680 | if (pdn->eeh_pe_config_addr) | |
681 | config_addr = pdn->eeh_pe_config_addr; | |
682 | ||
683 | rc = rtas_call(ibm_set_eeh_option, 4, 1, NULL, | |
684 | config_addr, | |
685 | BUID_HI(pdn->phb->buid), | |
686 | BUID_LO(pdn->phb->buid), | |
687 | function); | |
688 | ||
689 | if (rc) | |
fa1be476 | 690 | printk(KERN_WARNING "EEH: Unexpected state change %d, err=%d dn=%s\n", |
47b5c838 LV |
691 | function, rc, pdn->node->full_name); |
692 | ||
fa1be476 LV |
693 | rc = eeh_wait_for_slot_status (pdn, PCI_BUS_RESET_WAIT_MSEC); |
694 | if ((rc == 4) && (function == EEH_THAW_MMIO)) | |
695 | return 0; | |
696 | ||
47b5c838 LV |
697 | return rc; |
698 | } | |
699 | ||
cb5b5624 LV |
700 | /** |
701 | * rtas_pci_slot_reset - raises/lowers the pci #RST line | |
702 | * @pdn pci device node | |
703 | * @state: 1/0 to raise/lower the #RST | |
6dee3fb9 LV |
704 | * |
705 | * Clear the EEH-frozen condition on a slot. This routine | |
706 | * asserts the PCI #RST line if the 'state' argument is '1', | |
707 | * and drops the #RST line if 'state is '0'. This routine is | |
708 | * safe to call in an interrupt context. | |
709 | * | |
710 | */ | |
711 | ||
712 | static void | |
713 | rtas_pci_slot_reset(struct pci_dn *pdn, int state) | |
714 | { | |
25e591f6 | 715 | int config_addr; |
6dee3fb9 LV |
716 | int rc; |
717 | ||
718 | BUG_ON (pdn==NULL); | |
719 | ||
720 | if (!pdn->phb) { | |
721 | printk (KERN_WARNING "EEH: in slot reset, device node %s has no phb\n", | |
722 | pdn->node->full_name); | |
723 | return; | |
724 | } | |
725 | ||
25e591f6 LV |
726 | /* Use PE configuration address, if present */ |
727 | config_addr = pdn->eeh_config_addr; | |
728 | if (pdn->eeh_pe_config_addr) | |
729 | config_addr = pdn->eeh_pe_config_addr; | |
730 | ||
ecb73902 | 731 | rc = rtas_call(ibm_set_slot_reset, 4, 1, NULL, |
25e591f6 | 732 | config_addr, |
6dee3fb9 LV |
733 | BUID_HI(pdn->phb->buid), |
734 | BUID_LO(pdn->phb->buid), | |
735 | state); | |
ecb73902 RL |
736 | |
737 | /* Fundamental-reset not supported on this PE, try hot-reset */ | |
738 | if (rc == -8 && state == 3) { | |
739 | rc = rtas_call(ibm_set_slot_reset, 4, 1, NULL, | |
740 | config_addr, | |
741 | BUID_HI(pdn->phb->buid), | |
742 | BUID_LO(pdn->phb->buid), 1); | |
743 | if (rc) | |
744 | printk(KERN_WARNING | |
745 | "EEH: Unable to reset the failed slot," | |
746 | " #RST=%d dn=%s\n", | |
747 | rc, pdn->node->full_name); | |
748 | } | |
6dee3fb9 LV |
749 | } |
750 | ||
00c2ae35 BK |
751 | /** |
752 | * pcibios_set_pcie_slot_reset - Set PCI-E reset state | |
753 | * @dev: pci device struct | |
754 | * @state: reset state to enter | |
755 | * | |
756 | * Return value: | |
757 | * 0 if success | |
758 | **/ | |
759 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
760 | { | |
761 | struct device_node *dn = pci_device_to_OF_node(dev); | |
762 | struct pci_dn *pdn = PCI_DN(dn); | |
763 | ||
764 | switch (state) { | |
765 | case pcie_deassert_reset: | |
766 | rtas_pci_slot_reset(pdn, 0); | |
767 | break; | |
768 | case pcie_hot_reset: | |
769 | rtas_pci_slot_reset(pdn, 1); | |
770 | break; | |
771 | case pcie_warm_reset: | |
772 | rtas_pci_slot_reset(pdn, 3); | |
773 | break; | |
774 | default: | |
775 | return -EINVAL; | |
776 | }; | |
777 | ||
778 | return 0; | |
779 | } | |
780 | ||
cb5b5624 LV |
781 | /** |
782 | * rtas_set_slot_reset -- assert the pci #RST line for 1/4 second | |
783 | * @pdn: pci device node to be reset. | |
6dee3fb9 LV |
784 | */ |
785 | ||
e1029263 | 786 | static void __rtas_set_slot_reset(struct pci_dn *pdn) |
6dee3fb9 | 787 | { |
308fc4f8 | 788 | unsigned int freset = 0; |
6e19314c | 789 | |
308fc4f8 RL |
790 | /* Determine type of EEH reset required for |
791 | * Partitionable Endpoint, a hot-reset (1) | |
792 | * or a fundamental reset (3). | |
793 | * A fundamental reset required by any device under | |
794 | * Partitionable Endpoint trumps hot-reset. | |
795 | */ | |
796 | eeh_set_pe_freset(pdn->node, &freset); | |
797 | ||
798 | if (freset) | |
6e19314c MM |
799 | rtas_pci_slot_reset(pdn, 3); |
800 | else | |
801 | rtas_pci_slot_reset(pdn, 1); | |
6dee3fb9 LV |
802 | |
803 | /* The PCI bus requires that the reset be held high for at least | |
804 | * a 100 milliseconds. We wait a bit longer 'just in case'. */ | |
805 | ||
806 | #define PCI_BUS_RST_HOLD_TIME_MSEC 250 | |
807 | msleep (PCI_BUS_RST_HOLD_TIME_MSEC); | |
d9564ad1 LV |
808 | |
809 | /* We might get hit with another EEH freeze as soon as the | |
810 | * pci slot reset line is dropped. Make sure we don't miss | |
811 | * these, and clear the flag now. */ | |
812 | eeh_clear_slot (pdn->node, EEH_MODE_ISOLATED); | |
813 | ||
6dee3fb9 LV |
814 | rtas_pci_slot_reset (pdn, 0); |
815 | ||
816 | /* After a PCI slot has been reset, the PCI Express spec requires | |
817 | * a 1.5 second idle time for the bus to stabilize, before starting | |
818 | * up traffic. */ | |
819 | #define PCI_BUS_SETTLE_TIME_MSEC 1800 | |
820 | msleep (PCI_BUS_SETTLE_TIME_MSEC); | |
e1029263 LV |
821 | } |
822 | ||
823 | int rtas_set_slot_reset(struct pci_dn *pdn) | |
824 | { | |
825 | int i, rc; | |
826 | ||
9c547768 LV |
827 | /* Take three shots at resetting the bus */ |
828 | for (i=0; i<3; i++) { | |
829 | __rtas_set_slot_reset(pdn); | |
6dee3fb9 | 830 | |
9c547768 | 831 | rc = eeh_wait_for_slot_status(pdn, PCI_BUS_RESET_WAIT_MSEC); |
b6495c0c LV |
832 | if (rc == 0) |
833 | return 0; | |
e1029263 | 834 | |
e1029263 | 835 | if (rc < 0) { |
12588da7 LV |
836 | printk(KERN_ERR "EEH: unrecoverable slot failure %s\n", |
837 | pdn->node->full_name); | |
b6495c0c | 838 | return -1; |
e1029263 | 839 | } |
12588da7 LV |
840 | printk(KERN_ERR "EEH: bus reset %d failed on slot %s, rc=%d\n", |
841 | i+1, pdn->node->full_name, rc); | |
6dee3fb9 | 842 | } |
b6495c0c | 843 | |
9c547768 | 844 | return -1; |
6dee3fb9 LV |
845 | } |
846 | ||
8b553f32 LV |
847 | /* ------------------------------------------------------- */ |
848 | /** Save and restore of PCI BARs | |
849 | * | |
850 | * Although firmware will set up BARs during boot, it doesn't | |
851 | * set up device BAR's after a device reset, although it will, | |
852 | * if requested, set up bridge configuration. Thus, we need to | |
853 | * configure the PCI devices ourselves. | |
854 | */ | |
855 | ||
856 | /** | |
857 | * __restore_bars - Restore the Base Address Registers | |
cb5b5624 LV |
858 | * @pdn: pci device node |
859 | * | |
8b553f32 LV |
860 | * Loads the PCI configuration space base address registers, |
861 | * the expansion ROM base address, the latency timer, and etc. | |
862 | * from the saved values in the device node. | |
863 | */ | |
864 | static inline void __restore_bars (struct pci_dn *pdn) | |
865 | { | |
866 | int i; | |
cde274c0 | 867 | u32 cmd; |
8b553f32 LV |
868 | |
869 | if (NULL==pdn->phb) return; | |
870 | for (i=4; i<10; i++) { | |
871 | rtas_write_config(pdn, i*4, 4, pdn->config_space[i]); | |
872 | } | |
873 | ||
874 | /* 12 == Expansion ROM Address */ | |
875 | rtas_write_config(pdn, 12*4, 4, pdn->config_space[12]); | |
876 | ||
877 | #define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF)) | |
878 | #define SAVED_BYTE(OFF) (((u8 *)(pdn->config_space))[BYTE_SWAP(OFF)]) | |
879 | ||
880 | rtas_write_config (pdn, PCI_CACHE_LINE_SIZE, 1, | |
881 | SAVED_BYTE(PCI_CACHE_LINE_SIZE)); | |
882 | ||
883 | rtas_write_config (pdn, PCI_LATENCY_TIMER, 1, | |
884 | SAVED_BYTE(PCI_LATENCY_TIMER)); | |
885 | ||
886 | /* max latency, min grant, interrupt pin and line */ | |
887 | rtas_write_config(pdn, 15*4, 4, pdn->config_space[15]); | |
cde274c0 MM |
888 | |
889 | /* Restore PERR & SERR bits, some devices require it, | |
890 | don't touch the other command bits */ | |
891 | rtas_read_config(pdn, PCI_COMMAND, 4, &cmd); | |
892 | if (pdn->config_space[1] & PCI_COMMAND_PARITY) | |
893 | cmd |= PCI_COMMAND_PARITY; | |
894 | else | |
895 | cmd &= ~PCI_COMMAND_PARITY; | |
896 | if (pdn->config_space[1] & PCI_COMMAND_SERR) | |
897 | cmd |= PCI_COMMAND_SERR; | |
898 | else | |
899 | cmd &= ~PCI_COMMAND_SERR; | |
900 | rtas_write_config(pdn, PCI_COMMAND, 4, cmd); | |
8b553f32 LV |
901 | } |
902 | ||
903 | /** | |
904 | * eeh_restore_bars - restore the PCI config space info | |
905 | * | |
906 | * This routine performs a recursive walk to the children | |
907 | * of this device as well. | |
908 | */ | |
909 | void eeh_restore_bars(struct pci_dn *pdn) | |
910 | { | |
911 | struct device_node *dn; | |
912 | if (!pdn) | |
913 | return; | |
914 | ||
7684b40c | 915 | if ((pdn->eeh_mode & EEH_MODE_SUPPORTED) && !IS_BRIDGE(pdn->class_code)) |
8b553f32 LV |
916 | __restore_bars (pdn); |
917 | ||
acaa6176 | 918 | for_each_child_of_node(pdn->node, dn) |
8b553f32 | 919 | eeh_restore_bars (PCI_DN(dn)); |
8b553f32 LV |
920 | } |
921 | ||
922 | /** | |
923 | * eeh_save_bars - save device bars | |
924 | * | |
925 | * Save the values of the device bars. Unlike the restore | |
926 | * routine, this routine is *not* recursive. This is because | |
31116f0b | 927 | * PCI devices are added individually; but, for the restore, |
8b553f32 LV |
928 | * an entire slot is reset at a time. |
929 | */ | |
7684b40c | 930 | static void eeh_save_bars(struct pci_dn *pdn) |
8b553f32 LV |
931 | { |
932 | int i; | |
933 | ||
7684b40c | 934 | if (!pdn ) |
8b553f32 LV |
935 | return; |
936 | ||
937 | for (i = 0; i < 16; i++) | |
7684b40c | 938 | rtas_read_config(pdn, i * 4, 4, &pdn->config_space[i]); |
8b553f32 LV |
939 | } |
940 | ||
941 | void | |
942 | rtas_configure_bridge(struct pci_dn *pdn) | |
943 | { | |
fcb7543e | 944 | int config_addr; |
8b553f32 | 945 | int rc; |
65f47f13 | 946 | int token; |
8b553f32 | 947 | |
fcb7543e LV |
948 | /* Use PE configuration address, if present */ |
949 | config_addr = pdn->eeh_config_addr; | |
950 | if (pdn->eeh_pe_config_addr) | |
951 | config_addr = pdn->eeh_pe_config_addr; | |
952 | ||
65f47f13 RL |
953 | /* Use new configure-pe function, if supported */ |
954 | if (ibm_configure_pe != RTAS_UNKNOWN_SERVICE) | |
955 | token = ibm_configure_pe; | |
956 | else | |
957 | token = ibm_configure_bridge; | |
958 | ||
959 | rc = rtas_call(token, 3, 1, NULL, | |
fcb7543e | 960 | config_addr, |
8b553f32 LV |
961 | BUID_HI(pdn->phb->buid), |
962 | BUID_LO(pdn->phb->buid)); | |
963 | if (rc) { | |
964 | printk (KERN_WARNING "EEH: Unable to configure device bridge (%d) for %s\n", | |
965 | rc, pdn->node->full_name); | |
966 | } | |
967 | } | |
968 | ||
172ca926 LV |
969 | /* ------------------------------------------------------------- */ |
970 | /* The code below deals with enabling EEH for devices during the | |
971 | * early boot sequence. EEH must be enabled before any PCI probing | |
972 | * can be done. | |
973 | */ | |
974 | ||
975 | #define EEH_ENABLE 1 | |
976 | ||
1da177e4 LT |
977 | struct eeh_early_enable_info { |
978 | unsigned int buid_hi; | |
979 | unsigned int buid_lo; | |
980 | }; | |
981 | ||
147d6a37 LV |
982 | static int get_pe_addr (int config_addr, |
983 | struct eeh_early_enable_info *info) | |
984 | { | |
985 | unsigned int rets[3]; | |
986 | int ret; | |
987 | ||
988 | /* Use latest config-addr token on power6 */ | |
989 | if (ibm_get_config_addr_info2 != RTAS_UNKNOWN_SERVICE) { | |
990 | /* Make sure we have a PE in hand */ | |
991 | ret = rtas_call (ibm_get_config_addr_info2, 4, 2, rets, | |
992 | config_addr, info->buid_hi, info->buid_lo, 1); | |
993 | if (ret || (rets[0]==0)) | |
994 | return 0; | |
995 | ||
996 | ret = rtas_call (ibm_get_config_addr_info2, 4, 2, rets, | |
997 | config_addr, info->buid_hi, info->buid_lo, 0); | |
998 | if (ret) | |
999 | return 0; | |
1000 | return rets[0]; | |
1001 | } | |
1002 | ||
1003 | /* Use older config-addr token on power5 */ | |
1004 | if (ibm_get_config_addr_info != RTAS_UNKNOWN_SERVICE) { | |
1005 | ret = rtas_call (ibm_get_config_addr_info, 4, 2, rets, | |
1006 | config_addr, info->buid_hi, info->buid_lo, 0); | |
1007 | if (ret) | |
1008 | return 0; | |
1009 | return rets[0]; | |
1010 | } | |
1011 | return 0; | |
1012 | } | |
1013 | ||
1da177e4 LT |
1014 | /* Enable eeh for the given device node. */ |
1015 | static void *early_enable_eeh(struct device_node *dn, void *data) | |
1016 | { | |
25c4a46f | 1017 | unsigned int rets[3]; |
1da177e4 LT |
1018 | struct eeh_early_enable_info *info = data; |
1019 | int ret; | |
e2eb6392 SR |
1020 | const u32 *class_code = of_get_property(dn, "class-code", NULL); |
1021 | const u32 *vendor_id = of_get_property(dn, "vendor-id", NULL); | |
1022 | const u32 *device_id = of_get_property(dn, "device-id", NULL); | |
954a46e2 | 1023 | const u32 *regs; |
1da177e4 | 1024 | int enable; |
69376502 | 1025 | struct pci_dn *pdn = PCI_DN(dn); |
1da177e4 | 1026 | |
0f17574a | 1027 | pdn->class_code = 0; |
1635317f | 1028 | pdn->eeh_mode = 0; |
5c1344e9 LV |
1029 | pdn->eeh_check_count = 0; |
1030 | pdn->eeh_freeze_count = 0; | |
858955bd | 1031 | pdn->eeh_false_positives = 0; |
1da177e4 | 1032 | |
c6d4d5a8 NL |
1033 | if (!of_device_is_available(dn)) |
1034 | return NULL; | |
1da177e4 LT |
1035 | |
1036 | /* Ignore bad nodes. */ | |
1037 | if (!class_code || !vendor_id || !device_id) | |
1038 | return NULL; | |
1039 | ||
1040 | /* There is nothing to check on PCI to ISA bridges */ | |
1041 | if (dn->type && !strcmp(dn->type, "isa")) { | |
1635317f | 1042 | pdn->eeh_mode |= EEH_MODE_NOCHECK; |
1da177e4 LT |
1043 | return NULL; |
1044 | } | |
0f17574a | 1045 | pdn->class_code = *class_code; |
1da177e4 | 1046 | |
1da177e4 LT |
1047 | /* Ok... see if this device supports EEH. Some do, some don't, |
1048 | * and the only way to find out is to check each and every one. */ | |
e2eb6392 | 1049 | regs = of_get_property(dn, "reg", NULL); |
1da177e4 LT |
1050 | if (regs) { |
1051 | /* First register entry is addr (00BBSS00) */ | |
1052 | /* Try to enable eeh */ | |
1053 | ret = rtas_call(ibm_set_eeh_option, 4, 1, NULL, | |
172ca926 LV |
1054 | regs[0], info->buid_hi, info->buid_lo, |
1055 | EEH_ENABLE); | |
1056 | ||
25c4a46f | 1057 | enable = 0; |
1da177e4 | 1058 | if (ret == 0) { |
1635317f | 1059 | pdn->eeh_config_addr = regs[0]; |
25e591f6 LV |
1060 | |
1061 | /* If the newer, better, ibm,get-config-addr-info is supported, | |
1062 | * then use that instead. */ | |
147d6a37 | 1063 | pdn->eeh_pe_config_addr = get_pe_addr(pdn->eeh_config_addr, info); |
25c4a46f LV |
1064 | |
1065 | /* Some older systems (Power4) allow the | |
1066 | * ibm,set-eeh-option call to succeed even on nodes | |
1067 | * where EEH is not supported. Verify support | |
1068 | * explicitly. */ | |
1069 | ret = read_slot_reset_state(pdn, rets); | |
1070 | if ((ret == 0) && (rets[1] == 1)) | |
1071 | enable = 1; | |
1072 | } | |
1073 | ||
1074 | if (enable) { | |
1075 | eeh_subsystem_enabled = 1; | |
1076 | pdn->eeh_mode |= EEH_MODE_SUPPORTED; | |
1077 | ||
57b066ff BH |
1078 | pr_debug("EEH: %s: eeh enabled, config=%x pe_config=%x\n", |
1079 | dn->full_name, pdn->eeh_config_addr, | |
1080 | pdn->eeh_pe_config_addr); | |
1da177e4 LT |
1081 | } else { |
1082 | ||
1083 | /* This device doesn't support EEH, but it may have an | |
1084 | * EEH parent, in which case we mark it as supported. */ | |
69376502 | 1085 | if (dn->parent && PCI_DN(dn->parent) |
1635317f | 1086 | && (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) { |
1da177e4 | 1087 | /* Parent supports EEH. */ |
1635317f PM |
1088 | pdn->eeh_mode |= EEH_MODE_SUPPORTED; |
1089 | pdn->eeh_config_addr = PCI_DN(dn->parent)->eeh_config_addr; | |
1da177e4 LT |
1090 | return NULL; |
1091 | } | |
1092 | } | |
1093 | } else { | |
1094 | printk(KERN_WARNING "EEH: %s: unable to get reg property.\n", | |
1095 | dn->full_name); | |
1096 | } | |
1097 | ||
7684b40c | 1098 | eeh_save_bars(pdn); |
69376502 | 1099 | return NULL; |
1da177e4 LT |
1100 | } |
1101 | ||
1102 | /* | |
1103 | * Initialize EEH by trying to enable it for all of the adapters in the system. | |
1104 | * As a side effect we can determine here if eeh is supported at all. | |
1105 | * Note that we leave EEH on so failed config cycles won't cause a machine | |
1106 | * check. If a user turns off EEH for a particular adapter they are really | |
1107 | * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't | |
1108 | * grant access to a slot if EEH isn't enabled, and so we always enable | |
1109 | * EEH for all slots/all devices. | |
1110 | * | |
1111 | * The eeh-force-off option disables EEH checking globally, for all slots. | |
1112 | * Even if force-off is set, the EEH hardware is still enabled, so that | |
1113 | * newer systems can boot. | |
1114 | */ | |
1115 | void __init eeh_init(void) | |
1116 | { | |
1117 | struct device_node *phb, *np; | |
1118 | struct eeh_early_enable_info info; | |
1119 | ||
3d372628 | 1120 | raw_spin_lock_init(&confirm_error_lock); |
df7242b1 LV |
1121 | spin_lock_init(&slot_errbuf_lock); |
1122 | ||
1da177e4 LT |
1123 | np = of_find_node_by_path("/rtas"); |
1124 | if (np == NULL) | |
1125 | return; | |
1126 | ||
1127 | ibm_set_eeh_option = rtas_token("ibm,set-eeh-option"); | |
1128 | ibm_set_slot_reset = rtas_token("ibm,set-slot-reset"); | |
1129 | ibm_read_slot_reset_state2 = rtas_token("ibm,read-slot-reset-state2"); | |
1130 | ibm_read_slot_reset_state = rtas_token("ibm,read-slot-reset-state"); | |
1131 | ibm_slot_error_detail = rtas_token("ibm,slot-error-detail"); | |
25e591f6 | 1132 | ibm_get_config_addr_info = rtas_token("ibm,get-config-addr-info"); |
147d6a37 | 1133 | ibm_get_config_addr_info2 = rtas_token("ibm,get-config-addr-info2"); |
21e464dd | 1134 | ibm_configure_bridge = rtas_token ("ibm,configure-bridge"); |
65f47f13 | 1135 | ibm_configure_pe = rtas_token("ibm,configure-pe"); |
1da177e4 LT |
1136 | |
1137 | if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE) | |
1138 | return; | |
1139 | ||
1140 | eeh_error_buf_size = rtas_token("rtas-error-log-max"); | |
1141 | if (eeh_error_buf_size == RTAS_UNKNOWN_SERVICE) { | |
1142 | eeh_error_buf_size = 1024; | |
1143 | } | |
1144 | if (eeh_error_buf_size > RTAS_ERROR_LOG_MAX) { | |
1145 | printk(KERN_WARNING "EEH: rtas-error-log-max is bigger than allocated " | |
1146 | "buffer ! (%d vs %d)", eeh_error_buf_size, RTAS_ERROR_LOG_MAX); | |
1147 | eeh_error_buf_size = RTAS_ERROR_LOG_MAX; | |
1148 | } | |
1149 | ||
1150 | /* Enable EEH for all adapters. Note that eeh requires buid's */ | |
1151 | for (phb = of_find_node_by_name(NULL, "pci"); phb; | |
1152 | phb = of_find_node_by_name(phb, "pci")) { | |
1153 | unsigned long buid; | |
1154 | ||
1155 | buid = get_phb_buid(phb); | |
69376502 | 1156 | if (buid == 0 || PCI_DN(phb) == NULL) |
1da177e4 LT |
1157 | continue; |
1158 | ||
1159 | info.buid_lo = BUID_LO(buid); | |
1160 | info.buid_hi = BUID_HI(buid); | |
1161 | traverse_pci_devices(phb, early_enable_eeh, &info); | |
1162 | } | |
1163 | ||
1164 | if (eeh_subsystem_enabled) | |
1165 | printk(KERN_INFO "EEH: PCI Enhanced I/O Error Handling Enabled\n"); | |
1166 | else | |
1167 | printk(KERN_WARNING "EEH: No capable adapters found\n"); | |
1168 | } | |
1169 | ||
1170 | /** | |
1171 | * eeh_add_device_early - enable EEH for the indicated device_node | |
1172 | * @dn: device node for which to set up EEH | |
1173 | * | |
1174 | * This routine must be used to perform EEH initialization for PCI | |
1175 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
1176 | * This routine must be called before any i/o is performed to the | |
1177 | * adapter (inluding any config-space i/o). | |
1178 | * Whether this actually enables EEH or not for this device depends | |
1179 | * on the CEC architecture, type of the device, on earlier boot | |
1180 | * command-line arguments & etc. | |
1181 | */ | |
794e085e | 1182 | static void eeh_add_device_early(struct device_node *dn) |
1da177e4 LT |
1183 | { |
1184 | struct pci_controller *phb; | |
1185 | struct eeh_early_enable_info info; | |
1186 | ||
69376502 | 1187 | if (!dn || !PCI_DN(dn)) |
1da177e4 | 1188 | return; |
1635317f | 1189 | phb = PCI_DN(dn)->phb; |
f751f841 LV |
1190 | |
1191 | /* USB Bus children of PCI devices will not have BUID's */ | |
1192 | if (NULL == phb || 0 == phb->buid) | |
1da177e4 | 1193 | return; |
1da177e4 LT |
1194 | |
1195 | info.buid_hi = BUID_HI(phb->buid); | |
1196 | info.buid_lo = BUID_LO(phb->buid); | |
1197 | early_enable_eeh(dn, &info); | |
1198 | } | |
1da177e4 | 1199 | |
e2a296ee LV |
1200 | void eeh_add_device_tree_early(struct device_node *dn) |
1201 | { | |
1202 | struct device_node *sib; | |
acaa6176 SR |
1203 | |
1204 | for_each_child_of_node(dn, sib) | |
e2a296ee LV |
1205 | eeh_add_device_tree_early(sib); |
1206 | eeh_add_device_early(dn); | |
1207 | } | |
1208 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_early); | |
1209 | ||
1da177e4 LT |
1210 | /** |
1211 | * eeh_add_device_late - perform EEH initialization for the indicated pci device | |
1212 | * @dev: pci device for which to set up EEH | |
1213 | * | |
1214 | * This routine must be used to complete EEH initialization for PCI | |
1215 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
1216 | */ | |
794e085e | 1217 | static void eeh_add_device_late(struct pci_dev *dev) |
1da177e4 | 1218 | { |
56b0fca3 | 1219 | struct device_node *dn; |
8b553f32 | 1220 | struct pci_dn *pdn; |
56b0fca3 | 1221 | |
1da177e4 LT |
1222 | if (!dev || !eeh_subsystem_enabled) |
1223 | return; | |
1224 | ||
57b066ff | 1225 | pr_debug("EEH: Adding device %s\n", pci_name(dev)); |
1da177e4 | 1226 | |
56b0fca3 | 1227 | dn = pci_device_to_OF_node(dev); |
8b553f32 | 1228 | pdn = PCI_DN(dn); |
57b066ff BH |
1229 | if (pdn->pcidev == dev) { |
1230 | pr_debug("EEH: Already referenced !\n"); | |
1231 | return; | |
1232 | } | |
1233 | WARN_ON(pdn->pcidev); | |
1234 | ||
1235 | pci_dev_get (dev); | |
8b553f32 | 1236 | pdn->pcidev = dev; |
56b0fca3 | 1237 | |
e1d04c97 LV |
1238 | pci_addr_cache_insert_device(dev); |
1239 | eeh_sysfs_add_device(dev); | |
1da177e4 | 1240 | } |
794e085e NF |
1241 | |
1242 | void eeh_add_device_tree_late(struct pci_bus *bus) | |
1243 | { | |
1244 | struct pci_dev *dev; | |
1245 | ||
1246 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1247 | eeh_add_device_late(dev); | |
1248 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1249 | struct pci_bus *subbus = dev->subordinate; | |
1250 | if (subbus) | |
1251 | eeh_add_device_tree_late(subbus); | |
1252 | } | |
1253 | } | |
1254 | } | |
1255 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_late); | |
1da177e4 LT |
1256 | |
1257 | /** | |
1258 | * eeh_remove_device - undo EEH setup for the indicated pci device | |
1259 | * @dev: pci device to be removed | |
1260 | * | |
794e085e NF |
1261 | * This routine should be called when a device is removed from |
1262 | * a running system (e.g. by hotplug or dlpar). It unregisters | |
1263 | * the PCI device from the EEH subsystem. I/O errors affecting | |
1264 | * this device will no longer be detected after this call; thus, | |
1265 | * i/o errors affecting this slot may leave this device unusable. | |
1da177e4 | 1266 | */ |
794e085e | 1267 | static void eeh_remove_device(struct pci_dev *dev) |
1da177e4 | 1268 | { |
56b0fca3 | 1269 | struct device_node *dn; |
1da177e4 LT |
1270 | if (!dev || !eeh_subsystem_enabled) |
1271 | return; | |
1272 | ||
1273 | /* Unregister the device with the EEH/PCI address search system */ | |
57b066ff | 1274 | pr_debug("EEH: Removing device %s\n", pci_name(dev)); |
56b0fca3 LV |
1275 | |
1276 | dn = pci_device_to_OF_node(dev); | |
57b066ff BH |
1277 | if (PCI_DN(dn)->pcidev == NULL) { |
1278 | pr_debug("EEH: Not referenced !\n"); | |
1279 | return; | |
b055a9e1 | 1280 | } |
57b066ff BH |
1281 | PCI_DN(dn)->pcidev = NULL; |
1282 | pci_dev_put (dev); | |
1283 | ||
1284 | pci_addr_cache_remove_device(dev); | |
1285 | eeh_sysfs_remove_device(dev); | |
1da177e4 | 1286 | } |
1da177e4 | 1287 | |
e2a296ee LV |
1288 | void eeh_remove_bus_device(struct pci_dev *dev) |
1289 | { | |
794e085e NF |
1290 | struct pci_bus *bus = dev->subordinate; |
1291 | struct pci_dev *child, *tmp; | |
1292 | ||
e2a296ee | 1293 | eeh_remove_device(dev); |
794e085e NF |
1294 | |
1295 | if (bus && dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1296 | list_for_each_entry_safe(child, tmp, &bus->devices, bus_list) | |
1297 | eeh_remove_bus_device(child); | |
e2a296ee LV |
1298 | } |
1299 | } | |
1300 | EXPORT_SYMBOL_GPL(eeh_remove_bus_device); | |
1301 | ||
1da177e4 LT |
1302 | static int proc_eeh_show(struct seq_file *m, void *v) |
1303 | { | |
1da177e4 LT |
1304 | if (0 == eeh_subsystem_enabled) { |
1305 | seq_printf(m, "EEH Subsystem is globally disabled\n"); | |
257ffc64 | 1306 | seq_printf(m, "eeh_total_mmio_ffs=%ld\n", total_mmio_ffs); |
1da177e4 LT |
1307 | } else { |
1308 | seq_printf(m, "EEH Subsystem is enabled\n"); | |
177bc936 LV |
1309 | seq_printf(m, |
1310 | "no device=%ld\n" | |
1311 | "no device node=%ld\n" | |
1312 | "no config address=%ld\n" | |
1313 | "check not wanted=%ld\n" | |
1314 | "eeh_total_mmio_ffs=%ld\n" | |
1315 | "eeh_false_positives=%ld\n" | |
177bc936 | 1316 | "eeh_slot_resets=%ld\n", |
257ffc64 LV |
1317 | no_device, no_dn, no_cfg_addr, |
1318 | ignored_check, total_mmio_ffs, | |
42253a68 | 1319 | false_positives, |
257ffc64 | 1320 | slot_resets); |
1da177e4 LT |
1321 | } |
1322 | ||
1323 | return 0; | |
1324 | } | |
1325 | ||
1326 | static int proc_eeh_open(struct inode *inode, struct file *file) | |
1327 | { | |
1328 | return single_open(file, proc_eeh_show, NULL); | |
1329 | } | |
1330 | ||
5dfe4c96 | 1331 | static const struct file_operations proc_eeh_operations = { |
1da177e4 LT |
1332 | .open = proc_eeh_open, |
1333 | .read = seq_read, | |
1334 | .llseek = seq_lseek, | |
1335 | .release = single_release, | |
1336 | }; | |
1337 | ||
1338 | static int __init eeh_init_proc(void) | |
1339 | { | |
66747138 DL |
1340 | if (machine_is(pseries)) |
1341 | proc_create("ppc64/eeh", 0, NULL, &proc_eeh_operations); | |
1da177e4 LT |
1342 | return 0; |
1343 | } | |
1344 | __initcall(eeh_init_proc); |