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3038acf9 NC |
1 | /* |
2 | * Copyright (C) 2009 Extreme Engineering Solutions, Inc. | |
3 | * | |
4 | * X-ES board-specific functionality | |
5 | * | |
6 | * Based on mpc85xx_ds code from Freescale Semiconductor, Inc. | |
7 | * | |
8 | * Author: Nate Case <ncase@xes-inc.com> | |
9 | * | |
10 | * This is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/stddef.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/kdev_t.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/seq_file.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/of_platform.h> | |
23 | ||
3038acf9 NC |
24 | #include <asm/time.h> |
25 | #include <asm/machdep.h> | |
26 | #include <asm/pci-bridge.h> | |
27 | #include <mm/mmu_decl.h> | |
28 | #include <asm/prom.h> | |
29 | #include <asm/udbg.h> | |
30 | #include <asm/mpic.h> | |
31 | ||
32 | #include <sysdev/fsl_soc.h> | |
33 | #include <sysdev/fsl_pci.h> | |
582d3e09 | 34 | #include "smp.h" |
3038acf9 | 35 | |
543a07b1 DES |
36 | #include "mpc85xx.h" |
37 | ||
3038acf9 NC |
38 | /* A few bit definitions needed for fixups on some boards */ |
39 | #define MPC85xx_L2CTL_L2E 0x80000000 /* L2 enable */ | |
40 | #define MPC85xx_L2CTL_L2I 0x40000000 /* L2 flash invalidate */ | |
41 | #define MPC85xx_L2CTL_L2SIZ_MASK 0x30000000 /* L2 SRAM size (R/O) */ | |
42 | ||
43 | void __init xes_mpc85xx_pic_init(void) | |
44 | { | |
e55d7f73 | 45 | struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN, |
3038acf9 NC |
46 | 0, 256, " OpenPIC "); |
47 | BUG_ON(mpic == NULL); | |
3038acf9 NC |
48 | mpic_init(mpic); |
49 | } | |
50 | ||
51 | static void xes_mpc85xx_configure_l2(void __iomem *l2_base) | |
52 | { | |
53 | volatile uint32_t ctl, tmp; | |
54 | ||
55 | asm volatile("msync; isync"); | |
56 | tmp = in_be32(l2_base); | |
57 | ||
58 | /* | |
59 | * xMon may have enabled part of L2 as SRAM, so we need to set it | |
60 | * up for all cache mode just to be safe. | |
61 | */ | |
62 | printk(KERN_INFO "xes_mpc85xx: Enabling L2 as cache\n"); | |
63 | ||
64 | ctl = MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2I; | |
71a157e8 GL |
65 | if (of_machine_is_compatible("MPC8540") || |
66 | of_machine_is_compatible("MPC8560")) | |
3038acf9 NC |
67 | /* |
68 | * Assume L2 SRAM is used fully for cache, so set | |
69 | * L2BLKSZ (bits 4:5) to match L2SIZ (bits 2:3). | |
70 | */ | |
71 | ctl |= (tmp & MPC85xx_L2CTL_L2SIZ_MASK) >> 2; | |
72 | ||
73 | asm volatile("msync; isync"); | |
74 | out_be32(l2_base, ctl); | |
75 | asm volatile("msync; isync"); | |
76 | } | |
77 | ||
78 | static void xes_mpc85xx_fixups(void) | |
79 | { | |
80 | struct device_node *np; | |
81 | int err; | |
82 | ||
83 | /* | |
84 | * Legacy xMon firmware on some X-ES boards does not enable L2 | |
85 | * as cache. We must ensure that they get enabled here. | |
86 | */ | |
87 | for_each_node_by_name(np, "l2-cache-controller") { | |
88 | struct resource r[2]; | |
89 | void __iomem *l2_base; | |
90 | ||
91 | /* Only MPC8548, MPC8540, and MPC8560 boards are affected */ | |
92 | if (!of_device_is_compatible(np, | |
93 | "fsl,mpc8548-l2-cache-controller") && | |
94 | !of_device_is_compatible(np, | |
95 | "fsl,mpc8540-l2-cache-controller") && | |
96 | !of_device_is_compatible(np, | |
97 | "fsl,mpc8560-l2-cache-controller")) | |
98 | continue; | |
99 | ||
100 | err = of_address_to_resource(np, 0, &r[0]); | |
101 | if (err) { | |
102 | printk(KERN_WARNING "xes_mpc85xx: Could not get " | |
103 | "resource for device tree node '%s'", | |
104 | np->full_name); | |
105 | continue; | |
106 | } | |
107 | ||
28f65c11 | 108 | l2_base = ioremap(r[0].start, resource_size(&r[0])); |
3038acf9 NC |
109 | |
110 | xes_mpc85xx_configure_l2(l2_base); | |
111 | } | |
112 | } | |
113 | ||
114 | #ifdef CONFIG_PCI | |
115 | static int primary_phb_addr; | |
116 | #endif | |
117 | ||
118 | /* | |
119 | * Setup the architecture | |
120 | */ | |
3038acf9 NC |
121 | static void __init xes_mpc85xx_setup_arch(void) |
122 | { | |
123 | #ifdef CONFIG_PCI | |
124 | struct device_node *np; | |
125 | #endif | |
126 | struct device_node *root; | |
127 | const char *model = "Unknown"; | |
128 | ||
129 | root = of_find_node_by_path("/"); | |
130 | if (root == NULL) | |
131 | return; | |
132 | ||
133 | model = of_get_property(root, "model", NULL); | |
134 | ||
135 | printk(KERN_INFO "X-ES MPC85xx-based single-board computer: %s\n", | |
136 | model + strlen("xes,")); | |
137 | ||
138 | xes_mpc85xx_fixups(); | |
139 | ||
140 | #ifdef CONFIG_PCI | |
141 | for_each_node_by_type(np, "pci") { | |
142 | if (of_device_is_compatible(np, "fsl,mpc8540-pci") || | |
143 | of_device_is_compatible(np, "fsl,mpc8548-pcie")) { | |
144 | struct resource rsrc; | |
145 | of_address_to_resource(np, 0, &rsrc); | |
146 | if ((rsrc.start & 0xfffff) == primary_phb_addr) | |
147 | fsl_add_bridge(np, 1); | |
148 | else | |
149 | fsl_add_bridge(np, 0); | |
150 | } | |
151 | } | |
152 | #endif | |
153 | ||
3038acf9 | 154 | mpc85xx_smp_init(); |
3038acf9 NC |
155 | } |
156 | ||
46d026ac DES |
157 | machine_device_initcall(xes_mpc8572, mpc85xx_common_publish_devices); |
158 | machine_device_initcall(xes_mpc8548, mpc85xx_common_publish_devices); | |
159 | machine_device_initcall(xes_mpc8540, mpc85xx_common_publish_devices); | |
3038acf9 NC |
160 | |
161 | /* | |
162 | * Called very early, device-tree isn't unflattened | |
163 | */ | |
164 | static int __init xes_mpc8572_probe(void) | |
165 | { | |
166 | unsigned long root = of_get_flat_dt_root(); | |
167 | ||
168 | if (of_flat_dt_is_compatible(root, "xes,MPC8572")) { | |
169 | #ifdef CONFIG_PCI | |
170 | primary_phb_addr = 0x8000; | |
171 | #endif | |
172 | return 1; | |
173 | } else { | |
174 | return 0; | |
175 | } | |
176 | } | |
177 | ||
178 | static int __init xes_mpc8548_probe(void) | |
179 | { | |
180 | unsigned long root = of_get_flat_dt_root(); | |
181 | ||
182 | if (of_flat_dt_is_compatible(root, "xes,MPC8548")) { | |
183 | #ifdef CONFIG_PCI | |
184 | primary_phb_addr = 0xb000; | |
185 | #endif | |
186 | return 1; | |
187 | } else { | |
188 | return 0; | |
189 | } | |
190 | } | |
191 | ||
192 | static int __init xes_mpc8540_probe(void) | |
193 | { | |
194 | unsigned long root = of_get_flat_dt_root(); | |
195 | ||
196 | if (of_flat_dt_is_compatible(root, "xes,MPC8540")) { | |
197 | #ifdef CONFIG_PCI | |
198 | primary_phb_addr = 0xb000; | |
199 | #endif | |
200 | return 1; | |
201 | } else { | |
202 | return 0; | |
203 | } | |
204 | } | |
205 | ||
206 | define_machine(xes_mpc8572) { | |
207 | .name = "X-ES MPC8572", | |
208 | .probe = xes_mpc8572_probe, | |
209 | .setup_arch = xes_mpc85xx_setup_arch, | |
210 | .init_IRQ = xes_mpc85xx_pic_init, | |
211 | #ifdef CONFIG_PCI | |
212 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | |
213 | #endif | |
214 | .get_irq = mpic_get_irq, | |
215 | .restart = fsl_rstcr_restart, | |
216 | .calibrate_decr = generic_calibrate_decr, | |
217 | .progress = udbg_progress, | |
218 | }; | |
219 | ||
220 | define_machine(xes_mpc8548) { | |
221 | .name = "X-ES MPC8548", | |
222 | .probe = xes_mpc8548_probe, | |
223 | .setup_arch = xes_mpc85xx_setup_arch, | |
224 | .init_IRQ = xes_mpc85xx_pic_init, | |
225 | #ifdef CONFIG_PCI | |
226 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | |
227 | #endif | |
228 | .get_irq = mpic_get_irq, | |
229 | .restart = fsl_rstcr_restart, | |
230 | .calibrate_decr = generic_calibrate_decr, | |
231 | .progress = udbg_progress, | |
232 | }; | |
233 | ||
234 | define_machine(xes_mpc8540) { | |
235 | .name = "X-ES MPC8540", | |
236 | .probe = xes_mpc8540_probe, | |
237 | .setup_arch = xes_mpc85xx_setup_arch, | |
238 | .init_IRQ = xes_mpc85xx_pic_init, | |
239 | #ifdef CONFIG_PCI | |
240 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | |
241 | #endif | |
242 | .get_irq = mpic_get_irq, | |
243 | .restart = fsl_rstcr_restart, | |
244 | .calibrate_decr = generic_calibrate_decr, | |
245 | .progress = udbg_progress, | |
246 | }; |