[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / oprofile / op_model_fsl_booke.c

/*
 * arch/powerpc/oprofile/op_model_fsl_booke.c
 *
 * Freescale Book-E oprofile support, based on ppc64 oprofile support
 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
 *
 * Copyright (c) 2004 Freescale Semiconductor, Inc
 *
 * Author: Andy Fleming
 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/oprofile.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/processor.h>
#include <asm/cputable.h>
#include <asm/reg_booke.h>
#include <asm/page.h>
#include <asm/pmc.h>
#include <asm/oprofile_impl.h>

static unsigned long reset_value[OP_MAX_COUNTER];

static int num_counters;
static int oprofile_running;

static inline u32 get_pmlca(int ctr)
{
	u32 pmlca;

	switch (ctr) {
		case 0:
			pmlca = mfpmr(PMRN_PMLCA0);
			break;
		case 1:
			pmlca = mfpmr(PMRN_PMLCA1);
			break;
		case 2:
			pmlca = mfpmr(PMRN_PMLCA2);
			break;
		case 3:
			pmlca = mfpmr(PMRN_PMLCA3);
			break;
		default:
			panic("Bad ctr number\n");
	}

	return pmlca;
}

static inline void set_pmlca(int ctr, u32 pmlca)
{
	switch (ctr) {
		case 0:
			mtpmr(PMRN_PMLCA0, pmlca);
			break;
		case 1:
			mtpmr(PMRN_PMLCA1, pmlca);
			break;
		case 2:
			mtpmr(PMRN_PMLCA2, pmlca);
			break;
		case 3:
			mtpmr(PMRN_PMLCA3, pmlca);
			break;
		default:
			panic("Bad ctr number\n");
	}
}

static inline unsigned int ctr_read(unsigned int i)
{
	switch(i) {
		case 0:
			return mfpmr(PMRN_PMC0);
		case 1:
			return mfpmr(PMRN_PMC1);
		case 2:
			return mfpmr(PMRN_PMC2);
		case 3:
			return mfpmr(PMRN_PMC3);
		default:
			return 0;
	}
}

static inline void ctr_write(unsigned int i, unsigned int val)
{
	switch(i) {
		case 0:
			mtpmr(PMRN_PMC0, val);
			break;
		case 1:
			mtpmr(PMRN_PMC1, val);
			break;
		case 2:
			mtpmr(PMRN_PMC2, val);
			break;
		case 3:
			mtpmr(PMRN_PMC3, val);
			break;
		default:
			break;
	}
}


static void init_pmc_stop(int ctr)
{
	u32 pmlca = (PMLCA_FC | PMLCA_FCS | PMLCA_FCU |
			PMLCA_FCM1 | PMLCA_FCM0);
	u32 pmlcb = 0;

	switch (ctr) {
		case 0:
			mtpmr(PMRN_PMLCA0, pmlca);
			mtpmr(PMRN_PMLCB0, pmlcb);
			break;
		case 1:
			mtpmr(PMRN_PMLCA1, pmlca);
			mtpmr(PMRN_PMLCB1, pmlcb);
			break;
		case 2:
			mtpmr(PMRN_PMLCA2, pmlca);
			mtpmr(PMRN_PMLCB2, pmlcb);
			break;
		case 3:
			mtpmr(PMRN_PMLCA3, pmlca);
			mtpmr(PMRN_PMLCB3, pmlcb);
			break;
		default:
			panic("Bad ctr number!\n");
	}
}

static void set_pmc_event(int ctr, int event)
{
	u32 pmlca;

	pmlca = get_pmlca(ctr);

	pmlca = (pmlca & ~PMLCA_EVENT_MASK) |
		((event << PMLCA_EVENT_SHIFT) &
		 PMLCA_EVENT_MASK);

	set_pmlca(ctr, pmlca);
}

static void set_pmc_user_kernel(int ctr, int user, int kernel)
{
	u32 pmlca;

	pmlca = get_pmlca(ctr);

	if(user)
		pmlca &= ~PMLCA_FCU;
	else
		pmlca |= PMLCA_FCU;

	if(kernel)
		pmlca &= ~PMLCA_FCS;
	else
		pmlca |= PMLCA_FCS;

	set_pmlca(ctr, pmlca);
}

static void set_pmc_marked(int ctr, int mark0, int mark1)
{
	u32 pmlca = get_pmlca(ctr);

	if(mark0)
		pmlca &= ~PMLCA_FCM0;
	else
		pmlca |= PMLCA_FCM0;

	if(mark1)
		pmlca &= ~PMLCA_FCM1;
	else
		pmlca |= PMLCA_FCM1;

	set_pmlca(ctr, pmlca);
}

static void pmc_start_ctr(int ctr, int enable)
{
	u32 pmlca = get_pmlca(ctr);

	pmlca &= ~PMLCA_FC;

	if (enable)
		pmlca |= PMLCA_CE;
	else
		pmlca &= ~PMLCA_CE;

	set_pmlca(ctr, pmlca);
}

static void pmc_start_ctrs(int enable)
{
	u32 pmgc0 = mfpmr(PMRN_PMGC0);

	pmgc0 &= ~PMGC0_FAC;
	pmgc0 |= PMGC0_FCECE;

	if (enable)
		pmgc0 |= PMGC0_PMIE;
	else
		pmgc0 &= ~PMGC0_PMIE;

	mtpmr(PMRN_PMGC0, pmgc0);
}

static void pmc_stop_ctrs(void)
{
	u32 pmgc0 = mfpmr(PMRN_PMGC0);

	pmgc0 |= PMGC0_FAC;

	pmgc0 &= ~(PMGC0_PMIE | PMGC0_FCECE);

	mtpmr(PMRN_PMGC0, pmgc0);
}

static void dump_pmcs(void)
{
	printk("pmgc0: %x\n", mfpmr(PMRN_PMGC0));
	printk("pmc\t\tpmlca\t\tpmlcb\n");
	printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC0),
			mfpmr(PMRN_PMLCA0), mfpmr(PMRN_PMLCB0));
	printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC1),
			mfpmr(PMRN_PMLCA1), mfpmr(PMRN_PMLCB1));
	printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC2),
			mfpmr(PMRN_PMLCA2), mfpmr(PMRN_PMLCB2));
	printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC3),
			mfpmr(PMRN_PMLCA3), mfpmr(PMRN_PMLCB3));
}

static int fsl_booke_cpu_setup(struct op_counter_config *ctr)
{
	int i;

	/* freeze all counters */
	pmc_stop_ctrs();

	for (i = 0;i < num_counters;i++) {
		init_pmc_stop(i);

		set_pmc_event(i, ctr[i].event);

		set_pmc_user_kernel(i, ctr[i].user, ctr[i].kernel);
	}

	return 0;
}

static int fsl_booke_reg_setup(struct op_counter_config *ctr,
			     struct op_system_config *sys,
			     int num_ctrs)
{
	int i;

	num_counters = num_ctrs;

	/* Our counters count up, and "count" refers to
	 * how much before the next interrupt, and we interrupt
	 * on overflow.  So we calculate the starting value
	 * which will give us "count" until overflow.
	 * Then we set the events on the enabled counters */
	for (i = 0; i < num_counters; ++i)
		reset_value[i] = 0x80000000UL - ctr[i].count;

	return 0;
}

static int fsl_booke_start(struct op_counter_config *ctr)
{
	int i;

	mtmsr(mfmsr() | MSR_PMM);

	for (i = 0; i < num_counters; ++i) {
		if (ctr[i].enabled) {
			ctr_write(i, reset_value[i]);
			/* Set each enabled counter to only
			 * count when the Mark bit is *not* set */
			set_pmc_marked(i, 1, 0);
			pmc_start_ctr(i, 1);
		} else {
			ctr_write(i, 0);

			/* Set the ctr to be stopped */
			pmc_start_ctr(i, 0);
		}
	}

	/* Clear the freeze bit, and enable the interrupt.
	 * The counters won't actually start until the rfi clears
	 * the PMM bit */
	pmc_start_ctrs(1);

	oprofile_running = 1;

	pr_debug("start on cpu %d, pmgc0 %x\n", smp_processor_id(),
			mfpmr(PMRN_PMGC0));

	return 0;
}

static void fsl_booke_stop(void)
{
	/* freeze counters */
	pmc_stop_ctrs();

	oprofile_running = 0;

	pr_debug("stop on cpu %d, pmgc0 %x\n", smp_processor_id(),
			mfpmr(PMRN_PMGC0));

	mb();
}


static void fsl_booke_handle_interrupt(struct pt_regs *regs,
				    struct op_counter_config *ctr)
{
	unsigned long pc;
	int is_kernel;
	int val;
	int i;

	/* set the PMM bit (see comment below) */
	mtmsr(mfmsr() | MSR_PMM);

	pc = regs->nip;
	is_kernel = is_kernel_addr(pc);

	for (i = 0; i < num_counters; ++i) {
		val = ctr_read(i);
		if (val < 0) {
			if (oprofile_running && ctr[i].enabled) {
				oprofile_add_ext_sample(pc, regs, i, is_kernel);
				ctr_write(i, reset_value[i]);
			} else {
				ctr_write(i, 0);
			}
		}
	}

	/* The freeze bit was set by the interrupt. */
	/* Clear the freeze bit, and reenable the interrupt.
	 * The counters won't actually start until the rfi clears
	 * the PMM bit */
	pmc_start_ctrs(1);
}

struct op_powerpc_model op_model_fsl_booke = {
	.reg_setup		= fsl_booke_reg_setup,
	.cpu_setup		= fsl_booke_cpu_setup,
	.start			= fsl_booke_start,
	.stop			= fsl_booke_stop,
	.handle_interrupt	= fsl_booke_handle_interrupt,
};
Commit	Line	Data
1da177e4	1	/*
f30c2269	2	* arch/powerpc/oprofile/op_model_fsl_booke.c
1da177e4 LT	3	*
	4	* Freescale Book-E oprofile support, based on ppc64 oprofile support
	5	* Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
	6	*
	7	* Copyright (c) 2004 Freescale Semiconductor, Inc
	8	*
	9	* Author: Andy Fleming
4c8d3d99	10	* Maintainer: Kumar Gala <galak@kernel.crashing.org>
1da177e4 LT	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License
	14	* as published by the Free Software Foundation; either version
	15	* 2 of the License, or (at your option) any later version.
	16	*/
	17
	18	#include <linux/oprofile.h>
	19	#include <linux/init.h>
	20	#include <linux/smp.h>
	21	#include <asm/ptrace.h>
	22	#include <asm/system.h>
	23	#include <asm/processor.h>
	24	#include <asm/cputable.h>
	25	#include <asm/reg_booke.h>
	26	#include <asm/page.h>
f7f6f4fe	27	#include <asm/pmc.h>
654810ec	28	#include <asm/oprofile_impl.h>
1da177e4 LT	29
	30	static unsigned long reset_value[OP_MAX_COUNTER];
	31
	32	static int num_counters;
	33	static int oprofile_running;
	34
c69b767a OJ	35	static inline u32 get_pmlca(int ctr)
	36	{
	37	u32 pmlca;
	38
	39	switch (ctr) {
	40	case 0:
	41	pmlca = mfpmr(PMRN_PMLCA0);
	42	break;
	43	case 1:
	44	pmlca = mfpmr(PMRN_PMLCA1);
	45	break;
	46	case 2:
	47	pmlca = mfpmr(PMRN_PMLCA2);
	48	break;
	49	case 3:
	50	pmlca = mfpmr(PMRN_PMLCA3);
	51	break;
	52	default:
	53	panic("Bad ctr number\n");
	54	}
	55
	56	return pmlca;
	57	}
	58
	59	static inline void set_pmlca(int ctr, u32 pmlca)
	60	{
	61	switch (ctr) {
	62	case 0:
	63	mtpmr(PMRN_PMLCA0, pmlca);
	64	break;
	65	case 1:
	66	mtpmr(PMRN_PMLCA1, pmlca);
	67	break;
	68	case 2:
	69	mtpmr(PMRN_PMLCA2, pmlca);
	70	break;
	71	case 3:
	72	mtpmr(PMRN_PMLCA3, pmlca);
	73	break;
	74	default:
	75	panic("Bad ctr number\n");
	76	}
	77	}
	78
	79	static inline unsigned int ctr_read(unsigned int i)
	80	{
	81	switch(i) {
	82	case 0:
	83	return mfpmr(PMRN_PMC0);
	84	case 1:
	85	return mfpmr(PMRN_PMC1);
	86	case 2:
	87	return mfpmr(PMRN_PMC2);
	88	case 3:
	89	return mfpmr(PMRN_PMC3);
	90	default:
	91	return 0;
	92	}
	93	}
	94
	95	static inline void ctr_write(unsigned int i, unsigned int val)
	96	{
	97	switch(i) {
	98	case 0:
99	mtpmr(PMRN_PMC0, val);
100	break;
101	case 1:
102	mtpmr(PMRN_PMC1, val);
103	break;
104	case 2:
105	mtpmr(PMRN_PMC2, val);
106	break;
107	case 3:
108	mtpmr(PMRN_PMC3, val);
109	break;
110	default:
111	break;
112	}
113	}
114
115
dd6c89f6	116	static void init_pmc_stop(int ctr)
1da177e4	117	{
dd6c89f6 AF	118	u32 pmlca = (PMLCA_FC \| PMLCA_FCS \| PMLCA_FCU \|
	119	PMLCA_FCM1 \| PMLCA_FCM0);
	120	u32 pmlcb = 0;
1da177e4	121
dd6c89f6	122	switch (ctr) {
1da177e4	123	case 0:
dd6c89f6 AF	124	mtpmr(PMRN_PMLCA0, pmlca);
dd6c89f6 AF	125	mtpmr(PMRN_PMLCB0, pmlcb);
1da177e4 LT	126	break;
1da177e4 LT	127	case 1:
dd6c89f6 AF	128	mtpmr(PMRN_PMLCA1, pmlca);
dd6c89f6 AF	129	mtpmr(PMRN_PMLCB1, pmlcb);
1da177e4 LT	130	break;
1da177e4 LT	131	case 2:
dd6c89f6 AF	132	mtpmr(PMRN_PMLCA2, pmlca);
dd6c89f6 AF	133	mtpmr(PMRN_PMLCB2, pmlcb);
1da177e4 LT	134	break;
1da177e4 LT	135	case 3:
dd6c89f6 AF	136	mtpmr(PMRN_PMLCA3, pmlca);
dd6c89f6 AF	137	mtpmr(PMRN_PMLCB3, pmlcb);
1da177e4 LT	138	break;
1da177e4 LT	139	default:
dd6c89f6	140	panic("Bad ctr number!\n");
1da177e4 LT	141	}
	142	}
	143
dd6c89f6 AF	144	static void set_pmc_event(int ctr, int event)
	145	{
	146	u32 pmlca;
	147
	148	pmlca = get_pmlca(ctr);
	149
	150	pmlca = (pmlca & ~PMLCA_EVENT_MASK) \|
	151	((event << PMLCA_EVENT_SHIFT) &
	152	PMLCA_EVENT_MASK);
	153
	154	set_pmlca(ctr, pmlca);
	155	}
	156
	157	static void set_pmc_user_kernel(int ctr, int user, int kernel)
	158	{
	159	u32 pmlca;
	160
	161	pmlca = get_pmlca(ctr);
	162
	163	if(user)
	164	pmlca &= ~PMLCA_FCU;
	165	else
	166	pmlca \|= PMLCA_FCU;
	167
	168	if(kernel)
	169	pmlca &= ~PMLCA_FCS;
	170	else
	171	pmlca \|= PMLCA_FCS;
	172
	173	set_pmlca(ctr, pmlca);
	174	}
	175
	176	static void set_pmc_marked(int ctr, int mark0, int mark1)
	177	{
	178	u32 pmlca = get_pmlca(ctr);
	179
	180	if(mark0)
	181	pmlca &= ~PMLCA_FCM0;
	182	else
	183	pmlca \|= PMLCA_FCM0;
	184
	185	if(mark1)
	186	pmlca &= ~PMLCA_FCM1;
	187	else
	188	pmlca \|= PMLCA_FCM1;
	189
	190	set_pmlca(ctr, pmlca);
	191	}
	192
	193	static void pmc_start_ctr(int ctr, int enable)
	194	{
	195	u32 pmlca = get_pmlca(ctr);
	196
	197	pmlca &= ~PMLCA_FC;
	198
	199	if (enable)
	200	pmlca \|= PMLCA_CE;
	201	else
	202	pmlca &= ~PMLCA_CE;
	203
	204	set_pmlca(ctr, pmlca);
	205	}
	206
	207	static void pmc_start_ctrs(int enable)
208	{
209	u32 pmgc0 = mfpmr(PMRN_PMGC0);
210
211	pmgc0 &= ~PMGC0_FAC;
212	pmgc0 \|= PMGC0_FCECE;
213
214	if (enable)
215	pmgc0 \|= PMGC0_PMIE;
216	else
217	pmgc0 &= ~PMGC0_PMIE;
218
219	mtpmr(PMRN_PMGC0, pmgc0);
220	}
221
222	static void pmc_stop_ctrs(void)
223	{
224	u32 pmgc0 = mfpmr(PMRN_PMGC0);
225
226	pmgc0 \|= PMGC0_FAC;
227
228	pmgc0 &= ~(PMGC0_PMIE \| PMGC0_FCECE);
229
230	mtpmr(PMRN_PMGC0, pmgc0);
231	}
232
233	static void dump_pmcs(void)
234	{
235	printk("pmgc0: %x\n", mfpmr(PMRN_PMGC0));
236	printk("pmc\t\tpmlca\t\tpmlcb\n");
237	printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC0),
238	mfpmr(PMRN_PMLCA0), mfpmr(PMRN_PMLCB0));
239	printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC1),
240	mfpmr(PMRN_PMLCA1), mfpmr(PMRN_PMLCB1));
241	printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC2),
242	mfpmr(PMRN_PMLCA2), mfpmr(PMRN_PMLCB2));
243	printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC3),
244	mfpmr(PMRN_PMLCA3), mfpmr(PMRN_PMLCB3));
245	}
246
1474855d	247	static int fsl_booke_cpu_setup(struct op_counter_config *ctr)
dd6c89f6 AF	248	{
	249	int i;
	250
	251	/* freeze all counters */
	252	pmc_stop_ctrs();
	253
	254	for (i = 0;i < num_counters;i++) {
	255	init_pmc_stop(i);
	256
	257	set_pmc_event(i, ctr[i].event);
	258
	259	set_pmc_user_kernel(i, ctr[i].user, ctr[i].kernel);
	260	}
1474855d BN	261
1474855d BN	262	return 0;
dd6c89f6	263	}
1da177e4	264
1474855d	265	static int fsl_booke_reg_setup(struct op_counter_config *ctr,
1da177e4 LT	266	struct op_system_config *sys,
	267	int num_ctrs)
	268	{
	269	int i;
	270
	271	num_counters = num_ctrs;
	272
1da177e4 LT	273	/* Our counters count up, and "count" refers to
	274	* how much before the next interrupt, and we interrupt
	275	* on overflow. So we calculate the starting value
	276	* which will give us "count" until overflow.
	277	* Then we set the events on the enabled counters */
dd6c89f6	278	for (i = 0; i < num_counters; ++i)
1da177e4 LT	279	reset_value[i] = 0x80000000UL - ctr[i].count;
1da177e4 LT	280
1474855d	281	return 0;
1da177e4 LT	282	}
1da177e4 LT	283
1474855d	284	static int fsl_booke_start(struct op_counter_config *ctr)
1da177e4 LT	285	{
	286	int i;
	287
	288	mtmsr(mfmsr() \| MSR_PMM);
	289
	290	for (i = 0; i < num_counters; ++i) {
	291	if (ctr[i].enabled) {
	292	ctr_write(i, reset_value[i]);
dd6c89f6 AF	293	/* Set each enabled counter to only
dd6c89f6 AF	294	* count when the Mark bit is not set */
1da177e4 LT	295	set_pmc_marked(i, 1, 0);
	296	pmc_start_ctr(i, 1);
	297	} else {
	298	ctr_write(i, 0);
	299
	300	/* Set the ctr to be stopped */
	301	pmc_start_ctr(i, 0);
	302	}
	303	}
	304
	305	/* Clear the freeze bit, and enable the interrupt.
	306	* The counters won't actually start until the rfi clears
	307	* the PMM bit */
	308	pmc_start_ctrs(1);
	309
	310	oprofile_running = 1;
	311
	312	pr_debug("start on cpu %d, pmgc0 %x\n", smp_processor_id(),
	313	mfpmr(PMRN_PMGC0));
1474855d BN	314
1474855d BN	315	return 0;
1da177e4 LT	316	}
	317
	318	static void fsl_booke_stop(void)
	319	{
	320	/* freeze counters */
	321	pmc_stop_ctrs();
	322
	323	oprofile_running = 0;
	324
	325	pr_debug("stop on cpu %d, pmgc0 %x\n", smp_processor_id(),
	326	mfpmr(PMRN_PMGC0));
	327
	328	mb();
	329	}
	330
	331
	332	static void fsl_booke_handle_interrupt(struct pt_regs *regs,
	333	struct op_counter_config *ctr)
	334	{
	335	unsigned long pc;
	336	int is_kernel;
	337	int val;
	338	int i;
	339
	340	/* set the PMM bit (see comment below) */
	341	mtmsr(mfmsr() \| MSR_PMM);
	342
	343	pc = regs->nip;
fa465f8c	344	is_kernel = is_kernel_addr(pc);
1da177e4 LT	345
	346	for (i = 0; i < num_counters; ++i) {
	347	val = ctr_read(i);
	348	if (val < 0) {
	349	if (oprofile_running && ctr[i].enabled) {
fa465f8c	350	oprofile_add_ext_sample(pc, regs, i, is_kernel);
1da177e4 LT	351	ctr_write(i, reset_value[i]);
	352	} else {
	353	ctr_write(i, 0);
	354	}
	355	}
	356	}
	357
	358	/* The freeze bit was set by the interrupt. */
	359	/* Clear the freeze bit, and reenable the interrupt.
	360	* The counters won't actually start until the rfi clears
	361	* the PMM bit */
	362	pmc_start_ctrs(1);
	363	}
	364
a3e48c10	365	struct op_powerpc_model op_model_fsl_booke = {
1da177e4	366	.reg_setup = fsl_booke_reg_setup,
dd6c89f6	367	.cpu_setup = fsl_booke_cpu_setup,
1da177e4 LT	368	.start = fsl_booke_start,
	369	.stop = fsl_booke_stop,
	370	.handle_interrupt = fsl_booke_handle_interrupt,
	371	};