[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / kvm / emulate.c

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 *
 * Copyright IBM Corp. 2007
 *
 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
 */

#include <linux/jiffies.h>
#include <linux/hrtimer.h>
#include <linux/types.h>
#include <linux/string.h>
#include <linux/kvm_host.h>

#include <asm/reg.h>
#include <asm/time.h>
#include <asm/byteorder.h>
#include <asm/kvm_ppc.h>
#include <asm/disassemble.h>
#include "timing.h"
#include "trace.h"

#define OP_TRAP 3
#define OP_TRAP_64 2

#define OP_31_XOP_LWZX      23
#define OP_31_XOP_LBZX      87
#define OP_31_XOP_STWX      151
#define OP_31_XOP_STBX      215
#define OP_31_XOP_LBZUX     119
#define OP_31_XOP_STBUX     247
#define OP_31_XOP_LHZX      279
#define OP_31_XOP_LHZUX     311
#define OP_31_XOP_MFSPR     339
#define OP_31_XOP_LHAX      343
#define OP_31_XOP_STHX      407
#define OP_31_XOP_STHUX     439
#define OP_31_XOP_MTSPR     467
#define OP_31_XOP_DCBI      470
#define OP_31_XOP_LWBRX     534
#define OP_31_XOP_TLBSYNC   566
#define OP_31_XOP_STWBRX    662
#define OP_31_XOP_LHBRX     790
#define OP_31_XOP_STHBRX    918

#define OP_LWZ  32
#define OP_LWZU 33
#define OP_LBZ  34
#define OP_LBZU 35
#define OP_STW  36
#define OP_STWU 37
#define OP_STB  38
#define OP_STBU 39
#define OP_LHZ  40
#define OP_LHZU 41
#define OP_LHA  42
#define OP_LHAU 43
#define OP_STH  44
#define OP_STHU 45

#ifdef CONFIG_PPC_BOOK3S
static int kvmppc_dec_enabled(struct kvm_vcpu *vcpu)
{
	return 1;
}
#else
static int kvmppc_dec_enabled(struct kvm_vcpu *vcpu)
{
	return vcpu->arch.tcr & TCR_DIE;
}
#endif

void kvmppc_emulate_dec(struct kvm_vcpu *vcpu)
{
	unsigned long dec_nsec;

	pr_debug("mtDEC: %x\n", vcpu->arch.dec);
#ifdef CONFIG_PPC_BOOK3S
	/* mtdec lowers the interrupt line when positive. */
	kvmppc_core_dequeue_dec(vcpu);

	/* POWER4+ triggers a dec interrupt if the value is < 0 */
	if (vcpu->arch.dec & 0x80000000) {
		hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
		kvmppc_core_queue_dec(vcpu);
		return;
	}
#endif
	if (kvmppc_dec_enabled(vcpu)) {
		/* The decrementer ticks at the same rate as the timebase, so
		 * that's how we convert the guest DEC value to the number of
		 * host ticks. */

		hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
		dec_nsec = vcpu->arch.dec;
		dec_nsec *= 1000;
		dec_nsec /= tb_ticks_per_usec;
		hrtimer_start(&vcpu->arch.dec_timer, ktime_set(0, dec_nsec),
			      HRTIMER_MODE_REL);
		vcpu->arch.dec_jiffies = get_tb();
	} else {
		hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
	}
}

u32 kvmppc_get_dec(struct kvm_vcpu *vcpu, u64 tb)
{
	u64 jd = tb - vcpu->arch.dec_jiffies;
	return vcpu->arch.dec - jd;
}

/* XXX to do:
 * lhax
 * lhaux
 * lswx
 * lswi
 * stswx
 * stswi
 * lha
 * lhau
 * lmw
 * stmw
 *
 * XXX is_bigendian should depend on MMU mapping or MSR[LE]
 */
/* XXX Should probably auto-generate instruction decoding for a particular core
 * from opcode tables in the future. */
int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu)
{
	u32 inst = kvmppc_get_last_inst(vcpu);
	u32 ea;
	int ra;
	int rb;
	int rs;
	int rt;
	int sprn;
	enum emulation_result emulated = EMULATE_DONE;
	int advance = 1;

	/* this default type might be overwritten by subcategories */
	kvmppc_set_exit_type(vcpu, EMULATED_INST_EXITS);

	pr_debug("Emulating opcode %d / %d\n", get_op(inst), get_xop(inst));

	switch (get_op(inst)) {
	case OP_TRAP:
#ifdef CONFIG_PPC_BOOK3S
	case OP_TRAP_64:
		kvmppc_core_queue_program(vcpu, SRR1_PROGTRAP);
#else
		kvmppc_core_queue_program(vcpu, vcpu->arch.esr | ESR_PTR);
#endif
		advance = 0;
		break;

	case 31:
		switch (get_xop(inst)) {

		case OP_31_XOP_LWZX:
			rt = get_rt(inst);
			emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
			break;

		case OP_31_XOP_LBZX:
			rt = get_rt(inst);
			emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
			break;

		case OP_31_XOP_LBZUX:
			rt = get_rt(inst);
			ra = get_ra(inst);
			rb = get_rb(inst);

			ea = kvmppc_get_gpr(vcpu, rb);
			if (ra)
				ea += kvmppc_get_gpr(vcpu, ra);

			emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
			kvmppc_set_gpr(vcpu, ra, ea);
			break;

		case OP_31_XOP_STWX:
			rs = get_rs(inst);
			emulated = kvmppc_handle_store(run, vcpu,
						       kvmppc_get_gpr(vcpu, rs),
			                               4, 1);
			break;

		case OP_31_XOP_STBX:
			rs = get_rs(inst);
			emulated = kvmppc_handle_store(run, vcpu,
						       kvmppc_get_gpr(vcpu, rs),
			                               1, 1);
			break;

		case OP_31_XOP_STBUX:
			rs = get_rs(inst);
			ra = get_ra(inst);
			rb = get_rb(inst);

			ea = kvmppc_get_gpr(vcpu, rb);
			if (ra)
				ea += kvmppc_get_gpr(vcpu, ra);

			emulated = kvmppc_handle_store(run, vcpu,
						       kvmppc_get_gpr(vcpu, rs),
			                               1, 1);
			kvmppc_set_gpr(vcpu, rs, ea);
			break;

		case OP_31_XOP_LHAX:
			rt = get_rt(inst);
			emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1);
			break;

		case OP_31_XOP_LHZX:
			rt = get_rt(inst);
			emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
			break;

		case OP_31_XOP_LHZUX:
			rt = get_rt(inst);
			ra = get_ra(inst);
			rb = get_rb(inst);

			ea = kvmppc_get_gpr(vcpu, rb);
			if (ra)
				ea += kvmppc_get_gpr(vcpu, ra);

			emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
			kvmppc_set_gpr(vcpu, ra, ea);
			break;

		case OP_31_XOP_MFSPR:
			sprn = get_sprn(inst);
			rt = get_rt(inst);

			switch (sprn) {
			case SPRN_SRR0:
				kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->srr0);
				break;
			case SPRN_SRR1:
				kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->srr1);
				break;
			case SPRN_PVR:
				kvmppc_set_gpr(vcpu, rt, vcpu->arch.pvr); break;
			case SPRN_PIR:
				kvmppc_set_gpr(vcpu, rt, vcpu->vcpu_id); break;
			case SPRN_MSSSR0:
				kvmppc_set_gpr(vcpu, rt, 0); break;

			/* Note: mftb and TBRL/TBWL are user-accessible, so
			 * the guest can always access the real TB anyways.
			 * In fact, we probably will never see these traps. */
			case SPRN_TBWL:
				kvmppc_set_gpr(vcpu, rt, get_tb() >> 32); break;
			case SPRN_TBWU:
				kvmppc_set_gpr(vcpu, rt, get_tb()); break;

			case SPRN_SPRG0:
				kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->sprg0);
				break;
			case SPRN_SPRG1:
				kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->sprg1);
				break;
			case SPRN_SPRG2:
				kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->sprg2);
				break;
			case SPRN_SPRG3:
				kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->sprg3);
				break;
			/* Note: SPRG4-7 are user-readable, so we don't get
			 * a trap. */

			case SPRN_DEC:
			{
				kvmppc_set_gpr(vcpu, rt,
					       kvmppc_get_dec(vcpu, get_tb()));
				break;
			}
			default:
				emulated = kvmppc_core_emulate_mfspr(vcpu, sprn, rt);
				if (emulated == EMULATE_FAIL) {
					printk("mfspr: unknown spr %x\n", sprn);
					kvmppc_set_gpr(vcpu, rt, 0);
				}
				break;
			}
			kvmppc_set_exit_type(vcpu, EMULATED_MFSPR_EXITS);
			break;

		case OP_31_XOP_STHX:
			rs = get_rs(inst);
			ra = get_ra(inst);
			rb = get_rb(inst);

			emulated = kvmppc_handle_store(run, vcpu,
						       kvmppc_get_gpr(vcpu, rs),
			                               2, 1);
			break;

		case OP_31_XOP_STHUX:
			rs = get_rs(inst);
			ra = get_ra(inst);
			rb = get_rb(inst);

			ea = kvmppc_get_gpr(vcpu, rb);
			if (ra)
				ea += kvmppc_get_gpr(vcpu, ra);

			emulated = kvmppc_handle_store(run, vcpu,
						       kvmppc_get_gpr(vcpu, rs),
			                               2, 1);
			kvmppc_set_gpr(vcpu, ra, ea);
			break;

		case OP_31_XOP_MTSPR:
			sprn = get_sprn(inst);
			rs = get_rs(inst);
			switch (sprn) {
			case SPRN_SRR0:
				vcpu->arch.shared->srr0 = kvmppc_get_gpr(vcpu, rs);
				break;
			case SPRN_SRR1:
				vcpu->arch.shared->srr1 = kvmppc_get_gpr(vcpu, rs);
				break;

			/* XXX We need to context-switch the timebase for
			 * watchdog and FIT. */
			case SPRN_TBWL: break;
			case SPRN_TBWU: break;

			case SPRN_MSSSR0: break;

			case SPRN_DEC:
				vcpu->arch.dec = kvmppc_get_gpr(vcpu, rs);
				kvmppc_emulate_dec(vcpu);
				break;

			case SPRN_SPRG0:
				vcpu->arch.shared->sprg0 = kvmppc_get_gpr(vcpu, rs);
				break;
			case SPRN_SPRG1:
				vcpu->arch.shared->sprg1 = kvmppc_get_gpr(vcpu, rs);
				break;
			case SPRN_SPRG2:
				vcpu->arch.shared->sprg2 = kvmppc_get_gpr(vcpu, rs);
				break;
			case SPRN_SPRG3:
				vcpu->arch.shared->sprg3 = kvmppc_get_gpr(vcpu, rs);
				break;

			default:
				emulated = kvmppc_core_emulate_mtspr(vcpu, sprn, rs);
				if (emulated == EMULATE_FAIL)
					printk("mtspr: unknown spr %x\n", sprn);
				break;
			}
			kvmppc_set_exit_type(vcpu, EMULATED_MTSPR_EXITS);
			break;

		case OP_31_XOP_DCBI:
			/* Do nothing. The guest is performing dcbi because
			 * hardware DMA is not snooped by the dcache, but
			 * emulated DMA either goes through the dcache as
			 * normal writes, or the host kernel has handled dcache
			 * coherence. */
			break;

		case OP_31_XOP_LWBRX:
			rt = get_rt(inst);
			emulated = kvmppc_handle_load(run, vcpu, rt, 4, 0);
			break;

		case OP_31_XOP_TLBSYNC:
			break;

		case OP_31_XOP_STWBRX:
			rs = get_rs(inst);
			ra = get_ra(inst);
			rb = get_rb(inst);

			emulated = kvmppc_handle_store(run, vcpu,
						       kvmppc_get_gpr(vcpu, rs),
			                               4, 0);
			break;

		case OP_31_XOP_LHBRX:
			rt = get_rt(inst);
			emulated = kvmppc_handle_load(run, vcpu, rt, 2, 0);
			break;

		case OP_31_XOP_STHBRX:
			rs = get_rs(inst);
			ra = get_ra(inst);
			rb = get_rb(inst);

			emulated = kvmppc_handle_store(run, vcpu,
						       kvmppc_get_gpr(vcpu, rs),
			                               2, 0);
			break;

		default:
			/* Attempt core-specific emulation below. */
			emulated = EMULATE_FAIL;
		}
		break;

	case OP_LWZ:
		rt = get_rt(inst);
		emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
		break;

	case OP_LWZU:
		ra = get_ra(inst);
		rt = get_rt(inst);
		emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
		kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
		break;

	case OP_LBZ:
		rt = get_rt(inst);
		emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
		break;

	case OP_LBZU:
		ra = get_ra(inst);
		rt = get_rt(inst);
		emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
		kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
		break;

	case OP_STW:
		rs = get_rs(inst);
		emulated = kvmppc_handle_store(run, vcpu,
					       kvmppc_get_gpr(vcpu, rs),
		                               4, 1);
		break;

	case OP_STWU:
		ra = get_ra(inst);
		rs = get_rs(inst);
		emulated = kvmppc_handle_store(run, vcpu,
					       kvmppc_get_gpr(vcpu, rs),
		                               4, 1);
		kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
		break;

	case OP_STB:
		rs = get_rs(inst);
		emulated = kvmppc_handle_store(run, vcpu,
					       kvmppc_get_gpr(vcpu, rs),
		                               1, 1);
		break;

	case OP_STBU:
		ra = get_ra(inst);
		rs = get_rs(inst);
		emulated = kvmppc_handle_store(run, vcpu,
					       kvmppc_get_gpr(vcpu, rs),
		                               1, 1);
		kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
		break;

	case OP_LHZ:
		rt = get_rt(inst);
		emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
		break;

	case OP_LHZU:
		ra = get_ra(inst);
		rt = get_rt(inst);
		emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
		kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
		break;

	case OP_LHA:
		rt = get_rt(inst);
		emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1);
		break;

	case OP_LHAU:
		ra = get_ra(inst);
		rt = get_rt(inst);
		emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1);
		kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
		break;

	case OP_STH:
		rs = get_rs(inst);
		emulated = kvmppc_handle_store(run, vcpu,
					       kvmppc_get_gpr(vcpu, rs),
		                               2, 1);
		break;

	case OP_STHU:
		ra = get_ra(inst);
		rs = get_rs(inst);
		emulated = kvmppc_handle_store(run, vcpu,
					       kvmppc_get_gpr(vcpu, rs),
		                               2, 1);
		kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
		break;

	default:
		emulated = EMULATE_FAIL;
	}

	if (emulated == EMULATE_FAIL) {
		emulated = kvmppc_core_emulate_op(run, vcpu, inst, &advance);
		if (emulated == EMULATE_AGAIN) {
			advance = 0;
		} else if (emulated == EMULATE_FAIL) {
			advance = 0;
			printk(KERN_ERR "Couldn't emulate instruction 0x%08x "
			       "(op %d xop %d)\n", inst, get_op(inst), get_xop(inst));
			kvmppc_core_queue_program(vcpu, 0);
		}
	}

	trace_kvm_ppc_instr(inst, kvmppc_get_pc(vcpu), emulated);

	/* Advance past emulated instruction. */
	if (advance)
		kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + 4);

	return emulated;
}
Commit	Line	Data
bbf45ba5 HB	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License, version 2, as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope that it will be useful,
	7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	9	* GNU General Public License for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License
	12	* along with this program; if not, write to the Free Software
	13	* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
	14	*
	15	* Copyright IBM Corp. 2007
	16	*
	17	* Authors: Hollis Blanchard <hollisb@us.ibm.com>
	18	*/
	19
	20	#include <linux/jiffies.h>
544c6761	21	#include <linux/hrtimer.h>
bbf45ba5 HB	22	#include <linux/types.h>
	23	#include <linux/string.h>
	24	#include <linux/kvm_host.h>
	25
75f74f0d	26	#include <asm/reg.h>
bbf45ba5 HB	27	#include <asm/time.h>
	28	#include <asm/byteorder.h>
	29	#include <asm/kvm_ppc.h>
c381a043	30	#include <asm/disassemble.h>
73e75b41	31	#include "timing.h"
46f43c6e	32	#include "trace.h"
bbf45ba5	33
cea5d8c9	34	#define OP_TRAP 3
513579e3	35	#define OP_TRAP_64 2
cea5d8c9 HB	36
	37	#define OP_31_XOP_LWZX 23
	38	#define OP_31_XOP_LBZX 87
	39	#define OP_31_XOP_STWX 151
	40	#define OP_31_XOP_STBX 215
1c85e733	41	#define OP_31_XOP_LBZUX 119
cea5d8c9 HB	42	#define OP_31_XOP_STBUX 247
	43	#define OP_31_XOP_LHZX 279
	44	#define OP_31_XOP_LHZUX 311
	45	#define OP_31_XOP_MFSPR 339
1c85e733	46	#define OP_31_XOP_LHAX 343
cea5d8c9 HB	47	#define OP_31_XOP_STHX 407
	48	#define OP_31_XOP_STHUX 439
	49	#define OP_31_XOP_MTSPR 467
	50	#define OP_31_XOP_DCBI 470
	51	#define OP_31_XOP_LWBRX 534
	52	#define OP_31_XOP_TLBSYNC 566
	53	#define OP_31_XOP_STWBRX 662
	54	#define OP_31_XOP_LHBRX 790
	55	#define OP_31_XOP_STHBRX 918
	56
	57	#define OP_LWZ 32
	58	#define OP_LWZU 33
	59	#define OP_LBZ 34
	60	#define OP_LBZU 35
	61	#define OP_STW 36
	62	#define OP_STWU 37
	63	#define OP_STB 38
	64	#define OP_STBU 39
	65	#define OP_LHZ 40
	66	#define OP_LHZU 41
3587d534 AG	67	#define OP_LHA 42
3587d534 AG	68	#define OP_LHAU 43
cea5d8c9 HB	69	#define OP_STH 44
	70	#define OP_STHU 45
	71
00c3a37c	72	#ifdef CONFIG_PPC_BOOK3S
513579e3 AG	73	static int kvmppc_dec_enabled(struct kvm_vcpu *vcpu)
	74	{
	75	return 1;
	76	}
	77	#else
	78	static int kvmppc_dec_enabled(struct kvm_vcpu *vcpu)
	79	{
	80	return vcpu->arch.tcr & TCR_DIE;
	81	}
	82	#endif
	83
75f74f0d	84	void kvmppc_emulate_dec(struct kvm_vcpu *vcpu)
bbf45ba5	85	{
544c6761	86	unsigned long dec_nsec;
9a7a9b09	87
544c6761	88	pr_debug("mtDEC: %x\n", vcpu->arch.dec);
00c3a37c	89	#ifdef CONFIG_PPC_BOOK3S
7706664d AG	90	/* mtdec lowers the interrupt line when positive. */
	91	kvmppc_core_dequeue_dec(vcpu);
	92
513579e3 AG	93	/* POWER4+ triggers a dec interrupt if the value is < 0 */
513579e3 AG	94	if (vcpu->arch.dec & 0x80000000) {
544c6761	95	hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
513579e3 AG	96	kvmppc_core_queue_dec(vcpu);
	97	return;
	98	}
	99	#endif
	100	if (kvmppc_dec_enabled(vcpu)) {
bbf45ba5 HB	101	/* The decrementer ticks at the same rate as the timebase, so
	102	* that's how we convert the guest DEC value to the number of
	103	* host ticks. */
bbf45ba5	104
544c6761 AG	105	hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
	106	dec_nsec = vcpu->arch.dec;
	107	dec_nsec *= 1000;
	108	dec_nsec /= tb_ticks_per_usec;
	109	hrtimer_start(&vcpu->arch.dec_timer, ktime_set(0, dec_nsec),
	110	HRTIMER_MODE_REL);
513579e3	111	vcpu->arch.dec_jiffies = get_tb();
bbf45ba5	112	} else {
544c6761	113	hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
bbf45ba5 HB	114	}
	115	}
	116
5ce941ee SW	117	u32 kvmppc_get_dec(struct kvm_vcpu *vcpu, u64 tb)
	118	{
	119	u64 jd = tb - vcpu->arch.dec_jiffies;
	120	return vcpu->arch.dec - jd;
	121	}
	122
bbf45ba5 HB	123	/* XXX to do:
	124	* lhax
	125	* lhaux
	126	* lswx
	127	* lswi
	128	* stswx
	129	* stswi
	130	* lha
	131	* lhau
	132	* lmw
	133	* stmw
	134	*
	135	* XXX is_bigendian should depend on MMU mapping or MSR[LE]
	136	*/
75f74f0d HB	137	/* XXX Should probably auto-generate instruction decoding for a particular core
75f74f0d HB	138	* from opcode tables in the future. */
bbf45ba5 HB	139	int kvmppc_emulate_instruction(struct kvm_run run, struct kvm_vcpu vcpu)
bbf45ba5 HB	140	{
c7f38f46	141	u32 inst = kvmppc_get_last_inst(vcpu);
bbf45ba5 HB	142	u32 ea;
	143	int ra;
	144	int rb;
bbf45ba5 HB	145	int rs;
	146	int rt;
	147	int sprn;
bbf45ba5 HB	148	enum emulation_result emulated = EMULATE_DONE;
	149	int advance = 1;
	150
73e75b41 HB	151	/* this default type might be overwritten by subcategories */
	152	kvmppc_set_exit_type(vcpu, EMULATED_INST_EXITS);
	153
689fd14a	154	pr_debug("Emulating opcode %d / %d\n", get_op(inst), get_xop(inst));
513579e3	155
bbf45ba5	156	switch (get_op(inst)) {
cea5d8c9	157	case OP_TRAP:
00c3a37c	158	#ifdef CONFIG_PPC_BOOK3S
513579e3	159	case OP_TRAP_64:
daf5e271	160	kvmppc_core_queue_program(vcpu, SRR1_PROGTRAP);
513579e3	161	#else
daf5e271	162	kvmppc_core_queue_program(vcpu, vcpu->arch.esr \| ESR_PTR);
513579e3	163	#endif
bbf45ba5 HB	164	advance = 0;
	165	break;
	166
bbf45ba5 HB	167	case 31:
	168	switch (get_xop(inst)) {
	169
cea5d8c9	170	case OP_31_XOP_LWZX:
ac3cd34e HB	171	rt = get_rt(inst);
	172	emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
	173	break;
	174
cea5d8c9	175	case OP_31_XOP_LBZX:
bbf45ba5 HB	176	rt = get_rt(inst);
	177	emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
	178	break;
	179
1c85e733 AG	180	case OP_31_XOP_LBZUX:
	181	rt = get_rt(inst);
	182	ra = get_ra(inst);
	183	rb = get_rb(inst);
	184
	185	ea = kvmppc_get_gpr(vcpu, rb);
	186	if (ra)
	187	ea += kvmppc_get_gpr(vcpu, ra);
	188
	189	emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
	190	kvmppc_set_gpr(vcpu, ra, ea);
	191	break;
	192
cea5d8c9	193	case OP_31_XOP_STWX:
ac3cd34e HB	194	rs = get_rs(inst);
ac3cd34e HB	195	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5	196	kvmppc_get_gpr(vcpu, rs),
ac3cd34e HB	197	4, 1);
	198	break;
	199
cea5d8c9	200	case OP_31_XOP_STBX:
bbf45ba5 HB	201	rs = get_rs(inst);
bbf45ba5 HB	202	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5	203	kvmppc_get_gpr(vcpu, rs),
bbf45ba5 HB	204	1, 1);
	205	break;
	206
cea5d8c9	207	case OP_31_XOP_STBUX:
bbf45ba5 HB	208	rs = get_rs(inst);
	209	ra = get_ra(inst);
	210	rb = get_rb(inst);
	211
8e5b26b5	212	ea = kvmppc_get_gpr(vcpu, rb);
bbf45ba5	213	if (ra)
8e5b26b5	214	ea += kvmppc_get_gpr(vcpu, ra);
bbf45ba5 HB	215
bbf45ba5 HB	216	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5	217	kvmppc_get_gpr(vcpu, rs),
bbf45ba5	218	1, 1);
8e5b26b5	219	kvmppc_set_gpr(vcpu, rs, ea);
bbf45ba5 HB	220	break;
bbf45ba5 HB	221
1c85e733 AG	222	case OP_31_XOP_LHAX:
	223	rt = get_rt(inst);
	224	emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1);
	225	break;
	226
cea5d8c9	227	case OP_31_XOP_LHZX:
bbf45ba5 HB	228	rt = get_rt(inst);
	229	emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
	230	break;
	231
cea5d8c9	232	case OP_31_XOP_LHZUX:
bbf45ba5 HB	233	rt = get_rt(inst);
	234	ra = get_ra(inst);
	235	rb = get_rb(inst);
	236
8e5b26b5	237	ea = kvmppc_get_gpr(vcpu, rb);
bbf45ba5	238	if (ra)
8e5b26b5	239	ea += kvmppc_get_gpr(vcpu, ra);
bbf45ba5 HB	240
bbf45ba5 HB	241	emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
8e5b26b5	242	kvmppc_set_gpr(vcpu, ra, ea);
bbf45ba5 HB	243	break;
bbf45ba5 HB	244
cea5d8c9	245	case OP_31_XOP_MFSPR:
bbf45ba5 HB	246	sprn = get_sprn(inst);
	247	rt = get_rt(inst);
	248
	249	switch (sprn) {
	250	case SPRN_SRR0:
de7906c3 AG	251	kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->srr0);
de7906c3 AG	252	break;
bbf45ba5	253	case SPRN_SRR1:
de7906c3 AG	254	kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->srr1);
de7906c3 AG	255	break;
bbf45ba5	256	case SPRN_PVR:
8e5b26b5	257	kvmppc_set_gpr(vcpu, rt, vcpu->arch.pvr); break;
06579dd9	258	case SPRN_PIR:
8e5b26b5	259	kvmppc_set_gpr(vcpu, rt, vcpu->vcpu_id); break;
513579e3	260	case SPRN_MSSSR0:
8e5b26b5	261	kvmppc_set_gpr(vcpu, rt, 0); break;
bbf45ba5 HB	262
	263	/* Note: mftb and TBRL/TBWL are user-accessible, so
	264	* the guest can always access the real TB anyways.
	265	* In fact, we probably will never see these traps. */
	266	case SPRN_TBWL:
8e5b26b5	267	kvmppc_set_gpr(vcpu, rt, get_tb() >> 32); break;
bbf45ba5	268	case SPRN_TBWU:
8e5b26b5	269	kvmppc_set_gpr(vcpu, rt, get_tb()); break;
bbf45ba5 HB	270
bbf45ba5 HB	271	case SPRN_SPRG0:
a73a9599 AG	272	kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->sprg0);
a73a9599 AG	273	break;
bbf45ba5	274	case SPRN_SPRG1:
a73a9599 AG	275	kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->sprg1);
a73a9599 AG	276	break;
bbf45ba5	277	case SPRN_SPRG2:
a73a9599 AG	278	kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->sprg2);
a73a9599 AG	279	break;
bbf45ba5	280	case SPRN_SPRG3:
a73a9599 AG	281	kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->sprg3);
a73a9599 AG	282	break;
bbf45ba5 HB	283	/* Note: SPRG4-7 are user-readable, so we don't get
	284	* a trap. */
	285
9a7a9b09 AG	286	case SPRN_DEC:
9a7a9b09 AG	287	{
5ce941ee SW	288	kvmppc_set_gpr(vcpu, rt,
5ce941ee SW	289	kvmppc_get_dec(vcpu, get_tb()));
9a7a9b09 AG	290	break;
9a7a9b09 AG	291	}
bbf45ba5	292	default:
75f74f0d HB	293	emulated = kvmppc_core_emulate_mfspr(vcpu, sprn, rt);
	294	if (emulated == EMULATE_FAIL) {
	295	printk("mfspr: unknown spr %x\n", sprn);
8e5b26b5	296	kvmppc_set_gpr(vcpu, rt, 0);
75f74f0d	297	}
bbf45ba5 HB	298	break;
bbf45ba5 HB	299	}
49ea0695	300	kvmppc_set_exit_type(vcpu, EMULATED_MFSPR_EXITS);
bbf45ba5 HB	301	break;
bbf45ba5 HB	302
cea5d8c9	303	case OP_31_XOP_STHX:
bbf45ba5 HB	304	rs = get_rs(inst);
	305	ra = get_ra(inst);
	306	rb = get_rb(inst);
	307
	308	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5	309	kvmppc_get_gpr(vcpu, rs),
bbf45ba5 HB	310	2, 1);
	311	break;
	312
cea5d8c9	313	case OP_31_XOP_STHUX:
bbf45ba5 HB	314	rs = get_rs(inst);
	315	ra = get_ra(inst);
	316	rb = get_rb(inst);
	317
8e5b26b5	318	ea = kvmppc_get_gpr(vcpu, rb);
bbf45ba5	319	if (ra)
8e5b26b5	320	ea += kvmppc_get_gpr(vcpu, ra);
bbf45ba5 HB	321
bbf45ba5 HB	322	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5	323	kvmppc_get_gpr(vcpu, rs),
bbf45ba5	324	2, 1);
8e5b26b5	325	kvmppc_set_gpr(vcpu, ra, ea);
bbf45ba5 HB	326	break;
bbf45ba5 HB	327
cea5d8c9	328	case OP_31_XOP_MTSPR:
bbf45ba5 HB	329	sprn = get_sprn(inst);
	330	rs = get_rs(inst);
	331	switch (sprn) {
	332	case SPRN_SRR0:
de7906c3 AG	333	vcpu->arch.shared->srr0 = kvmppc_get_gpr(vcpu, rs);
de7906c3 AG	334	break;
bbf45ba5	335	case SPRN_SRR1:
de7906c3 AG	336	vcpu->arch.shared->srr1 = kvmppc_get_gpr(vcpu, rs);
de7906c3 AG	337	break;
bbf45ba5 HB	338
	339	/* XXX We need to context-switch the timebase for
	340	* watchdog and FIT. */
	341	case SPRN_TBWL: break;
	342	case SPRN_TBWU: break;
	343
513579e3 AG	344	case SPRN_MSSSR0: break;
513579e3 AG	345
bbf45ba5	346	case SPRN_DEC:
8e5b26b5	347	vcpu->arch.dec = kvmppc_get_gpr(vcpu, rs);
bbf45ba5 HB	348	kvmppc_emulate_dec(vcpu);
	349	break;
	350
bbf45ba5	351	case SPRN_SPRG0:
a73a9599 AG	352	vcpu->arch.shared->sprg0 = kvmppc_get_gpr(vcpu, rs);
a73a9599 AG	353	break;
bbf45ba5	354	case SPRN_SPRG1:
a73a9599 AG	355	vcpu->arch.shared->sprg1 = kvmppc_get_gpr(vcpu, rs);
a73a9599 AG	356	break;
bbf45ba5	357	case SPRN_SPRG2:
a73a9599 AG	358	vcpu->arch.shared->sprg2 = kvmppc_get_gpr(vcpu, rs);
a73a9599 AG	359	break;
bbf45ba5	360	case SPRN_SPRG3:
a73a9599 AG	361	vcpu->arch.shared->sprg3 = kvmppc_get_gpr(vcpu, rs);
a73a9599 AG	362	break;
bbf45ba5	363
bbf45ba5	364	default:
75f74f0d HB	365	emulated = kvmppc_core_emulate_mtspr(vcpu, sprn, rs);
	366	if (emulated == EMULATE_FAIL)
	367	printk("mtspr: unknown spr %x\n", sprn);
bbf45ba5 HB	368	break;
bbf45ba5 HB	369	}
49ea0695	370	kvmppc_set_exit_type(vcpu, EMULATED_MTSPR_EXITS);
bbf45ba5 HB	371	break;
bbf45ba5 HB	372
cea5d8c9	373	case OP_31_XOP_DCBI:
bbf45ba5 HB	374	/* Do nothing. The guest is performing dcbi because
	375	* hardware DMA is not snooped by the dcache, but
	376	* emulated DMA either goes through the dcache as
	377	* normal writes, or the host kernel has handled dcache
	378	* coherence. */
	379	break;
	380
cea5d8c9	381	case OP_31_XOP_LWBRX:
bbf45ba5 HB	382	rt = get_rt(inst);
	383	emulated = kvmppc_handle_load(run, vcpu, rt, 4, 0);
	384	break;
	385
cea5d8c9	386	case OP_31_XOP_TLBSYNC:
bbf45ba5 HB	387	break;
bbf45ba5 HB	388
cea5d8c9	389	case OP_31_XOP_STWBRX:
bbf45ba5 HB	390	rs = get_rs(inst);
	391	ra = get_ra(inst);
	392	rb = get_rb(inst);
	393
	394	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5	395	kvmppc_get_gpr(vcpu, rs),
bbf45ba5 HB	396	4, 0);
	397	break;
	398
cea5d8c9	399	case OP_31_XOP_LHBRX:
bbf45ba5 HB	400	rt = get_rt(inst);
	401	emulated = kvmppc_handle_load(run, vcpu, rt, 2, 0);
	402	break;
	403
cea5d8c9	404	case OP_31_XOP_STHBRX:
bbf45ba5 HB	405	rs = get_rs(inst);
	406	ra = get_ra(inst);
	407	rb = get_rb(inst);
	408
	409	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5	410	kvmppc_get_gpr(vcpu, rs),
bbf45ba5 HB	411	2, 0);
	412	break;
	413
bbf45ba5	414	default:
75f74f0d	415	/* Attempt core-specific emulation below. */
bbf45ba5	416	emulated = EMULATE_FAIL;
bbf45ba5 HB	417	}
	418	break;
	419
cea5d8c9	420	case OP_LWZ:
bbf45ba5 HB	421	rt = get_rt(inst);
	422	emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
	423	break;
	424
cea5d8c9	425	case OP_LWZU:
bbf45ba5 HB	426	ra = get_ra(inst);
	427	rt = get_rt(inst);
	428	emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
8e5b26b5	429	kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
bbf45ba5 HB	430	break;
bbf45ba5 HB	431
cea5d8c9	432	case OP_LBZ:
bbf45ba5 HB	433	rt = get_rt(inst);
	434	emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
	435	break;
	436
cea5d8c9	437	case OP_LBZU:
bbf45ba5 HB	438	ra = get_ra(inst);
	439	rt = get_rt(inst);
	440	emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
8e5b26b5	441	kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
bbf45ba5 HB	442	break;
bbf45ba5 HB	443
cea5d8c9	444	case OP_STW:
bbf45ba5	445	rs = get_rs(inst);
8e5b26b5 AG	446	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5 AG	447	kvmppc_get_gpr(vcpu, rs),
bbf45ba5 HB	448	4, 1);
	449	break;
	450
cea5d8c9	451	case OP_STWU:
bbf45ba5 HB	452	ra = get_ra(inst);
bbf45ba5 HB	453	rs = get_rs(inst);
8e5b26b5 AG	454	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5 AG	455	kvmppc_get_gpr(vcpu, rs),
bbf45ba5	456	4, 1);
8e5b26b5	457	kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
bbf45ba5 HB	458	break;
bbf45ba5 HB	459
cea5d8c9	460	case OP_STB:
bbf45ba5	461	rs = get_rs(inst);
8e5b26b5 AG	462	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5 AG	463	kvmppc_get_gpr(vcpu, rs),
bbf45ba5 HB	464	1, 1);
	465	break;
	466
cea5d8c9	467	case OP_STBU:
bbf45ba5 HB	468	ra = get_ra(inst);
bbf45ba5 HB	469	rs = get_rs(inst);
8e5b26b5 AG	470	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5 AG	471	kvmppc_get_gpr(vcpu, rs),
bbf45ba5	472	1, 1);
8e5b26b5	473	kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
bbf45ba5 HB	474	break;
bbf45ba5 HB	475
cea5d8c9	476	case OP_LHZ:
bbf45ba5 HB	477	rt = get_rt(inst);
	478	emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
	479	break;
	480
cea5d8c9	481	case OP_LHZU:
bbf45ba5 HB	482	ra = get_ra(inst);
	483	rt = get_rt(inst);
	484	emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
8e5b26b5	485	kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
bbf45ba5 HB	486	break;
bbf45ba5 HB	487
3587d534 AG	488	case OP_LHA:
	489	rt = get_rt(inst);
	490	emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1);
	491	break;
	492
	493	case OP_LHAU:
	494	ra = get_ra(inst);
	495	rt = get_rt(inst);
	496	emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1);
	497	kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
	498	break;
	499
cea5d8c9	500	case OP_STH:
bbf45ba5	501	rs = get_rs(inst);
8e5b26b5 AG	502	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5 AG	503	kvmppc_get_gpr(vcpu, rs),
bbf45ba5 HB	504	2, 1);
	505	break;
	506
cea5d8c9	507	case OP_STHU:
bbf45ba5 HB	508	ra = get_ra(inst);
bbf45ba5 HB	509	rs = get_rs(inst);
8e5b26b5 AG	510	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5 AG	511	kvmppc_get_gpr(vcpu, rs),
bbf45ba5	512	2, 1);
8e5b26b5	513	kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
bbf45ba5 HB	514	break;
	515
	516	default:
bbf45ba5	517	emulated = EMULATE_FAIL;
75f74f0d HB	518	}
	519
	520	if (emulated == EMULATE_FAIL) {
	521	emulated = kvmppc_core_emulate_op(run, vcpu, inst, &advance);
37f5bca6 AG	522	if (emulated == EMULATE_AGAIN) {
	523	advance = 0;
	524	} else if (emulated == EMULATE_FAIL) {
75f74f0d HB	525	advance = 0;
	526	printk(KERN_ERR "Couldn't emulate instruction 0x%08x "
	527	"(op %d xop %d)\n", inst, get_op(inst), get_xop(inst));
5f2b105a	528	kvmppc_core_queue_program(vcpu, 0);
75f74f0d	529	}
bbf45ba5 HB	530	}
bbf45ba5 HB	531
c7f38f46	532	trace_kvm_ppc_instr(inst, kvmppc_get_pc(vcpu), emulated);
3b4bd796	533
c7f38f46	534	/* Advance past emulated instruction. */
bbf45ba5	535	if (advance)
c7f38f46	536	kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + 4);
bbf45ba5 HB	537
	538	return emulated;
	539	}