[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / sgi-ip32 / ip32-irq.c

/*
 * Code to handle IP32 IRQs
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000 Harald Koerfgen
 * Copyright (C) 2001 Keith M Wesolowski
 */
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/bitops.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/random.h>
#include <linux/sched.h>

#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/signal.h>
#include <asm/system.h>
#include <asm/time.h>
#include <asm/ip32/crime.h>
#include <asm/ip32/mace.h>
#include <asm/ip32/ip32_ints.h>

/* issue a PIO read to make sure no PIO writes are pending */
static void inline flush_crime_bus(void)
{
	crime->control;
}

static void inline flush_mace_bus(void)
{
	mace->perif.ctrl.misc;
}

/*
 * O2 irq map
 *
 * IP0 -> software (ignored)
 * IP1 -> software (ignored)
 * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
 * IP3 -> (irq1) X unknown
 * IP4 -> (irq2) X unknown
 * IP5 -> (irq3) X unknown
 * IP6 -> (irq4) X unknown
 * IP7 -> (irq5) 7 CPU count/compare timer (system timer)
 *
 * crime: (C)
 *
 * CRIME_INT_STAT 31:0:
 *
 * 0  ->  8  Video in 1
 * 1  ->  9 Video in 2
 * 2  -> 10  Video out
 * 3  -> 11  Mace ethernet
 * 4  -> S  SuperIO sub-interrupt
 * 5  -> M  Miscellaneous sub-interrupt
 * 6  -> A  Audio sub-interrupt
 * 7  -> 15  PCI bridge errors
 * 8  -> 16  PCI SCSI aic7xxx 0
 * 9  -> 17 PCI SCSI aic7xxx 1
 * 10 -> 18 PCI slot 0
 * 11 -> 19 unused (PCI slot 1)
 * 12 -> 20 unused (PCI slot 2)
 * 13 -> 21 unused (PCI shared 0)
 * 14 -> 22 unused (PCI shared 1)
 * 15 -> 23 unused (PCI shared 2)
 * 16 -> 24 GBE0 (E)
 * 17 -> 25 GBE1 (E)
 * 18 -> 26 GBE2 (E)
 * 19 -> 27 GBE3 (E)
 * 20 -> 28 CPU errors
 * 21 -> 29 Memory errors
 * 22 -> 30 RE empty edge (E)
 * 23 -> 31 RE full edge (E)
 * 24 -> 32 RE idle edge (E)
 * 25 -> 33 RE empty level
 * 26 -> 34 RE full level
 * 27 -> 35 RE idle level
 * 28 -> 36 unused (software 0) (E)
 * 29 -> 37 unused (software 1) (E)
 * 30 -> 38 unused (software 2) - crime 1.5 CPU SysCorError (E)
 * 31 -> 39 VICE
 *
 * S, M, A: Use the MACE ISA interrupt register
 * MACE_ISA_INT_STAT 31:0
 *
 * 0-7 -> 40-47 Audio
 * 8 -> 48 RTC
 * 9 -> 49 Keyboard
 * 10 -> X Keyboard polled
 * 11 -> 51 Mouse
 * 12 -> X Mouse polled
 * 13-15 -> 53-55 Count/compare timers
 * 16-19 -> 56-59 Parallel (16 E)
 * 20-25 -> 60-62 Serial 1 (22 E)
 * 26-31 -> 66-71 Serial 2 (28 E)
 *
 * Note that this means IRQs 12-14, 50, and 52 do not exist.  This is a
 * different IRQ map than IRIX uses, but that's OK as Linux irq handling
 * is quite different anyway.
 */

/* Some initial interrupts to set up */
extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);

static struct irqaction memerr_irq = {
	.handler = crime_memerr_intr,
	.flags = IRQF_DISABLED,
	.name = "CRIME memory error",
};

static struct irqaction cpuerr_irq = {
	.handler = crime_cpuerr_intr,
	.flags = IRQF_DISABLED,
	.name = "CRIME CPU error",
};

/*
 * This is for pure CRIME interrupts - ie not MACE.  The advantage?
 * We get to split the register in half and do faster lookups.
 */

static uint64_t crime_mask;

static inline void crime_enable_irq(unsigned int irq)
{
	unsigned int bit = irq - CRIME_IRQ_BASE;

	crime_mask |= 1 << bit;
	crime->imask = crime_mask;
}

static inline void crime_disable_irq(unsigned int irq)
{
	unsigned int bit = irq - CRIME_IRQ_BASE;

	crime_mask &= ~(1 << bit);
	crime->imask = crime_mask;
	flush_crime_bus();
}

static void crime_level_mask_and_ack_irq(unsigned int irq)
{
	crime_disable_irq(irq);
}

static void crime_level_end_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		crime_enable_irq(irq);
}

static struct irq_chip crime_level_interrupt = {
	.name		= "IP32 CRIME",
	.ack		= crime_level_mask_and_ack_irq,
	.mask		= crime_disable_irq,
	.mask_ack	= crime_level_mask_and_ack_irq,
	.unmask		= crime_enable_irq,
	.end		= crime_level_end_irq,
};

static void crime_edge_mask_and_ack_irq(unsigned int irq)
{
	unsigned int bit = irq - CRIME_IRQ_BASE;
	uint64_t crime_int;

	/* Edge triggered interrupts must be cleared. */

	crime_int = crime->hard_int;
	crime_int &= ~(1 << bit);
	crime->hard_int = crime_int;

	crime_disable_irq(irq);
}

static void crime_edge_end_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		crime_enable_irq(irq);
}

static struct irq_chip crime_edge_interrupt = {
	.name		= "IP32 CRIME",
	.ack		= crime_edge_mask_and_ack_irq,
	.mask		= crime_disable_irq,
	.mask_ack	= crime_edge_mask_and_ack_irq,
	.unmask		= crime_enable_irq,
	.end		= crime_edge_end_irq,
};

/*
 * This is for MACE PCI interrupts.  We can decrease bus traffic by masking
 * as close to the source as possible.  This also means we can take the
 * next chunk of the CRIME register in one piece.
 */

static unsigned long macepci_mask;

static void enable_macepci_irq(unsigned int irq)
{
	macepci_mask |= MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ);
	mace->pci.control = macepci_mask;
	crime_mask |= 1 << (irq - CRIME_IRQ_BASE);
	crime->imask = crime_mask;
}

static void disable_macepci_irq(unsigned int irq)
{
	crime_mask &= ~(1 << (irq - CRIME_IRQ_BASE));
	crime->imask = crime_mask;
	flush_crime_bus();
	macepci_mask &= ~MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ);
	mace->pci.control = macepci_mask;
	flush_mace_bus();
}

static void end_macepci_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
		enable_macepci_irq(irq);
}

static struct irq_chip ip32_macepci_interrupt = {
	.name = "IP32 MACE PCI",
	.ack = disable_macepci_irq,
	.mask = disable_macepci_irq,
	.mask_ack = disable_macepci_irq,
	.unmask = enable_macepci_irq,
	.end = end_macepci_irq,
};

/* This is used for MACE ISA interrupts.  That means bits 4-6 in the
 * CRIME register.
 */

#define MACEISA_AUDIO_INT	(MACEISA_AUDIO_SW_INT |		\
				 MACEISA_AUDIO_SC_INT |		\
				 MACEISA_AUDIO1_DMAT_INT |	\
				 MACEISA_AUDIO1_OF_INT |	\
				 MACEISA_AUDIO2_DMAT_INT |	\
				 MACEISA_AUDIO2_MERR_INT |	\
				 MACEISA_AUDIO3_DMAT_INT |	\
				 MACEISA_AUDIO3_MERR_INT)
#define MACEISA_MISC_INT	(MACEISA_RTC_INT |		\
				 MACEISA_KEYB_INT |		\
				 MACEISA_KEYB_POLL_INT |	\
				 MACEISA_MOUSE_INT |		\
				 MACEISA_MOUSE_POLL_INT |	\
				 MACEISA_TIMER0_INT |		\
				 MACEISA_TIMER1_INT |		\
				 MACEISA_TIMER2_INT)
#define MACEISA_SUPERIO_INT	(MACEISA_PARALLEL_INT |		\
				 MACEISA_PAR_CTXA_INT |		\
				 MACEISA_PAR_CTXB_INT |		\
				 MACEISA_PAR_MERR_INT |		\
				 MACEISA_SERIAL1_INT |		\
				 MACEISA_SERIAL1_TDMAT_INT |	\
				 MACEISA_SERIAL1_TDMAPR_INT |	\
				 MACEISA_SERIAL1_TDMAME_INT |	\
				 MACEISA_SERIAL1_RDMAT_INT |	\
				 MACEISA_SERIAL1_RDMAOR_INT |	\
				 MACEISA_SERIAL2_INT |		\
				 MACEISA_SERIAL2_TDMAT_INT |	\
				 MACEISA_SERIAL2_TDMAPR_INT |	\
				 MACEISA_SERIAL2_TDMAME_INT |	\
				 MACEISA_SERIAL2_RDMAT_INT |	\
				 MACEISA_SERIAL2_RDMAOR_INT)

static unsigned long maceisa_mask;

static void enable_maceisa_irq(unsigned int irq)
{
	unsigned int crime_int = 0;

	pr_debug("maceisa enable: %u\n", irq);

	switch (irq) {
	case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
		crime_int = MACE_AUDIO_INT;
		break;
	case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
		crime_int = MACE_MISC_INT;
		break;
	case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
		crime_int = MACE_SUPERIO_INT;
		break;
	}
	pr_debug("crime_int %08x enabled\n", crime_int);
	crime_mask |= crime_int;
	crime->imask = crime_mask;
	maceisa_mask |= 1 << (irq - MACEISA_AUDIO_SW_IRQ);
	mace->perif.ctrl.imask = maceisa_mask;
}

static void disable_maceisa_irq(unsigned int irq)
{
	unsigned int crime_int = 0;

	maceisa_mask &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
        if (!(maceisa_mask & MACEISA_AUDIO_INT))
		crime_int |= MACE_AUDIO_INT;
        if (!(maceisa_mask & MACEISA_MISC_INT))
		crime_int |= MACE_MISC_INT;
        if (!(maceisa_mask & MACEISA_SUPERIO_INT))
		crime_int |= MACE_SUPERIO_INT;
	crime_mask &= ~crime_int;
	crime->imask = crime_mask;
	flush_crime_bus();
	mace->perif.ctrl.imask = maceisa_mask;
	flush_mace_bus();
}

static void mask_and_ack_maceisa_irq(unsigned int irq)
{
	unsigned long mace_int;

	/* edge triggered */
	mace_int = mace->perif.ctrl.istat;
	mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
	mace->perif.ctrl.istat = mace_int;

	disable_maceisa_irq(irq);
}

static void end_maceisa_irq(unsigned irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		enable_maceisa_irq(irq);
}

static struct irq_chip ip32_maceisa_level_interrupt = {
	.name		= "IP32 MACE ISA",
	.ack		= disable_maceisa_irq,
	.mask		= disable_maceisa_irq,
	.mask_ack	= disable_maceisa_irq,
	.unmask		= enable_maceisa_irq,
	.end		= end_maceisa_irq,
};

static struct irq_chip ip32_maceisa_edge_interrupt = {
	.name		= "IP32 MACE ISA",
	.ack		= mask_and_ack_maceisa_irq,
	.mask		= disable_maceisa_irq,
	.mask_ack	= mask_and_ack_maceisa_irq,
	.unmask		= enable_maceisa_irq,
	.end		= end_maceisa_irq,
};

/* This is used for regular non-ISA, non-PCI MACE interrupts.  That means
 * bits 0-3 and 7 in the CRIME register.
 */

static void enable_mace_irq(unsigned int irq)
{
	unsigned int bit = irq - CRIME_IRQ_BASE;

	crime_mask |= (1 << bit);
	crime->imask = crime_mask;
}

static void disable_mace_irq(unsigned int irq)
{
	unsigned int bit = irq - CRIME_IRQ_BASE;

	crime_mask &= ~(1 << bit);
	crime->imask = crime_mask;
	flush_crime_bus();
}

static void end_mace_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
		enable_mace_irq(irq);
}

static struct irq_chip ip32_mace_interrupt = {
	.name = "IP32 MACE",
	.ack = disable_mace_irq,
	.mask = disable_mace_irq,
	.mask_ack = disable_mace_irq,
	.unmask = enable_mace_irq,
	.end = end_mace_irq,
};

static void ip32_unknown_interrupt(void)
{
	printk("Unknown interrupt occurred!\n");
	printk("cp0_status: %08x\n", read_c0_status());
	printk("cp0_cause: %08x\n", read_c0_cause());
	printk("CRIME intr mask: %016lx\n", crime->imask);
	printk("CRIME intr status: %016lx\n", crime->istat);
	printk("CRIME hardware intr register: %016lx\n", crime->hard_int);
	printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
	printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
	printk("MACE PCI control register: %08x\n", mace->pci.control);

	printk("Register dump:\n");
	show_regs(get_irq_regs());

	printk("Please mail this report to linux-mips@linux-mips.org\n");
	printk("Spinning...");
	while(1) ;
}

/* CRIME 1.1 appears to deliver all interrupts to this one pin. */
/* change this to loop over all edge-triggered irqs, exception masked out ones */
static void ip32_irq0(void)
{
	uint64_t crime_int;
	int irq = 0;

	/*
	 * Sanity check interrupt numbering enum.
	 * MACE got 32 interrupts and there are 32 MACE ISA interrupts daisy
	 * chained.
	 */
	BUILD_BUG_ON(CRIME_VICE_IRQ - MACE_VID_IN1_IRQ != 31);
	BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31);

	crime_int = crime->istat & crime_mask;

	/* crime sometime delivers spurious interrupts, ignore them */
	if (unlikely(crime_int == 0))
		return;

	irq = MACE_VID_IN1_IRQ + __ffs(crime_int);

	if (crime_int & CRIME_MACEISA_INT_MASK) {
		unsigned long mace_int = mace->perif.ctrl.istat;
		irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ;
	}

	pr_debug("*irq %u*\n", irq);
	do_IRQ(irq);
}

static void ip32_irq1(void)
{
	ip32_unknown_interrupt();
}

static void ip32_irq2(void)
{
	ip32_unknown_interrupt();
}

static void ip32_irq3(void)
{
	ip32_unknown_interrupt();
}

static void ip32_irq4(void)
{
	ip32_unknown_interrupt();
}

static void ip32_irq5(void)
{
	do_IRQ(MIPS_CPU_IRQ_BASE + 7);
}

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int pending = read_c0_status() & read_c0_cause();

	if (likely(pending & IE_IRQ0))
		ip32_irq0();
	else if (unlikely(pending & IE_IRQ1))
		ip32_irq1();
	else if (unlikely(pending & IE_IRQ2))
		ip32_irq2();
	else if (unlikely(pending & IE_IRQ3))
		ip32_irq3();
	else if (unlikely(pending & IE_IRQ4))
		ip32_irq4();
	else if (likely(pending & IE_IRQ5))
		ip32_irq5();
}

void __init arch_init_irq(void)
{
	unsigned int irq;

	/* Install our interrupt handler, then clear and disable all
	 * CRIME and MACE interrupts. */
	crime->imask = 0;
	crime->hard_int = 0;
	crime->soft_int = 0;
	mace->perif.ctrl.istat = 0;
	mace->perif.ctrl.imask = 0;

	mips_cpu_irq_init();
	for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
		switch (irq) {
		case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
			set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt,
				handle_level_irq, "level");
			break;

		case MACEPCI_SCSI0_IRQ ...  MACEPCI_SHARED2_IRQ:
			set_irq_chip_and_handler_name(irq,
				&ip32_macepci_interrupt, handle_level_irq,
				"level");
			break;

		case CRIME_CPUERR_IRQ:
		case CRIME_MEMERR_IRQ:
			set_irq_chip_and_handler_name(irq,
				&crime_level_interrupt, handle_level_irq,
				"level");
			break;

		case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
		case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
		case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
		case CRIME_VICE_IRQ:
			set_irq_chip_and_handler_name(irq,
				&crime_edge_interrupt, handle_edge_irq, "edge");
			break;

		case MACEISA_PARALLEL_IRQ:
		case MACEISA_SERIAL1_TDMAPR_IRQ:
		case MACEISA_SERIAL2_TDMAPR_IRQ:
			set_irq_chip_and_handler_name(irq,
				&ip32_maceisa_edge_interrupt, handle_edge_irq,
				"edge");
			break;

		default:
			set_irq_chip_and_handler_name(irq,
				&ip32_maceisa_level_interrupt, handle_level_irq,
				"level");
			break;
		}
	}
	setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
	setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);

#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
	change_c0_status(ST0_IM, ALLINTS);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Code to handle IP32 IRQs
	3	*
	4	* This file is subject to the terms and conditions of the GNU General Public
	5	* License. See the file "COPYING" in the main directory of this archive
	6	* for more details.
	7	*
	8	* Copyright (C) 2000 Harald Koerfgen
	9	* Copyright (C) 2001 Keith M Wesolowski
	10	*/
	11	#include <linux/init.h>
	12	#include <linux/kernel_stat.h>
	13	#include <linux/types.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/irq.h>
	16	#include <linux/bitops.h>
	17	#include <linux/kernel.h>
1da177e4 LT	18	#include <linux/mm.h>
	19	#include <linux/random.h>
	20	#include <linux/sched.h>
	21
dd67b155	22	#include <asm/irq_cpu.h>
1da177e4 LT	23	#include <asm/mipsregs.h>
	24	#include <asm/signal.h>
	25	#include <asm/system.h>
	26	#include <asm/time.h>
	27	#include <asm/ip32/crime.h>
	28	#include <asm/ip32/mace.h>
	29	#include <asm/ip32/ip32_ints.h>
	30
	31	/* issue a PIO read to make sure no PIO writes are pending */
	32	static void inline flush_crime_bus(void)
	33	{
b6d7c7a9	34	crime->control;
1da177e4 LT	35	}
	36
	37	static void inline flush_mace_bus(void)
	38	{
b6d7c7a9	39	mace->perif.ctrl.misc;
1da177e4 LT	40	}
1da177e4 LT	41
dd67b155 RB	42	/*
dd67b155 RB	43	* O2 irq map
1da177e4 LT	44	*
	45	* IP0 -> software (ignored)
	46	* IP1 -> software (ignored)
	47	* IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
	48	* IP3 -> (irq1) X unknown
	49	* IP4 -> (irq2) X unknown
	50	* IP5 -> (irq3) X unknown
	51	* IP6 -> (irq4) X unknown
dd67b155	52	* IP7 -> (irq5) 7 CPU count/compare timer (system timer)
1da177e4 LT	53	*
	54	* crime: (C)
	55	*
	56	* CRIME_INT_STAT 31:0:
	57	*
dd67b155 RB	58	* 0 -> 8 Video in 1
	59	* 1 -> 9 Video in 2
	60	* 2 -> 10 Video out
	61	* 3 -> 11 Mace ethernet
1da177e4 LT	62	* 4 -> S SuperIO sub-interrupt
	63	* 5 -> M Miscellaneous sub-interrupt
	64	* 6 -> A Audio sub-interrupt
dd67b155 RB	65	* 7 -> 15 PCI bridge errors
	66	* 8 -> 16 PCI SCSI aic7xxx 0
	67	* 9 -> 17 PCI SCSI aic7xxx 1
	68	* 10 -> 18 PCI slot 0
	69	* 11 -> 19 unused (PCI slot 1)
	70	* 12 -> 20 unused (PCI slot 2)
	71	* 13 -> 21 unused (PCI shared 0)
	72	* 14 -> 22 unused (PCI shared 1)
	73	* 15 -> 23 unused (PCI shared 2)
	74	* 16 -> 24 GBE0 (E)
	75	* 17 -> 25 GBE1 (E)
	76	* 18 -> 26 GBE2 (E)
	77	* 19 -> 27 GBE3 (E)
	78	* 20 -> 28 CPU errors
	79	* 21 -> 29 Memory errors
	80	* 22 -> 30 RE empty edge (E)
	81	* 23 -> 31 RE full edge (E)
	82	* 24 -> 32 RE idle edge (E)
	83	* 25 -> 33 RE empty level
	84	* 26 -> 34 RE full level
	85	* 27 -> 35 RE idle level
	86	* 28 -> 36 unused (software 0) (E)
	87	* 29 -> 37 unused (software 1) (E)
	88	* 30 -> 38 unused (software 2) - crime 1.5 CPU SysCorError (E)
	89	* 31 -> 39 VICE
1da177e4 LT	90	*
	91	* S, M, A: Use the MACE ISA interrupt register
	92	* MACE_ISA_INT_STAT 31:0
	93	*
dd67b155 RB	94	* 0-7 -> 40-47 Audio
	95	* 8 -> 48 RTC
	96	* 9 -> 49 Keyboard
1da177e4	97	* 10 -> X Keyboard polled
dd67b155	98	* 11 -> 51 Mouse
1da177e4	99	* 12 -> X Mouse polled
dd67b155 RB	100	* 13-15 -> 53-55 Count/compare timers
	101	* 16-19 -> 56-59 Parallel (16 E)
	102	* 20-25 -> 60-62 Serial 1 (22 E)
	103	* 26-31 -> 66-71 Serial 2 (28 E)
1da177e4	104	*
dd67b155	105	* Note that this means IRQs 12-14, 50, and 52 do not exist. This is a
1da177e4 LT	106	* different IRQ map than IRIX uses, but that's OK as Linux irq handling
	107	* is quite different anyway.
	108	*/
	109
1da177e4	110	/* Some initial interrupts to set up */
937a8015 RB	111	extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
937a8015 RB	112	extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
1da177e4	113
ae537387	114	static struct irqaction memerr_irq = {
4e45171c TG	115	.handler = crime_memerr_intr,
4e45171c TG	116	.flags = IRQF_DISABLED,
4e45171c TG	117	.name = "CRIME memory error",
4e45171c TG	118	};
8a13ecd7	119
ae537387	120	static struct irqaction cpuerr_irq = {
4e45171c TG	121	.handler = crime_cpuerr_intr,
4e45171c TG	122	.flags = IRQF_DISABLED,
4e45171c TG	123	.name = "CRIME CPU error",
4e45171c TG	124	};
1da177e4	125
1da177e4 LT	126	/*
	127	* This is for pure CRIME interrupts - ie not MACE. The advantage?
	128	* We get to split the register in half and do faster lookups.
	129	*/
	130
	131	static uint64_t crime_mask;
	132
8a13ecd7	133	static inline void crime_enable_irq(unsigned int irq)
1da177e4	134	{
8a13ecd7 RB	135	unsigned int bit = irq - CRIME_IRQ_BASE;
	136
	137	crime_mask \|= 1 << bit;
1da177e4	138	crime->imask = crime_mask;
1da177e4 LT	139	}
1da177e4 LT	140
8a13ecd7	141	static inline void crime_disable_irq(unsigned int irq)
1da177e4	142	{
8a13ecd7 RB	143	unsigned int bit = irq - CRIME_IRQ_BASE;
	144
	145	crime_mask &= ~(1 << bit);
1da177e4 LT	146	crime->imask = crime_mask;
1da177e4 LT	147	flush_crime_bus();
1da177e4 LT	148	}
1da177e4 LT	149
8a13ecd7 RB	150	static void crime_level_mask_and_ack_irq(unsigned int irq)
	151	{
	152	crime_disable_irq(irq);
	153	}
	154
	155	static void crime_level_end_irq(unsigned int irq)
	156	{
	157	if (!(irq_desc[irq].status & (IRQ_DISABLED \| IRQ_INPROGRESS)))
	158	crime_enable_irq(irq);
	159	}
	160
	161	static struct irq_chip crime_level_interrupt = {
	162	.name = "IP32 CRIME",
	163	.ack = crime_level_mask_and_ack_irq,
	164	.mask = crime_disable_irq,
	165	.mask_ack = crime_level_mask_and_ack_irq,
	166	.unmask = crime_enable_irq,
	167	.end = crime_level_end_irq,
	168	};
	169
	170	static void crime_edge_mask_and_ack_irq(unsigned int irq)
1da177e4	171	{
8a13ecd7 RB	172	unsigned int bit = irq - CRIME_IRQ_BASE;
	173	uint64_t crime_int;
	174
1da177e4	175	/* Edge triggered interrupts must be cleared. */
8a13ecd7 RB	176
	177	crime_int = crime->hard_int;
	178	crime_int &= ~(1 << bit);
	179	crime->hard_int = crime_int;
	180
	181	crime_disable_irq(irq);
1da177e4 LT	182	}
1da177e4 LT	183
8a13ecd7	184	static void crime_edge_end_irq(unsigned int irq)
1da177e4 LT	185	{
1da177e4 LT	186	if (!(irq_desc[irq].status & (IRQ_DISABLED \| IRQ_INPROGRESS)))
8a13ecd7	187	crime_enable_irq(irq);
1da177e4 LT	188	}
1da177e4 LT	189
8a13ecd7 RB	190	static struct irq_chip crime_edge_interrupt = {
	191	.name = "IP32 CRIME",
	192	.ack = crime_edge_mask_and_ack_irq,
	193	.mask = crime_disable_irq,
	194	.mask_ack = crime_edge_mask_and_ack_irq,
	195	.unmask = crime_enable_irq,
	196	.end = crime_edge_end_irq,
1da177e4 LT	197	};
	198
	199	/*
	200	* This is for MACE PCI interrupts. We can decrease bus traffic by masking
	201	* as close to the source as possible. This also means we can take the
	202	* next chunk of the CRIME register in one piece.
	203	*/
	204
	205	static unsigned long macepci_mask;
	206
	207	static void enable_macepci_irq(unsigned int irq)
	208	{
98ce4721	209	macepci_mask \|= MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ);
1da177e4	210	mace->pci.control = macepci_mask;
98ce4721	211	crime_mask \|= 1 << (irq - CRIME_IRQ_BASE);
1da177e4	212	crime->imask = crime_mask;
1da177e4 LT	213	}
	214
	215	static void disable_macepci_irq(unsigned int irq)
	216	{
98ce4721	217	crime_mask &= ~(1 << (irq - CRIME_IRQ_BASE));
1da177e4 LT	218	crime->imask = crime_mask;
1da177e4 LT	219	flush_crime_bus();
98ce4721	220	macepci_mask &= ~MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ);
1da177e4 LT	221	mace->pci.control = macepci_mask;
1da177e4 LT	222	flush_mace_bus();
1da177e4 LT	223	}
	224
	225	static void end_macepci_irq(unsigned int irq)
	226	{
	227	if (!(irq_desc[irq].status & (IRQ_DISABLED\|IRQ_INPROGRESS)))
	228	enable_macepci_irq(irq);
	229	}
	230
94dee171	231	static struct irq_chip ip32_macepci_interrupt = {
70d21cde	232	.name = "IP32 MACE PCI",
1603b5ac AN	233	.ack = disable_macepci_irq,
	234	.mask = disable_macepci_irq,
	235	.mask_ack = disable_macepci_irq,
	236	.unmask = enable_macepci_irq,
8ab00b9a	237	.end = end_macepci_irq,
1da177e4 LT	238	};
	239
	240	/* This is used for MACE ISA interrupts. That means bits 4-6 in the
	241	* CRIME register.
	242	*/
	243
	244	#define MACEISA_AUDIO_INT (MACEISA_AUDIO_SW_INT \| \
	245	MACEISA_AUDIO_SC_INT \| \
	246	MACEISA_AUDIO1_DMAT_INT \| \
	247	MACEISA_AUDIO1_OF_INT \| \
	248	MACEISA_AUDIO2_DMAT_INT \| \
	249	MACEISA_AUDIO2_MERR_INT \| \
	250	MACEISA_AUDIO3_DMAT_INT \| \
	251	MACEISA_AUDIO3_MERR_INT)
	252	#define MACEISA_MISC_INT (MACEISA_RTC_INT \| \
	253	MACEISA_KEYB_INT \| \
	254	MACEISA_KEYB_POLL_INT \| \
	255	MACEISA_MOUSE_INT \| \
	256	MACEISA_MOUSE_POLL_INT \| \
cfbae5d3 TS	257	MACEISA_TIMER0_INT \| \
	258	MACEISA_TIMER1_INT \| \
	259	MACEISA_TIMER2_INT)
1da177e4 LT	260	#define MACEISA_SUPERIO_INT (MACEISA_PARALLEL_INT \| \
	261	MACEISA_PAR_CTXA_INT \| \
	262	MACEISA_PAR_CTXB_INT \| \
	263	MACEISA_PAR_MERR_INT \| \
	264	MACEISA_SERIAL1_INT \| \
	265	MACEISA_SERIAL1_TDMAT_INT \| \
	266	MACEISA_SERIAL1_TDMAPR_INT \| \
	267	MACEISA_SERIAL1_TDMAME_INT \| \
	268	MACEISA_SERIAL1_RDMAT_INT \| \
	269	MACEISA_SERIAL1_RDMAOR_INT \| \
	270	MACEISA_SERIAL2_INT \| \
	271	MACEISA_SERIAL2_TDMAT_INT \| \
	272	MACEISA_SERIAL2_TDMAPR_INT \| \
	273	MACEISA_SERIAL2_TDMAME_INT \| \
	274	MACEISA_SERIAL2_RDMAT_INT \| \
	275	MACEISA_SERIAL2_RDMAOR_INT)
	276
	277	static unsigned long maceisa_mask;
	278
49a89efb	279	static void enable_maceisa_irq(unsigned int irq)
1da177e4 LT	280	{
1da177e4 LT	281	unsigned int crime_int = 0;
1da177e4	282
8a13ecd7	283	pr_debug("maceisa enable: %u\n", irq);
1da177e4 LT	284
	285	switch (irq) {
	286	case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
	287	crime_int = MACE_AUDIO_INT;
	288	break;
cfbae5d3	289	case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
1da177e4 LT	290	crime_int = MACE_MISC_INT;
	291	break;
	292	case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
	293	crime_int = MACE_SUPERIO_INT;
	294	break;
	295	}
8a13ecd7	296	pr_debug("crime_int %08x enabled\n", crime_int);
1da177e4 LT	297	crime_mask \|= crime_int;
1da177e4 LT	298	crime->imask = crime_mask;
98ce4721	299	maceisa_mask \|= 1 << (irq - MACEISA_AUDIO_SW_IRQ);
1da177e4	300	mace->perif.ctrl.imask = maceisa_mask;
1da177e4 LT	301	}
	302
	303	static void disable_maceisa_irq(unsigned int irq)
	304	{
	305	unsigned int crime_int = 0;
1da177e4	306
98ce4721	307	maceisa_mask &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
8a13ecd7	308	if (!(maceisa_mask & MACEISA_AUDIO_INT))
1da177e4	309	crime_int \|= MACE_AUDIO_INT;
8a13ecd7	310	if (!(maceisa_mask & MACEISA_MISC_INT))
1da177e4	311	crime_int \|= MACE_MISC_INT;
8a13ecd7	312	if (!(maceisa_mask & MACEISA_SUPERIO_INT))
1da177e4 LT	313	crime_int \|= MACE_SUPERIO_INT;
	314	crime_mask &= ~crime_int;
	315	crime->imask = crime_mask;
	316	flush_crime_bus();
	317	mace->perif.ctrl.imask = maceisa_mask;
	318	flush_mace_bus();
1da177e4 LT	319	}
	320
	321	static void mask_and_ack_maceisa_irq(unsigned int irq)
	322	{
1603b5ac	323	unsigned long mace_int;
1da177e4	324
c87e0909 RB	325	/* edge triggered */
	326	mace_int = mace->perif.ctrl.istat;
	327	mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
	328	mace->perif.ctrl.istat = mace_int;
	329
1da177e4 LT	330	disable_maceisa_irq(irq);
	331	}
	332
	333	static void end_maceisa_irq(unsigned irq)
	334	{
	335	if (!(irq_desc[irq].status & (IRQ_DISABLED \| IRQ_INPROGRESS)))
	336	enable_maceisa_irq(irq);
	337	}
	338
c87e0909 RB	339	static struct irq_chip ip32_maceisa_level_interrupt = {
	340	.name = "IP32 MACE ISA",
	341	.ack = disable_maceisa_irq,
	342	.mask = disable_maceisa_irq,
	343	.mask_ack = disable_maceisa_irq,
	344	.unmask = enable_maceisa_irq,
	345	.end = end_maceisa_irq,
	346	};
	347
	348	static struct irq_chip ip32_maceisa_edge_interrupt = {
8a13ecd7 RB	349	.name = "IP32 MACE ISA",
	350	.ack = mask_and_ack_maceisa_irq,
	351	.mask = disable_maceisa_irq,
	352	.mask_ack = mask_and_ack_maceisa_irq,
	353	.unmask = enable_maceisa_irq,
	354	.end = end_maceisa_irq,
1da177e4 LT	355	};
	356
	357	/* This is used for regular non-ISA, non-PCI MACE interrupts. That means
	358	* bits 0-3 and 7 in the CRIME register.
	359	*/
	360
	361	static void enable_mace_irq(unsigned int irq)
	362	{
98ce4721 RB	363	unsigned int bit = irq - CRIME_IRQ_BASE;
	364
	365	crime_mask \|= (1 << bit);
1da177e4	366	crime->imask = crime_mask;
1da177e4 LT	367	}
	368
	369	static void disable_mace_irq(unsigned int irq)
	370	{
98ce4721 RB	371	unsigned int bit = irq - CRIME_IRQ_BASE;
	372
	373	crime_mask &= ~(1 << bit);
1da177e4 LT	374	crime->imask = crime_mask;
1da177e4 LT	375	flush_crime_bus();
1da177e4 LT	376	}
	377
	378	static void end_mace_irq(unsigned int irq)
	379	{
	380	if (!(irq_desc[irq].status & (IRQ_DISABLED\|IRQ_INPROGRESS)))
	381	enable_mace_irq(irq);
	382	}
	383
94dee171	384	static struct irq_chip ip32_mace_interrupt = {
70d21cde	385	.name = "IP32 MACE",
1603b5ac AN	386	.ack = disable_mace_irq,
	387	.mask = disable_mace_irq,
	388	.mask_ack = disable_mace_irq,
	389	.unmask = enable_mace_irq,
8ab00b9a	390	.end = end_mace_irq,
1da177e4 LT	391	};
1da177e4 LT	392
937a8015	393	static void ip32_unknown_interrupt(void)
1da177e4	394	{
49a89efb RB	395	printk("Unknown interrupt occurred!\n");
	396	printk("cp0_status: %08x\n", read_c0_status());
	397	printk("cp0_cause: %08x\n", read_c0_cause());
	398	printk("CRIME intr mask: %016lx\n", crime->imask);
	399	printk("CRIME intr status: %016lx\n", crime->istat);
	400	printk("CRIME hardware intr register: %016lx\n", crime->hard_int);
	401	printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
	402	printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
	403	printk("MACE PCI control register: %08x\n", mace->pci.control);
1da177e4 LT	404
1da177e4 LT	405	printk("Register dump:\n");
937a8015	406	show_regs(get_irq_regs());
1da177e4 LT	407
	408	printk("Please mail this report to linux-mips@linux-mips.org\n");
	409	printk("Spinning...");
	410	while(1) ;
	411	}
	412
	413	/* CRIME 1.1 appears to deliver all interrupts to this one pin. */
	414	/* change this to loop over all edge-triggered irqs, exception masked out ones */
937a8015	415	static void ip32_irq0(void)
1da177e4 LT	416	{
	417	uint64_t crime_int;
	418	int irq = 0;
	419
dd67b155 RB	420	/*
	421	* Sanity check interrupt numbering enum.
	422	* MACE got 32 interrupts and there are 32 MACE ISA interrupts daisy
	423	* chained.
	424	*/
	425	BUILD_BUG_ON(CRIME_VICE_IRQ - MACE_VID_IN1_IRQ != 31);
	426	BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31);
	427
1da177e4	428	crime_int = crime->istat & crime_mask;
1faf7f25 TB	429
	430	/* crime sometime delivers spurious interrupts, ignore them */
	431	if (unlikely(crime_int == 0))
	432	return;
	433
dd67b155	434	irq = MACE_VID_IN1_IRQ + __ffs(crime_int);
1da177e4 LT	435
	436	if (crime_int & CRIME_MACEISA_INT_MASK) {
	437	unsigned long mace_int = mace->perif.ctrl.istat;
dd67b155	438	irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ;
1da177e4	439	}
dd67b155	440
8a13ecd7	441	pr_debug("irq %u\n", irq);
937a8015	442	do_IRQ(irq);
1da177e4 LT	443	}
1da177e4 LT	444
937a8015	445	static void ip32_irq1(void)
1da177e4	446	{
937a8015	447	ip32_unknown_interrupt();
1da177e4 LT	448	}
1da177e4 LT	449
937a8015	450	static void ip32_irq2(void)
1da177e4	451	{
937a8015	452	ip32_unknown_interrupt();
1da177e4 LT	453	}
1da177e4 LT	454
937a8015	455	static void ip32_irq3(void)
1da177e4	456	{
937a8015	457	ip32_unknown_interrupt();
1da177e4 LT	458	}
1da177e4 LT	459
937a8015	460	static void ip32_irq4(void)
1da177e4	461	{
937a8015	462	ip32_unknown_interrupt();
1da177e4 LT	463	}
1da177e4 LT	464
937a8015	465	static void ip32_irq5(void)
1da177e4	466	{
dd67b155	467	do_IRQ(MIPS_CPU_IRQ_BASE + 7);
1da177e4 LT	468	}
1da177e4 LT	469
937a8015	470	asmlinkage void plat_irq_dispatch(void)
e4ac58af	471	{
119537c0	472	unsigned int pending = read_c0_status() & read_c0_cause();
e4ac58af RB	473
e4ac58af RB	474	if (likely(pending & IE_IRQ0))
937a8015	475	ip32_irq0();
e4ac58af	476	else if (unlikely(pending & IE_IRQ1))
937a8015	477	ip32_irq1();
e4ac58af	478	else if (unlikely(pending & IE_IRQ2))
937a8015	479	ip32_irq2();
e4ac58af	480	else if (unlikely(pending & IE_IRQ3))
937a8015	481	ip32_irq3();
e4ac58af	482	else if (unlikely(pending & IE_IRQ4))
937a8015	483	ip32_irq4();
e4ac58af	484	else if (likely(pending & IE_IRQ5))
937a8015	485	ip32_irq5();
e4ac58af RB	486	}
e4ac58af RB	487
1da177e4 LT	488	void __init arch_init_irq(void)
	489	{
	490	unsigned int irq;
	491
	492	/* Install our interrupt handler, then clear and disable all
	493	* CRIME and MACE interrupts. */
	494	crime->imask = 0;
	495	crime->hard_int = 0;
	496	crime->soft_int = 0;
	497	mace->perif.ctrl.istat = 0;
	498	mace->perif.ctrl.imask = 0;
1da177e4	499
dd67b155	500	mips_cpu_irq_init();
98ce4721	501	for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
dd67b155 RB	502	switch (irq) {
dd67b155 RB	503	case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
c87e0909 RB	504	set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt,
c87e0909 RB	505	handle_level_irq, "level");
dd67b155	506	break;
c87e0909	507
dd67b155	508	case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ:
c87e0909 RB	509	set_irq_chip_and_handler_name(irq,
	510	&ip32_macepci_interrupt, handle_level_irq,
	511	"level");
8a13ecd7	512	break;
c87e0909	513
8a13ecd7 RB	514	case CRIME_CPUERR_IRQ:
8a13ecd7 RB	515	case CRIME_MEMERR_IRQ:
c87e0909 RB	516	set_irq_chip_and_handler_name(irq,
	517	&crime_level_interrupt, handle_level_irq,
	518	"level");
dd67b155	519	break;
c87e0909	520
2fe06260	521	case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
8a13ecd7 RB	522	case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
8a13ecd7 RB	523	case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
8a13ecd7	524	case CRIME_VICE_IRQ:
c87e0909 RB	525	set_irq_chip_and_handler_name(irq,
	526	&crime_edge_interrupt, handle_edge_irq, "edge");
	527	break;
	528
	529	case MACEISA_PARALLEL_IRQ:
	530	case MACEISA_SERIAL1_TDMAPR_IRQ:
	531	case MACEISA_SERIAL2_TDMAPR_IRQ:
	532	set_irq_chip_and_handler_name(irq,
	533	&ip32_maceisa_edge_interrupt, handle_edge_irq,
	534	"edge");
dd67b155	535	break;
c87e0909	536
dd67b155	537	default:
c87e0909 RB	538	set_irq_chip_and_handler_name(irq,
	539	&ip32_maceisa_level_interrupt, handle_level_irq,
	540	"level");
8a13ecd7	541	break;
dd67b155	542	}
1da177e4 LT	543	}
	544	setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
	545	setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
	546
	547	#define ALLINTS (IE_IRQ0 \| IE_IRQ1 \| IE_IRQ2 \| IE_IRQ3 \| IE_IRQ4 \| IE_IRQ5)
	548	change_c0_status(ST0_IM, ALLINTS);
	549	}