[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / mm / sc-mips.c

/*
 * Copyright (C) 2006 Chris Dearman (chris@mips.com),
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>

#include <asm/mipsregs.h>
#include <asm/bcache.h>
#include <asm/cacheops.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/mmu_context.h>
#include <asm/r4kcache.h>

/*
 * MIPS32/MIPS64 L2 cache handling
 */

/*
 * Writeback and invalidate the secondary cache before DMA.
 */
static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
{
	blast_scache_range(addr, addr + size);
}

/*
 * Invalidate the secondary cache before DMA.
 */
static void mips_sc_inv(unsigned long addr, unsigned long size)
{
	unsigned long lsize = cpu_scache_line_size();
	unsigned long almask = ~(lsize - 1);

	cache_op(Hit_Writeback_Inv_SD, addr & almask);
	cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);
	blast_inv_scache_range(addr, addr + size);
}

static void mips_sc_enable(void)
{
	/* L2 cache is permanently enabled */
}

static void mips_sc_disable(void)
{
	/* L2 cache is permanently enabled */
}

static struct bcache_ops mips_sc_ops = {
	.bc_enable = mips_sc_enable,
	.bc_disable = mips_sc_disable,
	.bc_wback_inv = mips_sc_wback_inv,
	.bc_inv = mips_sc_inv
};

/*
 * Check if the L2 cache controller is activated on a particular platform.
 * MTI's L2 controller and the L2 cache controller of Broadcom's BMIPS
 * cores both use c0_config2's bit 12 as "L2 Bypass" bit, that is the
 * cache being disabled.  However there is no guarantee for this to be
 * true on all platforms.  In an act of stupidity the spec defined bits
 * 12..15 as implementation defined so below function will eventually have
 * to be replaced by a platform specific probe.
 */
static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
{
	unsigned int config2 = read_c0_config2();
	unsigned int tmp;

	/* Check the bypass bit (L2B) */
	switch (c->cputype) {
	case CPU_34K:
	case CPU_74K:
	case CPU_1004K:
	case CPU_BMIPS5000:
		if (config2 & (1 << 12))
			return 0;
	}

	tmp = (config2 >> 4) & 0x0f;
	if (0 < tmp && tmp <= 7)
		c->scache.linesz = 2 << tmp;
	else
		return 0;
	return 1;
}

static inline int __init mips_sc_probe(void)
{
	struct cpuinfo_mips *c = &current_cpu_data;
	unsigned int config1, config2;
	unsigned int tmp;

	/* Mark as not present until probe completed */
	c->scache.flags |= MIPS_CACHE_NOT_PRESENT;

	/* Ignore anything but MIPSxx processors */
	if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
			      MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)))
		return 0;

	/* Does this MIPS32/MIPS64 CPU have a config2 register? */
	config1 = read_c0_config1();
	if (!(config1 & MIPS_CONF_M))
		return 0;

	config2 = read_c0_config2();

	if (!mips_sc_is_activated(c))
		return 0;

	tmp = (config2 >> 8) & 0x0f;
	if (0 <= tmp && tmp <= 7)
		c->scache.sets = 64 << tmp;
	else
		return 0;

	tmp = (config2 >> 0) & 0x0f;
	if (0 <= tmp && tmp <= 7)
		c->scache.ways = tmp + 1;
	else
		return 0;

	c->scache.waysize = c->scache.sets * c->scache.linesz;
	c->scache.waybit = __ffs(c->scache.waysize);

	c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;

	return 1;
}

int __cpuinit mips_sc_init(void)
{
	int found = mips_sc_probe();
	if (found) {
		mips_sc_enable();
		bcops = &mips_sc_ops;
	}
	return found;
}
Commit	Line	Data
9318c51a CD	1	/*
	2	* Copyright (C) 2006 Chris Dearman (chris@mips.com),
	3	*/
	4	#include <linux/init.h>
	5	#include <linux/kernel.h>
	6	#include <linux/sched.h>
	7	#include <linux/mm.h>
	8
	9	#include <asm/mipsregs.h>
	10	#include <asm/bcache.h>
	11	#include <asm/cacheops.h>
	12	#include <asm/page.h>
	13	#include <asm/pgtable.h>
9318c51a CD	14	#include <asm/mmu_context.h>
	15	#include <asm/r4kcache.h>
	16
	17	/*
	18	* MIPS32/MIPS64 L2 cache handling
	19	*/
	20
	21	/*
	22	* Writeback and invalidate the secondary cache before DMA.
	23	*/
	24	static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
	25	{
a2c2bc4b	26	blast_scache_range(addr, addr + size);
9318c51a CD	27	}
	28
	29	/*
	30	* Invalidate the secondary cache before DMA.
	31	*/
	32	static void mips_sc_inv(unsigned long addr, unsigned long size)
	33	{
96983ffe KC	34	unsigned long lsize = cpu_scache_line_size();
	35	unsigned long almask = ~(lsize - 1);
	36
	37	cache_op(Hit_Writeback_Inv_SD, addr & almask);
	38	cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);
a2c2bc4b	39	blast_inv_scache_range(addr, addr + size);
9318c51a CD	40	}
	41
	42	static void mips_sc_enable(void)
	43	{
	44	/* L2 cache is permanently enabled */
	45	}
	46
	47	static void mips_sc_disable(void)
	48	{
	49	/* L2 cache is permanently enabled */
	50	}
	51
	52	static struct bcache_ops mips_sc_ops = {
	53	.bc_enable = mips_sc_enable,
	54	.bc_disable = mips_sc_disable,
	55	.bc_wback_inv = mips_sc_wback_inv,
	56	.bc_inv = mips_sc_inv
	57	};
	58
ea31a6b2 KC	59	/*
	60	* Check if the L2 cache controller is activated on a particular platform.
	61	* MTI's L2 controller and the L2 cache controller of Broadcom's BMIPS
	62	* cores both use c0_config2's bit 12 as "L2 Bypass" bit, that is the
	63	* cache being disabled. However there is no guarantee for this to be
	64	* true on all platforms. In an act of stupidity the spec defined bits
	65	* 12..15 as implementation defined so below function will eventually have
	66	* to be replaced by a platform specific probe.
	67	*/
	68	static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
	69	{
081d835f KC	70	unsigned int config2 = read_c0_config2();
	71	unsigned int tmp;
	72
ea31a6b2 KC	73	/* Check the bypass bit (L2B) */
	74	switch (c->cputype) {
	75	case CPU_34K:
	76	case CPU_74K:
	77	case CPU_1004K:
	78	case CPU_BMIPS5000:
	79	if (config2 & (1 << 12))
	80	return 0;
	81	}
	82
	83	tmp = (config2 >> 4) & 0x0f;
	84	if (0 < tmp && tmp <= 7)
	85	c->scache.linesz = 2 << tmp;
	86	else
	87	return 0;
081d835f	88	return 1;
ea31a6b2 KC	89	}
ea31a6b2 KC	90
9318c51a CD	91	static inline int __init mips_sc_probe(void)
	92	{
	93	struct cpuinfo_mips *c = &current_cpu_data;
	94	unsigned int config1, config2;
	95	unsigned int tmp;
	96
	97	/* Mark as not present until probe completed */
	98	c->scache.flags \|= MIPS_CACHE_NOT_PRESENT;
	99
	100	/* Ignore anything but MIPSxx processors */
adb37892 DCZ	101	if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 \| MIPS_CPU_ISA_M32R2 \|
adb37892 DCZ	102	MIPS_CPU_ISA_M64R1 \| MIPS_CPU_ISA_M64R2)))
9318c51a CD	103	return 0;
	104
	105	/* Does this MIPS32/MIPS64 CPU have a config2 register? */
	106	config1 = read_c0_config1();
	107	if (!(config1 & MIPS_CONF_M))
	108	return 0;
	109
	110	config2 = read_c0_config2();
ea31a6b2 KC	111
ea31a6b2 KC	112	if (!mips_sc_is_activated(c))
9318c51a CD	113	return 0;
	114
	115	tmp = (config2 >> 8) & 0x0f;
	116	if (0 <= tmp && tmp <= 7)
	117	c->scache.sets = 64 << tmp;
	118	else
	119	return 0;
	120
	121	tmp = (config2 >> 0) & 0x0f;
	122	if (0 <= tmp && tmp <= 7)
	123	c->scache.ways = tmp + 1;
	124	else
	125	return 0;
	126
	127	c->scache.waysize = c->scache.sets * c->scache.linesz;
a2c2bc4b	128	c->scache.waybit = __ffs(c->scache.waysize);
9318c51a CD	129
	130	c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
	131
	132	return 1;
	133	}
	134
234fcd14	135	int __cpuinit mips_sc_init(void)
9318c51a	136	{
49a89efb	137	int found = mips_sc_probe();
9318c51a CD	138	if (found) {
	139	mips_sc_enable();
	140	bcops = &mips_sc_ops;
	141	}
	142	return found;
	143	}