[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / kernel / ptrace.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1992 Ross Biro
 * Copyright (C) Linus Torvalds
 * Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
 * Copyright (C) 1996 David S. Miller
 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 1999 MIPS Technologies, Inc.
 * Copyright (C) 2000 Ulf Carlsson
 *
 * At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
 * binaries.
 */
#include <linux/compiler.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/errno.h>
#include <linux/ptrace.h>
#include <linux/smp.h>
#include <linux/user.h>
#include <linux/security.h>
#include <linux/audit.h>
#include <linux/seccomp.h>

#include <asm/byteorder.h>
#include <asm/cpu.h>
#include <asm/dsp.h>
#include <asm/fpu.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/uaccess.h>
#include <asm/bootinfo.h>
#include <asm/reg.h>

/*
 * Called by kernel/ptrace.c when detaching..
 *
 * Make sure single step bits etc are not set.
 */
void ptrace_disable(struct task_struct *child)
{
	/* Don't load the watchpoint registers for the ex-child. */
	clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
}

/*
 * Read a general register set.	 We always use the 64-bit format, even
 * for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
 * Registers are sign extended to fill the available space.
 */
int ptrace_getregs(struct task_struct *child, __s64 __user *data)
{
	struct pt_regs *regs;
	int i;

	if (!access_ok(VERIFY_WRITE, data, 38 * 8))
		return -EIO;

	regs = task_pt_regs(child);

	for (i = 0; i < 32; i++)
		__put_user((long)regs->regs[i], data + i);
	__put_user((long)regs->lo, data + EF_LO - EF_R0);
	__put_user((long)regs->hi, data + EF_HI - EF_R0);
	__put_user((long)regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
	__put_user((long)regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0);
	__put_user((long)regs->cp0_status, data + EF_CP0_STATUS - EF_R0);
	__put_user((long)regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0);

	return 0;
}

/*
 * Write a general register set.  As for PTRACE_GETREGS, we always use
 * the 64-bit format.  On a 32-bit kernel only the lower order half
 * (according to endianness) will be used.
 */
int ptrace_setregs(struct task_struct *child, __s64 __user *data)
{
	struct pt_regs *regs;
	int i;

	if (!access_ok(VERIFY_READ, data, 38 * 8))
		return -EIO;

	regs = task_pt_regs(child);

	for (i = 0; i < 32; i++)
		__get_user(regs->regs[i], data + i);
	__get_user(regs->lo, data + EF_LO - EF_R0);
	__get_user(regs->hi, data + EF_HI - EF_R0);
	__get_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0);

	/* badvaddr, status, and cause may not be written.  */

	return 0;
}

int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)
{
	int i;
	unsigned int tmp;

	if (!access_ok(VERIFY_WRITE, data, 33 * 8))
		return -EIO;

	if (tsk_used_math(child)) {
		fpureg_t *fregs = get_fpu_regs(child);
		for (i = 0; i < 32; i++)
			__put_user(fregs[i], i + (__u64 __user *) data);
	} else {
		for (i = 0; i < 32; i++)
			__put_user((__u64) -1, i + (__u64 __user *) data);
	}

	__put_user(child->thread.fpu.fcr31, data + 64);

	preempt_disable();
	if (cpu_has_fpu) {
		unsigned int flags;

		if (cpu_has_mipsmt) {
			unsigned int vpflags = dvpe();
			flags = read_c0_status();
			__enable_fpu();
			__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
			write_c0_status(flags);
			evpe(vpflags);
		} else {
			flags = read_c0_status();
			__enable_fpu();
			__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
			write_c0_status(flags);
		}
	} else {
		tmp = 0;
	}
	preempt_enable();
	__put_user(tmp, data + 65);

	return 0;
}

int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
{
	fpureg_t *fregs;
	int i;

	if (!access_ok(VERIFY_READ, data, 33 * 8))
		return -EIO;

	fregs = get_fpu_regs(child);

	for (i = 0; i < 32; i++)
		__get_user(fregs[i], i + (__u64 __user *) data);

	__get_user(child->thread.fpu.fcr31, data + 64);
	child->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;

	/* FIR may not be written.  */

	return 0;
}

int ptrace_get_watch_regs(struct task_struct *child,
			  struct pt_watch_regs __user *addr)
{
	enum pt_watch_style style;
	int i;

	if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
		return -EIO;
	if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs)))
		return -EIO;

#ifdef CONFIG_32BIT
	style = pt_watch_style_mips32;
#define WATCH_STYLE mips32
#else
	style = pt_watch_style_mips64;
#define WATCH_STYLE mips64
#endif

	__put_user(style, &addr->style);
	__put_user(current_cpu_data.watch_reg_use_cnt,
		   &addr->WATCH_STYLE.num_valid);
	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
		__put_user(child->thread.watch.mips3264.watchlo[i],
			   &addr->WATCH_STYLE.watchlo[i]);
		__put_user(child->thread.watch.mips3264.watchhi[i] & 0xfff,
			   &addr->WATCH_STYLE.watchhi[i]);
		__put_user(current_cpu_data.watch_reg_masks[i],
			   &addr->WATCH_STYLE.watch_masks[i]);
	}
	for (; i < 8; i++) {
		__put_user(0, &addr->WATCH_STYLE.watchlo[i]);
		__put_user(0, &addr->WATCH_STYLE.watchhi[i]);
		__put_user(0, &addr->WATCH_STYLE.watch_masks[i]);
	}

	return 0;
}

int ptrace_set_watch_regs(struct task_struct *child,
			  struct pt_watch_regs __user *addr)
{
	int i;
	int watch_active = 0;
	unsigned long lt[NUM_WATCH_REGS];
	u16 ht[NUM_WATCH_REGS];

	if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
		return -EIO;
	if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs)))
		return -EIO;
	/* Check the values. */
	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
		__get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
#ifdef CONFIG_32BIT
		if (lt[i] & __UA_LIMIT)
			return -EINVAL;
#else
		if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) {
			if (lt[i] & 0xffffffff80000000UL)
				return -EINVAL;
		} else {
			if (lt[i] & __UA_LIMIT)
				return -EINVAL;
		}
#endif
		__get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
		if (ht[i] & ~0xff8)
			return -EINVAL;
	}
	/* Install them. */
	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
		if (lt[i] & 7)
			watch_active = 1;
		child->thread.watch.mips3264.watchlo[i] = lt[i];
		/* Set the G bit. */
		child->thread.watch.mips3264.watchhi[i] = ht[i];
	}

	if (watch_active)
		set_tsk_thread_flag(child, TIF_LOAD_WATCH);
	else
		clear_tsk_thread_flag(child, TIF_LOAD_WATCH);

	return 0;
}

long arch_ptrace(struct task_struct *child, long request,
		 unsigned long addr, unsigned long data)
{
	int ret;
	void __user *addrp = (void __user *) addr;
	void __user *datavp = (void __user *) data;
	unsigned long __user *datalp = (void __user *) data;

	switch (request) {
	/* when I and D space are separate, these will need to be fixed. */
	case PTRACE_PEEKTEXT: /* read word at location addr. */
	case PTRACE_PEEKDATA:
		ret = generic_ptrace_peekdata(child, addr, data);
		break;

	/* Read the word at location addr in the USER area. */
	case PTRACE_PEEKUSR: {
		struct pt_regs *regs;
		unsigned long tmp = 0;

		regs = task_pt_regs(child);
		ret = 0;  /* Default return value. */

		switch (addr) {
		case 0 ... 31:
			tmp = regs->regs[addr];
			break;
		case FPR_BASE ... FPR_BASE + 31:
			if (tsk_used_math(child)) {
				fpureg_t *fregs = get_fpu_regs(child);

#ifdef CONFIG_32BIT
				/*
				 * The odd registers are actually the high
				 * order bits of the values stored in the even
				 * registers - unless we're using r2k_switch.S.
				 */
				if (addr & 1)
					tmp = (unsigned long) (fregs[((addr & ~1) - 32)] >> 32);
				else
					tmp = (unsigned long) (fregs[(addr - 32)] & 0xffffffff);
#endif
#ifdef CONFIG_64BIT
				tmp = fregs[addr - FPR_BASE];
#endif
			} else {
				tmp = -1;	/* FP not yet used  */
			}
			break;
		case PC:
			tmp = regs->cp0_epc;
			break;
		case CAUSE:
			tmp = regs->cp0_cause;
			break;
		case BADVADDR:
			tmp = regs->cp0_badvaddr;
			break;
		case MMHI:
			tmp = regs->hi;
			break;
		case MMLO:
			tmp = regs->lo;
			break;
#ifdef CONFIG_CPU_HAS_SMARTMIPS
		case ACX:
			tmp = regs->acx;
			break;
#endif
		case FPC_CSR:
			tmp = child->thread.fpu.fcr31;
			break;
		case FPC_EIR: { /* implementation / version register */
			unsigned int flags;
#ifdef CONFIG_MIPS_MT_SMTC
			unsigned long irqflags;
			unsigned int mtflags;
#endif /* CONFIG_MIPS_MT_SMTC */

			preempt_disable();
			if (!cpu_has_fpu) {
				preempt_enable();
				break;
			}

#ifdef CONFIG_MIPS_MT_SMTC
			/* Read-modify-write of Status must be atomic */
			local_irq_save(irqflags);
			mtflags = dmt();
#endif /* CONFIG_MIPS_MT_SMTC */
			if (cpu_has_mipsmt) {
				unsigned int vpflags = dvpe();
				flags = read_c0_status();
				__enable_fpu();
				__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
				write_c0_status(flags);
				evpe(vpflags);
			} else {
				flags = read_c0_status();
				__enable_fpu();
				__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
				write_c0_status(flags);
			}
#ifdef CONFIG_MIPS_MT_SMTC
			emt(mtflags);
			local_irq_restore(irqflags);
#endif /* CONFIG_MIPS_MT_SMTC */
			preempt_enable();
			break;
		}
		case DSP_BASE ... DSP_BASE + 5: {
			dspreg_t *dregs;

			if (!cpu_has_dsp) {
				tmp = 0;
				ret = -EIO;
				goto out;
			}
			dregs = __get_dsp_regs(child);
			tmp = (unsigned long) (dregs[addr - DSP_BASE]);
			break;
		}
		case DSP_CONTROL:
			if (!cpu_has_dsp) {
				tmp = 0;
				ret = -EIO;
				goto out;
			}
			tmp = child->thread.dsp.dspcontrol;
			break;
		default:
			tmp = 0;
			ret = -EIO;
			goto out;
		}
		ret = put_user(tmp, datalp);
		break;
	}

	/* when I and D space are separate, this will have to be fixed. */
	case PTRACE_POKETEXT: /* write the word at location addr. */
	case PTRACE_POKEDATA:
		ret = generic_ptrace_pokedata(child, addr, data);
		break;

	case PTRACE_POKEUSR: {
		struct pt_regs *regs;
		ret = 0;
		regs = task_pt_regs(child);

		switch (addr) {
		case 0 ... 31:
			regs->regs[addr] = data;
			break;
		case FPR_BASE ... FPR_BASE + 31: {
			fpureg_t *fregs = get_fpu_regs(child);

			if (!tsk_used_math(child)) {
				/* FP not yet used  */
				memset(&child->thread.fpu, ~0,
				       sizeof(child->thread.fpu));
				child->thread.fpu.fcr31 = 0;
			}
#ifdef CONFIG_32BIT
			/*
			 * The odd registers are actually the high order bits
			 * of the values stored in the even registers - unless
			 * we're using r2k_switch.S.
			 */
			if (addr & 1) {
				fregs[(addr & ~1) - FPR_BASE] &= 0xffffffff;
				fregs[(addr & ~1) - FPR_BASE] |= ((unsigned long long) data) << 32;
			} else {
				fregs[addr - FPR_BASE] &= ~0xffffffffLL;
				fregs[addr - FPR_BASE] |= data;
			}
#endif
#ifdef CONFIG_64BIT
			fregs[addr - FPR_BASE] = data;
#endif
			break;
		}
		case PC:
			regs->cp0_epc = data;
			break;
		case MMHI:
			regs->hi = data;
			break;
		case MMLO:
			regs->lo = data;
			break;
#ifdef CONFIG_CPU_HAS_SMARTMIPS
		case ACX:
			regs->acx = data;
			break;
#endif
		case FPC_CSR:
			child->thread.fpu.fcr31 = data & ~FPU_CSR_ALL_X;
			break;
		case DSP_BASE ... DSP_BASE + 5: {
			dspreg_t *dregs;

			if (!cpu_has_dsp) {
				ret = -EIO;
				break;
			}

			dregs = __get_dsp_regs(child);
			dregs[addr - DSP_BASE] = data;
			break;
		}
		case DSP_CONTROL:
			if (!cpu_has_dsp) {
				ret = -EIO;
				break;
			}
			child->thread.dsp.dspcontrol = data;
			break;
		default:
			/* The rest are not allowed. */
			ret = -EIO;
			break;
		}
		break;
		}

	case PTRACE_GETREGS:
		ret = ptrace_getregs(child, datavp);
		break;

	case PTRACE_SETREGS:
		ret = ptrace_setregs(child, datavp);
		break;

	case PTRACE_GETFPREGS:
		ret = ptrace_getfpregs(child, datavp);
		break;

	case PTRACE_SETFPREGS:
		ret = ptrace_setfpregs(child, datavp);
		break;

	case PTRACE_GET_THREAD_AREA:
		ret = put_user(task_thread_info(child)->tp_value, datalp);
		break;

	case PTRACE_GET_WATCH_REGS:
		ret = ptrace_get_watch_regs(child, addrp);
		break;

	case PTRACE_SET_WATCH_REGS:
		ret = ptrace_set_watch_regs(child, addrp);
		break;

	default:
		ret = ptrace_request(child, request, addr, data);
		break;
	}
 out:
	return ret;
}

static inline int audit_arch(void)
{
	int arch = EM_MIPS;
#ifdef CONFIG_64BIT
	arch |=	 __AUDIT_ARCH_64BIT;
#endif
#if defined(__LITTLE_ENDIAN)
	arch |=	 __AUDIT_ARCH_LE;
#endif
	return arch;
}

/*
 * Notification of system call entry/exit
 * - triggered by current->work.syscall_trace
 */
asmlinkage void syscall_trace_enter(struct pt_regs *regs)
{
	/* do the secure computing check first */
	secure_computing_strict(regs->regs[2]);

	if (!(current->ptrace & PT_PTRACED))
		goto out;

	if (!test_thread_flag(TIF_SYSCALL_TRACE))
		goto out;

	/* The 0x80 provides a way for the tracing parent to distinguish
	   between a syscall stop and SIGTRAP delivery */
	ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ?
				 0x80 : 0));

	/*
	 * this isn't the same as continuing with a signal, but it will do
	 * for normal use.  strace only continues with a signal if the
	 * stopping signal is not SIGTRAP.  -brl
	 */
	if (current->exit_code) {
		send_sig(current->exit_code, current, 1);
		current->exit_code = 0;
	}

out:
	audit_syscall_entry(audit_arch(), regs->regs[2],
			    regs->regs[4], regs->regs[5],
			    regs->regs[6], regs->regs[7]);
}

/*
 * Notification of system call entry/exit
 * - triggered by current->work.syscall_trace
 */
asmlinkage void syscall_trace_leave(struct pt_regs *regs)
{
	audit_syscall_exit(regs);

	if (!(current->ptrace & PT_PTRACED))
		return;

	if (!test_thread_flag(TIF_SYSCALL_TRACE))
		return;

	/* The 0x80 provides a way for the tracing parent to distinguish
	   between a syscall stop and SIGTRAP delivery */
	ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ?
				 0x80 : 0));

	/*
	 * this isn't the same as continuing with a signal, but it will do
	 * for normal use.  strace only continues with a signal if the
	 * stopping signal is not SIGTRAP.  -brl
	 */
	if (current->exit_code) {
		send_sig(current->exit_code, current, 1);
		current->exit_code = 0;
	}
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1992 Ross Biro
	7	* Copyright (C) Linus Torvalds
	8	* Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
	9	* Copyright (C) 1996 David S. Miller
	10	* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
	11	* Copyright (C) 1999 MIPS Technologies, Inc.
	12	* Copyright (C) 2000 Ulf Carlsson
	13	*
	14	* At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
	15	* binaries.
	16	*/
1da177e4 LT	17	#include <linux/compiler.h>
	18	#include <linux/kernel.h>
	19	#include <linux/sched.h>
	20	#include <linux/mm.h>
	21	#include <linux/errno.h>
	22	#include <linux/ptrace.h>
1da177e4	23	#include <linux/smp.h>
1da177e4 LT	24	#include <linux/user.h>
1da177e4 LT	25	#include <linux/security.h>
293c5bd1 RB	26	#include <linux/audit.h>
293c5bd1 RB	27	#include <linux/seccomp.h>
1da177e4	28
f8280c8d	29	#include <asm/byteorder.h>
1da177e4	30	#include <asm/cpu.h>
e50c0a8f	31	#include <asm/dsp.h>
1da177e4 LT	32	#include <asm/fpu.h>
1da177e4 LT	33	#include <asm/mipsregs.h>
101b3531	34	#include <asm/mipsmtregs.h>
1da177e4 LT	35	#include <asm/pgtable.h>
1da177e4 LT	36	#include <asm/page.h>
1da177e4 LT	37	#include <asm/uaccess.h>
1da177e4 LT	38	#include <asm/bootinfo.h>
ea3d710f	39	#include <asm/reg.h>
1da177e4 LT	40
	41	/*
	42	* Called by kernel/ptrace.c when detaching..
	43	*
	44	* Make sure single step bits etc are not set.
	45	*/
	46	void ptrace_disable(struct task_struct *child)
	47	{
0926bf95 DD	48	/* Don't load the watchpoint registers for the ex-child. */
0926bf95 DD	49	clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
1da177e4 LT	50	}
1da177e4 LT	51
ea3d710f	52	/*
70342287	53	* Read a general register set. We always use the 64-bit format, even
ea3d710f DJ	54	* for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
	55	* Registers are sign extended to fill the available space.
	56	*/
49a89efb	57	int ptrace_getregs(struct task_struct child, __s64 __user data)
ea3d710f DJ	58	{
	59	struct pt_regs *regs;
	60	int i;
	61
	62	if (!access_ok(VERIFY_WRITE, data, 38 * 8))
	63	return -EIO;
	64
40bc9c67	65	regs = task_pt_regs(child);
ea3d710f DJ	66
ea3d710f DJ	67	for (i = 0; i < 32; i++)
62b14c24 AN	68	__put_user((long)regs->regs[i], data + i);
	69	__put_user((long)regs->lo, data + EF_LO - EF_R0);
	70	__put_user((long)regs->hi, data + EF_HI - EF_R0);
	71	__put_user((long)regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
	72	__put_user((long)regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0);
	73	__put_user((long)regs->cp0_status, data + EF_CP0_STATUS - EF_R0);
	74	__put_user((long)regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0);
ea3d710f DJ	75
	76	return 0;
	77	}
	78
	79	/*
	80	* Write a general register set. As for PTRACE_GETREGS, we always use
	81	* the 64-bit format. On a 32-bit kernel only the lower order half
	82	* (according to endianness) will be used.
	83	*/
49a89efb	84	int ptrace_setregs(struct task_struct child, __s64 __user data)
ea3d710f DJ	85	{
	86	struct pt_regs *regs;
	87	int i;
	88
	89	if (!access_ok(VERIFY_READ, data, 38 * 8))
	90	return -EIO;
	91
40bc9c67	92	regs = task_pt_regs(child);
ea3d710f DJ	93
ea3d710f DJ	94	for (i = 0; i < 32; i++)
49a89efb RB	95	__get_user(regs->regs[i], data + i);
	96	__get_user(regs->lo, data + EF_LO - EF_R0);
	97	__get_user(regs->hi, data + EF_HI - EF_R0);
	98	__get_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
ea3d710f DJ	99
	100	/* badvaddr, status, and cause may not be written. */
	101
	102	return 0;
	103	}
	104
49a89efb	105	int ptrace_getfpregs(struct task_struct child, __u32 __user data)
ea3d710f DJ	106	{
ea3d710f DJ	107	int i;
e04582b7	108	unsigned int tmp;
ea3d710f DJ	109
	110	if (!access_ok(VERIFY_WRITE, data, 33 * 8))
	111	return -EIO;
	112
	113	if (tsk_used_math(child)) {
	114	fpureg_t *fregs = get_fpu_regs(child);
	115	for (i = 0; i < 32; i++)
49a89efb	116	__put_user(fregs[i], i + (__u64 __user *) data);
ea3d710f DJ	117	} else {
ea3d710f DJ	118	for (i = 0; i < 32; i++)
49a89efb	119	__put_user((__u64) -1, i + (__u64 __user *) data);
ea3d710f DJ	120	}
ea3d710f DJ	121
49a89efb	122	__put_user(child->thread.fpu.fcr31, data + 64);
eae89076	123
e04582b7	124	preempt_disable();
ea3d710f	125	if (cpu_has_fpu) {
e04582b7	126	unsigned int flags;
ea3d710f	127
101b3531 RB	128	if (cpu_has_mipsmt) {
	129	unsigned int vpflags = dvpe();
	130	flags = read_c0_status();
	131	__enable_fpu();
	132	__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
	133	write_c0_status(flags);
	134	evpe(vpflags);
	135	} else {
	136	flags = read_c0_status();
	137	__enable_fpu();
	138	__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
	139	write_c0_status(flags);
	140	}
ea3d710f	141	} else {
e04582b7	142	tmp = 0;
ea3d710f	143	}
e04582b7	144	preempt_enable();
49a89efb	145	__put_user(tmp, data + 65);
ea3d710f DJ	146
	147	return 0;
	148	}
	149
49a89efb	150	int ptrace_setfpregs(struct task_struct child, __u32 __user data)
ea3d710f DJ	151	{
	152	fpureg_t *fregs;
	153	int i;
	154
	155	if (!access_ok(VERIFY_READ, data, 33 * 8))
	156	return -EIO;
	157
	158	fregs = get_fpu_regs(child);
	159
	160	for (i = 0; i < 32; i++)
49a89efb	161	__get_user(fregs[i], i + (__u64 __user *) data);
ea3d710f	162
49a89efb	163	__get_user(child->thread.fpu.fcr31, data + 64);
fbd9df2e	164	child->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
ea3d710f DJ	165
	166	/* FIR may not be written. */
	167
	168	return 0;
	169	}
	170
0926bf95 DD	171	int ptrace_get_watch_regs(struct task_struct *child,
	172	struct pt_watch_regs __user *addr)
	173	{
	174	enum pt_watch_style style;
	175	int i;
	176
	177	if (!cpu_has_watch \|\| current_cpu_data.watch_reg_use_cnt == 0)
	178	return -EIO;
	179	if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs)))
	180	return -EIO;
	181
	182	#ifdef CONFIG_32BIT
	183	style = pt_watch_style_mips32;
	184	#define WATCH_STYLE mips32
	185	#else
	186	style = pt_watch_style_mips64;
	187	#define WATCH_STYLE mips64
	188	#endif
	189
	190	__put_user(style, &addr->style);
	191	__put_user(current_cpu_data.watch_reg_use_cnt,
	192	&addr->WATCH_STYLE.num_valid);
	193	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
	194	__put_user(child->thread.watch.mips3264.watchlo[i],
	195	&addr->WATCH_STYLE.watchlo[i]);
	196	__put_user(child->thread.watch.mips3264.watchhi[i] & 0xfff,
	197	&addr->WATCH_STYLE.watchhi[i]);
	198	__put_user(current_cpu_data.watch_reg_masks[i],
	199	&addr->WATCH_STYLE.watch_masks[i]);
	200	}
	201	for (; i < 8; i++) {
	202	__put_user(0, &addr->WATCH_STYLE.watchlo[i]);
	203	__put_user(0, &addr->WATCH_STYLE.watchhi[i]);
	204	__put_user(0, &addr->WATCH_STYLE.watch_masks[i]);
	205	}
	206
	207	return 0;
	208	}
	209
	210	int ptrace_set_watch_regs(struct task_struct *child,
	211	struct pt_watch_regs __user *addr)
	212	{
	213	int i;
	214	int watch_active = 0;
	215	unsigned long lt[NUM_WATCH_REGS];
	216	u16 ht[NUM_WATCH_REGS];
	217
	218	if (!cpu_has_watch \|\| current_cpu_data.watch_reg_use_cnt == 0)
	219	return -EIO;
	220	if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs)))
	221	return -EIO;
	222	/* Check the values. */
	223	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
	224	__get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
	225	#ifdef CONFIG_32BIT
	226	if (lt[i] & __UA_LIMIT)
	227	return -EINVAL;
	228	#else
	229	if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) {
	230	if (lt[i] & 0xffffffff80000000UL)
	231	return -EINVAL;
	232	} else {
	233	if (lt[i] & __UA_LIMIT)
	234	return -EINVAL;
235	}
236	#endif
237	__get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
238	if (ht[i] & ~0xff8)
239	return -EINVAL;
240	}
241	/* Install them. */
242	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
243	if (lt[i] & 7)
244	watch_active = 1;
245	child->thread.watch.mips3264.watchlo[i] = lt[i];
246	/* Set the G bit. */
247	child->thread.watch.mips3264.watchhi[i] = ht[i];
248	}
249
250	if (watch_active)
251	set_tsk_thread_flag(child, TIF_LOAD_WATCH);
252	else
253	clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
254
255	return 0;
256	}
257
9b05a69e NK	258	long arch_ptrace(struct task_struct *child, long request,
9b05a69e NK	259	unsigned long addr, unsigned long data)
1da177e4	260	{
1da177e4	261	int ret;
fb671139 NK	262	void __user addrp = (void __user ) addr;
	263	void __user datavp = (void __user ) data;
	264	unsigned long __user datalp = (void __user ) data;
1da177e4	265
1da177e4 LT	266	switch (request) {
	267	/* when I and D space are separate, these will need to be fixed. */
	268	case PTRACE_PEEKTEXT: /* read word at location addr. */
76647323 AD	269	case PTRACE_PEEKDATA:
76647323 AD	270	ret = generic_ptrace_peekdata(child, addr, data);
1da177e4	271	break;
1da177e4 LT	272
	273	/* Read the word at location addr in the USER area. */
	274	case PTRACE_PEEKUSR: {
	275	struct pt_regs *regs;
	276	unsigned long tmp = 0;
	277
40bc9c67	278	regs = task_pt_regs(child);
1da177e4 LT	279	ret = 0; /* Default return value. */
	280
	281	switch (addr) {
	282	case 0 ... 31:
	283	tmp = regs->regs[addr];
	284	break;
	285	case FPR_BASE ... FPR_BASE + 31:
	286	if (tsk_used_math(child)) {
	287	fpureg_t *fregs = get_fpu_regs(child);
	288
875d43e7	289	#ifdef CONFIG_32BIT
1da177e4 LT	290	/*
	291	* The odd registers are actually the high
	292	* order bits of the values stored in the even
	293	* registers - unless we're using r2k_switch.S.
	294	*/
	295	if (addr & 1)
	296	tmp = (unsigned long) (fregs[((addr & ~1) - 32)] >> 32);
	297	else
	298	tmp = (unsigned long) (fregs[(addr - 32)] & 0xffffffff);
	299	#endif
875d43e7	300	#ifdef CONFIG_64BIT
1da177e4 LT	301	tmp = fregs[addr - FPR_BASE];
	302	#endif
	303	} else {
	304	tmp = -1; /* FP not yet used */
	305	}
	306	break;
	307	case PC:
	308	tmp = regs->cp0_epc;
	309	break;
	310	case CAUSE:
	311	tmp = regs->cp0_cause;
	312	break;
	313	case BADVADDR:
	314	tmp = regs->cp0_badvaddr;
	315	break;
	316	case MMHI:
	317	tmp = regs->hi;
	318	break;
	319	case MMLO:
	320	tmp = regs->lo;
	321	break;
9693a853 FBH	322	#ifdef CONFIG_CPU_HAS_SMARTMIPS
	323	case ACX:
	324	tmp = regs->acx;
	325	break;
	326	#endif
1da177e4	327	case FPC_CSR:
eae89076	328	tmp = child->thread.fpu.fcr31;
1da177e4	329	break;
70342287	330	case FPC_EIR: { /* implementation / version register */
1da177e4	331	unsigned int flags;
41c594ab	332	#ifdef CONFIG_MIPS_MT_SMTC
b7e4226e	333	unsigned long irqflags;
41c594ab RB	334	unsigned int mtflags;
41c594ab RB	335	#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4	336
e04582b7 AN	337	preempt_disable();
	338	if (!cpu_has_fpu) {
	339	preempt_enable();
1da177e4	340	break;
e04582b7	341	}
1da177e4	342
41c594ab RB	343	#ifdef CONFIG_MIPS_MT_SMTC
	344	/* Read-modify-write of Status must be atomic */
	345	local_irq_save(irqflags);
	346	mtflags = dmt();
	347	#endif /* CONFIG_MIPS_MT_SMTC */
101b3531 RB	348	if (cpu_has_mipsmt) {
	349	unsigned int vpflags = dvpe();
	350	flags = read_c0_status();
	351	__enable_fpu();
	352	__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
	353	write_c0_status(flags);
	354	evpe(vpflags);
	355	} else {
	356	flags = read_c0_status();
	357	__enable_fpu();
	358	__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
	359	write_c0_status(flags);
	360	}
41c594ab RB	361	#ifdef CONFIG_MIPS_MT_SMTC
	362	emt(mtflags);
	363	local_irq_restore(irqflags);
	364	#endif /* CONFIG_MIPS_MT_SMTC */
101b3531	365	preempt_enable();
1da177e4 LT	366	break;
1da177e4 LT	367	}
c134a5ec RB	368	case DSP_BASE ... DSP_BASE + 5: {
	369	dspreg_t *dregs;
	370
e50c0a8f RB	371	if (!cpu_has_dsp) {
	372	tmp = 0;
	373	ret = -EIO;
481bed45	374	goto out;
e50c0a8f	375	}
6c355852 RB	376	dregs = __get_dsp_regs(child);
6c355852 RB	377	tmp = (unsigned long) (dregs[addr - DSP_BASE]);
e50c0a8f	378	break;
c134a5ec	379	}
e50c0a8f RB	380	case DSP_CONTROL:
	381	if (!cpu_has_dsp) {
	382	tmp = 0;
	383	ret = -EIO;
481bed45	384	goto out;
e50c0a8f RB	385	}
	386	tmp = child->thread.dsp.dspcontrol;
	387	break;
1da177e4 LT	388	default:
	389	tmp = 0;
	390	ret = -EIO;
481bed45	391	goto out;
1da177e4	392	}
fb671139	393	ret = put_user(tmp, datalp);
1da177e4 LT	394	break;
	395	}
	396
	397	/* when I and D space are separate, this will have to be fixed. */
	398	case PTRACE_POKETEXT: /* write the word at location addr. */
	399	case PTRACE_POKEDATA:
f284ce72	400	ret = generic_ptrace_pokedata(child, addr, data);
1da177e4 LT	401	break;
	402
	403	case PTRACE_POKEUSR: {
	404	struct pt_regs *regs;
	405	ret = 0;
40bc9c67	406	regs = task_pt_regs(child);
1da177e4 LT	407
	408	switch (addr) {
	409	case 0 ... 31:
	410	regs->regs[addr] = data;
	411	break;
	412	case FPR_BASE ... FPR_BASE + 31: {
	413	fpureg_t *fregs = get_fpu_regs(child);
	414
	415	if (!tsk_used_math(child)) {
	416	/* FP not yet used */
eae89076 AN	417	memset(&child->thread.fpu, ~0,
	418	sizeof(child->thread.fpu));
	419	child->thread.fpu.fcr31 = 0;
1da177e4	420	}
875d43e7	421	#ifdef CONFIG_32BIT
1da177e4 LT	422	/*
	423	* The odd registers are actually the high order bits
	424	* of the values stored in the even registers - unless
	425	* we're using r2k_switch.S.
	426	*/
	427	if (addr & 1) {
	428	fregs[(addr & ~1) - FPR_BASE] &= 0xffffffff;
	429	fregs[(addr & ~1) - FPR_BASE] \|= ((unsigned long long) data) << 32;
	430	} else {
	431	fregs[addr - FPR_BASE] &= ~0xffffffffLL;
	432	fregs[addr - FPR_BASE] \|= data;
	433	}
	434	#endif
875d43e7	435	#ifdef CONFIG_64BIT
1da177e4 LT	436	fregs[addr - FPR_BASE] = data;
	437	#endif
	438	break;
	439	}
	440	case PC:
	441	regs->cp0_epc = data;
	442	break;
	443	case MMHI:
	444	regs->hi = data;
	445	break;
	446	case MMLO:
	447	regs->lo = data;
	448	break;
9693a853 FBH	449	#ifdef CONFIG_CPU_HAS_SMARTMIPS
	450	case ACX:
	451	regs->acx = data;
	452	break;
	453	#endif
1da177e4	454	case FPC_CSR:
fbd9df2e	455	child->thread.fpu.fcr31 = data & ~FPU_CSR_ALL_X;
1da177e4	456	break;
c134a5ec RB	457	case DSP_BASE ... DSP_BASE + 5: {
	458	dspreg_t *dregs;
	459
e50c0a8f RB	460	if (!cpu_has_dsp) {
	461	ret = -EIO;
	462	break;
	463	}
	464
c134a5ec	465	dregs = __get_dsp_regs(child);
e50c0a8f RB	466	dregs[addr - DSP_BASE] = data;
e50c0a8f RB	467	break;
c134a5ec	468	}
e50c0a8f RB	469	case DSP_CONTROL:
	470	if (!cpu_has_dsp) {
	471	ret = -EIO;
	472	break;
	473	}
	474	child->thread.dsp.dspcontrol = data;
	475	break;
1da177e4 LT	476	default:
	477	/* The rest are not allowed. */
	478	ret = -EIO;
	479	break;
	480	}
	481	break;
	482	}
	483
ea3d710f	484	case PTRACE_GETREGS:
fb671139	485	ret = ptrace_getregs(child, datavp);
ea3d710f DJ	486	break;
	487
	488	case PTRACE_SETREGS:
fb671139	489	ret = ptrace_setregs(child, datavp);
ea3d710f DJ	490	break;
	491
	492	case PTRACE_GETFPREGS:
fb671139	493	ret = ptrace_getfpregs(child, datavp);
ea3d710f DJ	494	break;
	495
	496	case PTRACE_SETFPREGS:
fb671139	497	ret = ptrace_setfpregs(child, datavp);
ea3d710f DJ	498	break;
ea3d710f DJ	499
3c37026d	500	case PTRACE_GET_THREAD_AREA:
fb671139	501	ret = put_user(task_thread_info(child)->tp_value, datalp);
3c37026d RB	502	break;
3c37026d RB	503
0926bf95	504	case PTRACE_GET_WATCH_REGS:
fb671139	505	ret = ptrace_get_watch_regs(child, addrp);
0926bf95 DD	506	break;
	507
	508	case PTRACE_SET_WATCH_REGS:
fb671139	509	ret = ptrace_set_watch_regs(child, addrp);
0926bf95 DD	510	break;
0926bf95 DD	511
1da177e4 LT	512	default:
	513	ret = ptrace_request(child, request, addr, data);
	514	break;
	515	}
481bed45	516	out:
1da177e4 LT	517	return ret;
	518	}
	519
67eb81e1	520	static inline int audit_arch(void)
2fd6f58b	521	{
f8280c8d	522	int arch = EM_MIPS;
875d43e7	523	#ifdef CONFIG_64BIT
70342287	524	arch \|= __AUDIT_ARCH_64BIT;
f8280c8d RB	525	#endif
f8280c8d RB	526	#if defined(__LITTLE_ENDIAN)
70342287	527	arch \|= __AUDIT_ARCH_LE;
f8280c8d RB	528	#endif
f8280c8d RB	529	return arch;
2fd6f58b DW	530	}
2fd6f58b DW	531
1da177e4 LT	532	/*
	533	* Notification of system call entry/exit
	534	* - triggered by current->work.syscall_trace
	535	*/
8b659a39	536	asmlinkage void syscall_trace_enter(struct pt_regs *regs)
1da177e4	537	{
293c5bd1	538	/* do the secure computing check first */
e4da89d0	539	secure_computing_strict(regs->regs[2]);
1da177e4	540
1da177e4	541	if (!(current->ptrace & PT_PTRACED))
2fd6f58b	542	goto out;
293c5bd1	543
f8280c8d RB	544	if (!test_thread_flag(TIF_SYSCALL_TRACE))
f8280c8d RB	545	goto out;
1da177e4 LT	546
	547	/* The 0x80 provides a way for the tracing parent to distinguish
	548	between a syscall stop and SIGTRAP delivery */
	549	ptrace_notify(SIGTRAP \| ((current->ptrace & PT_TRACESYSGOOD) ?
70342287	550	0x80 : 0));
1da177e4 LT	551
	552	/*
	553	* this isn't the same as continuing with a signal, but it will do
	554	* for normal use. strace only continues with a signal if the
	555	* stopping signal is not SIGTRAP. -brl
	556	*/
	557	if (current->exit_code) {
	558	send_sig(current->exit_code, current, 1);
	559	current->exit_code = 0;
	560	}
293c5bd1 RB	561
293c5bd1 RB	562	out:
b05d8447 EP	563	audit_syscall_entry(audit_arch(), regs->regs[2],
	564	regs->regs[4], regs->regs[5],
	565	regs->regs[6], regs->regs[7]);
1da177e4	566	}
8b659a39 RB	567
	568	/*
	569	* Notification of system call entry/exit
	570	* - triggered by current->work.syscall_trace
	571	*/
	572	asmlinkage void syscall_trace_leave(struct pt_regs *regs)
	573	{
d7e7528b	574	audit_syscall_exit(regs);
8b659a39 RB	575
	576	if (!(current->ptrace & PT_PTRACED))
	577	return;
	578
	579	if (!test_thread_flag(TIF_SYSCALL_TRACE))
	580	return;
	581
	582	/* The 0x80 provides a way for the tracing parent to distinguish
	583	between a syscall stop and SIGTRAP delivery */
	584	ptrace_notify(SIGTRAP \| ((current->ptrace & PT_TRACESYSGOOD) ?
70342287	585	0x80 : 0));
8b659a39 RB	586
	587	/*
	588	* this isn't the same as continuing with a signal, but it will do
	589	* for normal use. strace only continues with a signal if the
	590	* stopping signal is not SIGTRAP. -brl
	591	*/
	592	if (current->exit_code) {
	593	send_sig(current->exit_code, current, 1);
	594	current->exit_code = 0;
	595	}
	596	}