[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / kernel / irq-gic.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
 * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
 */
#include <linux/bitmap.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/irq.h>
#include <linux/clocksource.h>

#include <asm/io.h>
#include <asm/gic.h>
#include <asm/setup.h>
#include <asm/traps.h>
#include <asm/gcmpregs.h>
#include <linux/hardirq.h>
#include <asm-generic/bitops/find.h>

unsigned int gic_frequency;
unsigned int gic_present;
unsigned long _gic_base;
unsigned int gic_irq_base;
unsigned int gic_irq_flags[GIC_NUM_INTRS];

/* The index into this array is the vector # of the interrupt. */
struct gic_shared_intr_map gic_shared_intr_map[GIC_NUM_INTRS];

static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
static struct gic_pending_regs pending_regs[NR_CPUS];
static struct gic_intrmask_regs intrmask_regs[NR_CPUS];

#if defined(CONFIG_CSRC_GIC) || defined(CONFIG_CEVT_GIC)
cycle_t gic_read_count(void)
{
	unsigned int hi, hi2, lo;

	do {
		GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi);
		GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), lo);
		GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi2);
	} while (hi2 != hi);

	return (((cycle_t) hi) << 32) + lo;
}

void gic_write_compare(cycle_t cnt)
{
	GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),
				(int)(cnt >> 32));
	GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),
				(int)(cnt & 0xffffffff));
}

cycle_t gic_read_compare(void)
{
	unsigned int hi, lo;

	GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI), hi);
	GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO), lo);

	return (((cycle_t) hi) << 32) + lo;
}
#endif

unsigned int gic_get_timer_pending(void)
{
	unsigned int vpe_pending;

	GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), 0);
	GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_PEND), vpe_pending);
	return (vpe_pending & GIC_VPE_PEND_TIMER_MSK);
}

void gic_bind_eic_interrupt(int irq, int set)
{
	/* Convert irq vector # to hw int # */
	irq -= GIC_PIN_TO_VEC_OFFSET;

	/* Set irq to use shadow set */
	GICWRITE(GIC_REG_ADDR(VPE_LOCAL, GIC_VPE_EIC_SS(irq)), set);
}

void gic_send_ipi(unsigned int intr)
{
	GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
}

static void gic_eic_irq_dispatch(void)
{
	unsigned int cause = read_c0_cause();
	int irq;

	irq = (cause & ST0_IM) >> STATUSB_IP2;
	if (irq == 0)
		irq = -1;

	if (irq >= 0)
		do_IRQ(gic_irq_base + irq);
	else
		spurious_interrupt();
}

static void __init vpe_local_setup(unsigned int numvpes)
{
	unsigned long timer_intr = GIC_INT_TMR;
	unsigned long perf_intr = GIC_INT_PERFCTR;
	unsigned int vpe_ctl;
	int i;

	if (cpu_has_veic) {
		/*
		 * GIC timer interrupt -> CPU HW Int X (vector X+2) ->
		 * map to pin X+2-1 (since GIC adds 1)
		 */
		timer_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
		/*
		 * GIC perfcnt interrupt -> CPU HW Int X (vector X+2) ->
		 * map to pin X+2-1 (since GIC adds 1)
		 */
		perf_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
	}

	/*
	 * Setup the default performance counter timer interrupts
	 * for all VPEs
	 */
	for (i = 0; i < numvpes; i++) {
		GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);

		/* Are Interrupts locally routable? */
		GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl);
		if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK)
			GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
				 GIC_MAP_TO_PIN_MSK | timer_intr);
		if (cpu_has_veic) {
			set_vi_handler(timer_intr + GIC_PIN_TO_VEC_OFFSET,
				gic_eic_irq_dispatch);
			gic_shared_intr_map[timer_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_TIMER_MSK;
		}

		if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
			GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
				 GIC_MAP_TO_PIN_MSK | perf_intr);
		if (cpu_has_veic) {
			set_vi_handler(perf_intr + GIC_PIN_TO_VEC_OFFSET, gic_eic_irq_dispatch);
			gic_shared_intr_map[perf_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_PERFCNT_MSK;
		}
	}
}

unsigned int gic_compare_int(void)
{
	unsigned int pending;

	GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_PEND), pending);
	if (pending & GIC_VPE_PEND_CMP_MSK)
		return 1;
	else
		return 0;
}

unsigned int gic_get_int(void)
{
	unsigned int i;
	unsigned long *pending, *intrmask, *pcpu_mask;
	unsigned long *pending_abs, *intrmask_abs;

	/* Get per-cpu bitmaps */
	pending = pending_regs[smp_processor_id()].pending;
	intrmask = intrmask_regs[smp_processor_id()].intrmask;
	pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;

	pending_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
							 GIC_SH_PEND_31_0_OFS);
	intrmask_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
							  GIC_SH_MASK_31_0_OFS);

	for (i = 0; i < BITS_TO_LONGS(GIC_NUM_INTRS); i++) {
		GICREAD(*pending_abs, pending[i]);
		GICREAD(*intrmask_abs, intrmask[i]);
		pending_abs++;
		intrmask_abs++;
	}

	bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
	bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);

	return find_first_bit(pending, GIC_NUM_INTRS);
}

static void gic_mask_irq(struct irq_data *d)
{
	GIC_CLR_INTR_MASK(d->irq - gic_irq_base);
}

static void gic_unmask_irq(struct irq_data *d)
{
	GIC_SET_INTR_MASK(d->irq - gic_irq_base);
}

#ifdef CONFIG_SMP
static DEFINE_SPINLOCK(gic_lock);

static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
			    bool force)
{
	unsigned int irq = (d->irq - gic_irq_base);
	cpumask_t	tmp = CPU_MASK_NONE;
	unsigned long	flags;
	int		i;

	cpumask_and(&tmp, cpumask, cpu_online_mask);
	if (cpus_empty(tmp))
		return -1;

	/* Assumption : cpumask refers to a single CPU */
	spin_lock_irqsave(&gic_lock, flags);
	for (;;) {
		/* Re-route this IRQ */
		GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));

		/* Update the pcpu_masks */
		for (i = 0; i < NR_CPUS; i++)
			clear_bit(irq, pcpu_masks[i].pcpu_mask);
		set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);

	}
	cpumask_copy(d->affinity, cpumask);
	spin_unlock_irqrestore(&gic_lock, flags);

	return IRQ_SET_MASK_OK_NOCOPY;
}
#endif

static struct irq_chip gic_irq_controller = {
	.name			=	"MIPS GIC",
	.irq_ack		=	gic_irq_ack,
	.irq_mask		=	gic_mask_irq,
	.irq_mask_ack		=	gic_mask_irq,
	.irq_unmask		=	gic_unmask_irq,
	.irq_eoi		=	gic_finish_irq,
#ifdef CONFIG_SMP
	.irq_set_affinity	=	gic_set_affinity,
#endif
};

static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
	unsigned int pin, unsigned int polarity, unsigned int trigtype,
	unsigned int flags)
{
	struct gic_shared_intr_map *map_ptr;

	/* Setup Intr to Pin mapping */
	if (pin & GIC_MAP_TO_NMI_MSK) {
		int i;

		GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
		/* FIXME: hack to route NMI to all cpu's */
		for (i = 0; i < NR_CPUS; i += 32) {
			GICWRITE(GIC_REG_ADDR(SHARED,
					  GIC_SH_MAP_TO_VPE_REG_OFF(intr, i)),
				 0xffffffff);
		}
	} else {
		GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
			 GIC_MAP_TO_PIN_MSK | pin);
		/* Setup Intr to CPU mapping */
		GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
		if (cpu_has_veic) {
			set_vi_handler(pin + GIC_PIN_TO_VEC_OFFSET,
				gic_eic_irq_dispatch);
			map_ptr = &gic_shared_intr_map[pin + GIC_PIN_TO_VEC_OFFSET];
			if (map_ptr->num_shared_intr >= GIC_MAX_SHARED_INTR)
				BUG();
			map_ptr->intr_list[map_ptr->num_shared_intr++] = intr;
		}
	}

	/* Setup Intr Polarity */
	GIC_SET_POLARITY(intr, polarity);

	/* Setup Intr Trigger Type */
	GIC_SET_TRIGGER(intr, trigtype);

	/* Init Intr Masks */
	GIC_CLR_INTR_MASK(intr);
	/* Initialise per-cpu Interrupt software masks */
	if (flags & GIC_FLAG_IPI)
		set_bit(intr, pcpu_masks[cpu].pcpu_mask);
	if ((flags & GIC_FLAG_TRANSPARENT) && (cpu_has_veic == 0))
		GIC_SET_INTR_MASK(intr);
	if (trigtype == GIC_TRIG_EDGE)
		gic_irq_flags[intr] |= GIC_TRIG_EDGE;
}

static void __init gic_basic_init(int numintrs, int numvpes,
			struct gic_intr_map *intrmap, int mapsize)
{
	unsigned int i, cpu;
	unsigned int pin_offset = 0;

	board_bind_eic_interrupt = &gic_bind_eic_interrupt;

	/* Setup defaults */
	for (i = 0; i < numintrs; i++) {
		GIC_SET_POLARITY(i, GIC_POL_POS);
		GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
		GIC_CLR_INTR_MASK(i);
		if (i < GIC_NUM_INTRS) {
			gic_irq_flags[i] = 0;
			gic_shared_intr_map[i].num_shared_intr = 0;
			gic_shared_intr_map[i].local_intr_mask = 0;
		}
	}

	/*
	 * In EIC mode, the HW_INT# is offset by (2-1). Need to subtract
	 * one because the GIC will add one (since 0=no intr).
	 */
	if (cpu_has_veic)
		pin_offset = (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);

	/* Setup specifics */
	for (i = 0; i < mapsize; i++) {
		cpu = intrmap[i].cpunum;
		if (cpu == GIC_UNUSED)
			continue;
		if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
			continue;
		gic_setup_intr(i,
			intrmap[i].cpunum,
			intrmap[i].pin + pin_offset,
			intrmap[i].polarity,
			intrmap[i].trigtype,
			intrmap[i].flags);
	}

	vpe_local_setup(numvpes);
}

void __init gic_init(unsigned long gic_base_addr,
		     unsigned long gic_addrspace_size,
		     struct gic_intr_map *intr_map, unsigned int intr_map_size,
		     unsigned int irqbase)
{
	unsigned int gicconfig;
	int numvpes, numintrs;

	_gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
						    gic_addrspace_size);
	gic_irq_base = irqbase;

	GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
	numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
		   GIC_SH_CONFIG_NUMINTRS_SHF;
	numintrs = ((numintrs + 1) * 8);

	numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
		  GIC_SH_CONFIG_NUMVPES_SHF;
	numvpes = numvpes + 1;

	gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);

	gic_platform_init(numintrs, &gic_irq_controller);
}
Commit	Line	Data
2299c49d SH	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
	7	* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
	8	*/
39b8d525 RB	9	#include <linux/bitmap.h>
39b8d525 RB	10	#include <linux/init.h>
631330f5	11	#include <linux/smp.h>
ca4d3e67	12	#include <linux/irq.h>
dfa762e1	13	#include <linux/clocksource.h>
39b8d525 RB	14
	15	#include <asm/io.h>
	16	#include <asm/gic.h>
98b67c37 SH	17	#include <asm/setup.h>
98b67c37 SH	18	#include <asm/traps.h>
39b8d525	19	#include <asm/gcmpregs.h>
39b8d525 RB	20	#include <linux/hardirq.h>
	21	#include <asm-generic/bitops/find.h>
	22
28ea2151	23	unsigned int gic_frequency;
ff86714f	24	unsigned int gic_present;
0b271f56 SH	25	unsigned long _gic_base;
	26	unsigned int gic_irq_base;
	27	unsigned int gic_irq_flags[GIC_NUM_INTRS];
39b8d525	28
98b67c37 SH	29	/* The index into this array is the vector # of the interrupt. */
	30	struct gic_shared_intr_map gic_shared_intr_map[GIC_NUM_INTRS];
	31
0b271f56	32	static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
39b8d525 RB	33	static struct gic_pending_regs pending_regs[NR_CPUS];
	34	static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
	35
0ab2b7d0	36	#if defined(CONFIG_CSRC_GIC) \|\| defined(CONFIG_CEVT_GIC)
dfa762e1 SH	37	cycle_t gic_read_count(void)
	38	{
	39	unsigned int hi, hi2, lo;
	40
	41	do {
	42	GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi);
	43	GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), lo);
	44	GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi2);
	45	} while (hi2 != hi);
	46
	47	return (((cycle_t) hi) << 32) + lo;
	48	}
0ab2b7d0 RG	49
	50	void gic_write_compare(cycle_t cnt)
	51	{
	52	GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),
	53	(int)(cnt >> 32));
	54	GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),
	55	(int)(cnt & 0xffffffff));
	56	}
	57
	58	cycle_t gic_read_compare(void)
	59	{
	60	unsigned int hi, lo;
	61
	62	GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI), hi);
	63	GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO), lo);
	64
	65	return (((cycle_t) hi) << 32) + lo;
	66	}
dfa762e1 SH	67	#endif
dfa762e1 SH	68
98b67c37 SH	69	unsigned int gic_get_timer_pending(void)
	70	{
	71	unsigned int vpe_pending;
	72
	73	GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), 0);
	74	GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_PEND), vpe_pending);
	75	return (vpe_pending & GIC_VPE_PEND_TIMER_MSK);
	76	}
	77
	78	void gic_bind_eic_interrupt(int irq, int set)
	79	{
	80	/* Convert irq vector # to hw int # */
	81	irq -= GIC_PIN_TO_VEC_OFFSET;
	82
	83	/* Set irq to use shadow set */
	84	GICWRITE(GIC_REG_ADDR(VPE_LOCAL, GIC_VPE_EIC_SS(irq)), set);
	85	}
	86
39b8d525 RB	87	void gic_send_ipi(unsigned int intr)
39b8d525 RB	88	{
39b8d525	89	GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 \| intr);
39b8d525 RB	90	}
39b8d525 RB	91
98b67c37 SH	92	static void gic_eic_irq_dispatch(void)
	93	{
	94	unsigned int cause = read_c0_cause();
	95	int irq;
	96
	97	irq = (cause & ST0_IM) >> STATUSB_IP2;
	98	if (irq == 0)
	99	irq = -1;
	100
	101	if (irq >= 0)
	102	do_IRQ(gic_irq_base + irq);
	103	else
	104	spurious_interrupt();
	105	}
	106
7098f748	107	static void __init vpe_local_setup(unsigned int numvpes)
39b8d525	108	{
98b67c37 SH	109	unsigned long timer_intr = GIC_INT_TMR;
98b67c37 SH	110	unsigned long perf_intr = GIC_INT_PERFCTR;
39b8d525	111	unsigned int vpe_ctl;
2299c49d	112	int i;
39b8d525	113
98b67c37 SH	114	if (cpu_has_veic) {
	115	/*
	116	* GIC timer interrupt -> CPU HW Int X (vector X+2) ->
	117	* map to pin X+2-1 (since GIC adds 1)
	118	*/
	119	timer_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
	120	/*
	121	* GIC perfcnt interrupt -> CPU HW Int X (vector X+2) ->
	122	* map to pin X+2-1 (since GIC adds 1)
	123	*/
	124	perf_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
	125	}
	126
39b8d525 RB	127	/*
	128	* Setup the default performance counter timer interrupts
	129	* for all VPEs
	130	*/
	131	for (i = 0; i < numvpes; i++) {
	132	GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
	133
	134	/* Are Interrupts locally routable? */
	135	GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl);
	136	if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK)
	137	GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
98b67c37 SH	138	GIC_MAP_TO_PIN_MSK \| timer_intr);
	139	if (cpu_has_veic) {
	140	set_vi_handler(timer_intr + GIC_PIN_TO_VEC_OFFSET,
	141	gic_eic_irq_dispatch);
	142	gic_shared_intr_map[timer_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask \|= GIC_VPE_RMASK_TIMER_MSK;
	143	}
39b8d525 RB	144
	145	if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
	146	GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
98b67c37 SH	147	GIC_MAP_TO_PIN_MSK \| perf_intr);
	148	if (cpu_has_veic) {
	149	set_vi_handler(perf_intr + GIC_PIN_TO_VEC_OFFSET, gic_eic_irq_dispatch);
	150	gic_shared_intr_map[perf_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask \|= GIC_VPE_RMASK_PERFCNT_MSK;
	151	}
39b8d525 RB	152	}
	153	}
	154
0ab2b7d0 RG	155	unsigned int gic_compare_int(void)
	156	{
	157	unsigned int pending;
	158
	159	GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_PEND), pending);
	160	if (pending & GIC_VPE_PEND_CMP_MSK)
	161	return 1;
	162	else
	163	return 0;
	164	}
	165
39b8d525 RB	166	unsigned int gic_get_int(void)
	167	{
	168	unsigned int i;
	169	unsigned long pending, intrmask, *pcpu_mask;
	170	unsigned long pending_abs, intrmask_abs;
	171
	172	/* Get per-cpu bitmaps */
	173	pending = pending_regs[smp_processor_id()].pending;
	174	intrmask = intrmask_regs[smp_processor_id()].intrmask;
	175	pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
	176
	177	pending_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
	178	GIC_SH_PEND_31_0_OFS);
	179	intrmask_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
	180	GIC_SH_MASK_31_0_OFS);
	181
	182	for (i = 0; i < BITS_TO_LONGS(GIC_NUM_INTRS); i++) {
	183	GICREAD(*pending_abs, pending[i]);
	184	GICREAD(*intrmask_abs, intrmask[i]);
	185	pending_abs++;
	186	intrmask_abs++;
	187	}
	188
	189	bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
	190	bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);
	191
2299c49d	192	return find_first_bit(pending, GIC_NUM_INTRS);
39b8d525 RB	193	}
39b8d525 RB	194
161d049e	195	static void gic_mask_irq(struct irq_data *d)
39b8d525	196	{
2299c49d	197	GIC_CLR_INTR_MASK(d->irq - gic_irq_base);
39b8d525 RB	198	}
39b8d525 RB	199
161d049e	200	static void gic_unmask_irq(struct irq_data *d)
39b8d525	201	{
2299c49d	202	GIC_SET_INTR_MASK(d->irq - gic_irq_base);
39b8d525 RB	203	}
	204
	205	#ifdef CONFIG_SMP
39b8d525 RB	206	static DEFINE_SPINLOCK(gic_lock);
39b8d525 RB	207
161d049e TG	208	static int gic_set_affinity(struct irq_data d, const struct cpumask cpumask,
161d049e TG	209	bool force)
39b8d525	210	{
2299c49d	211	unsigned int irq = (d->irq - gic_irq_base);
39b8d525 RB	212	cpumask_t tmp = CPU_MASK_NONE;
	213	unsigned long flags;
	214	int i;
	215
0de26520	216	cpumask_and(&tmp, cpumask, cpu_online_mask);
39b8d525	217	if (cpus_empty(tmp))
d5dedd45	218	return -1;
39b8d525 RB	219
	220	/* Assumption : cpumask refers to a single CPU */
	221	spin_lock_irqsave(&gic_lock, flags);
	222	for (;;) {
	223	/* Re-route this IRQ */
	224	GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
	225
39b8d525 RB	226	/* Update the pcpu_masks */
	227	for (i = 0; i < NR_CPUS; i++)
	228	clear_bit(irq, pcpu_masks[i].pcpu_mask);
	229	set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
	230
	231	}
161d049e	232	cpumask_copy(d->affinity, cpumask);
39b8d525 RB	233	spin_unlock_irqrestore(&gic_lock, flags);
39b8d525 RB	234
161d049e	235	return IRQ_SET_MASK_OK_NOCOPY;
39b8d525 RB	236	}
	237	#endif
	238
	239	static struct irq_chip gic_irq_controller = {
161d049e TG	240	.name = "MIPS GIC",
	241	.irq_ack = gic_irq_ack,
	242	.irq_mask = gic_mask_irq,
	243	.irq_mask_ack = gic_mask_irq,
	244	.irq_unmask = gic_unmask_irq,
ec167f2d	245	.irq_eoi = gic_finish_irq,
39b8d525	246	#ifdef CONFIG_SMP
161d049e	247	.irq_set_affinity = gic_set_affinity,
39b8d525 RB	248	#endif
	249	};
	250
7098f748 CD	251	static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
	252	unsigned int pin, unsigned int polarity, unsigned int trigtype,
	253	unsigned int flags)
39b8d525	254	{
98b67c37 SH	255	struct gic_shared_intr_map *map_ptr;
98b67c37 SH	256
39b8d525 RB	257	/* Setup Intr to Pin mapping */
39b8d525 RB	258	if (pin & GIC_MAP_TO_NMI_MSK) {
f52337e5 JD	259	int i;
f52337e5 JD	260
39b8d525 RB	261	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
39b8d525 RB	262	/* FIXME: hack to route NMI to all cpu's */
f52337e5	263	for (i = 0; i < NR_CPUS; i += 32) {
39b8d525	264	GICWRITE(GIC_REG_ADDR(SHARED,
f52337e5	265	GIC_SH_MAP_TO_VPE_REG_OFF(intr, i)),
39b8d525 RB	266	0xffffffff);
	267	}
	268	} else {
	269	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
	270	GIC_MAP_TO_PIN_MSK \| pin);
	271	/* Setup Intr to CPU mapping */
	272	GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
98b67c37 SH	273	if (cpu_has_veic) {
	274	set_vi_handler(pin + GIC_PIN_TO_VEC_OFFSET,
	275	gic_eic_irq_dispatch);
	276	map_ptr = &gic_shared_intr_map[pin + GIC_PIN_TO_VEC_OFFSET];
	277	if (map_ptr->num_shared_intr >= GIC_MAX_SHARED_INTR)
	278	BUG();
	279	map_ptr->intr_list[map_ptr->num_shared_intr++] = intr;
	280	}
39b8d525 RB	281	}
	282
	283	/* Setup Intr Polarity */
	284	GIC_SET_POLARITY(intr, polarity);
	285
	286	/* Setup Intr Trigger Type */
	287	GIC_SET_TRIGGER(intr, trigtype);
	288
	289	/* Init Intr Masks */
7098f748 CD	290	GIC_CLR_INTR_MASK(intr);
	291	/* Initialise per-cpu Interrupt software masks */
	292	if (flags & GIC_FLAG_IPI)
	293	set_bit(intr, pcpu_masks[cpu].pcpu_mask);
98b67c37	294	if ((flags & GIC_FLAG_TRANSPARENT) && (cpu_has_veic == 0))
7098f748 CD	295	GIC_SET_INTR_MASK(intr);
7098f748 CD	296	if (trigtype == GIC_TRIG_EDGE)
0b271f56	297	gic_irq_flags[intr] \|= GIC_TRIG_EDGE;
39b8d525 RB	298	}
39b8d525 RB	299
7098f748 CD	300	static void __init gic_basic_init(int numintrs, int numvpes,
7098f748 CD	301	struct gic_intr_map *intrmap, int mapsize)
39b8d525 RB	302	{
39b8d525 RB	303	unsigned int i, cpu;
98b67c37 SH	304	unsigned int pin_offset = 0;
	305
	306	board_bind_eic_interrupt = &gic_bind_eic_interrupt;
39b8d525 RB	307
39b8d525 RB	308	/* Setup defaults */
7098f748	309	for (i = 0; i < numintrs; i++) {
39b8d525 RB	310	GIC_SET_POLARITY(i, GIC_POL_POS);
39b8d525 RB	311	GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
7098f748	312	GIC_CLR_INTR_MASK(i);
98b67c37	313	if (i < GIC_NUM_INTRS) {
7098f748	314	gic_irq_flags[i] = 0;
98b67c37 SH	315	gic_shared_intr_map[i].num_shared_intr = 0;
	316	gic_shared_intr_map[i].local_intr_mask = 0;
	317	}
39b8d525 RB	318	}
39b8d525 RB	319
98b67c37 SH	320	/*
	321	* In EIC mode, the HW_INT# is offset by (2-1). Need to subtract
	322	* one because the GIC will add one (since 0=no intr).
	323	*/
	324	if (cpu_has_veic)
	325	pin_offset = (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
	326
39b8d525	327	/* Setup specifics */
7098f748 CD	328	for (i = 0; i < mapsize; i++) {
7098f748 CD	329	cpu = intrmap[i].cpunum;
863cb9ba	330	if (cpu == GIC_UNUSED)
39b8d525	331	continue;
7098f748	332	if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
a214cef9	333	continue;
7098f748 CD	334	gic_setup_intr(i,
7098f748 CD	335	intrmap[i].cpunum,
98b67c37	336	intrmap[i].pin + pin_offset,
7098f748 CD	337	intrmap[i].polarity,
	338	intrmap[i].trigtype,
	339	intrmap[i].flags);
39b8d525 RB	340	}
	341
	342	vpe_local_setup(numvpes);
39b8d525 RB	343	}
	344
	345	void __init gic_init(unsigned long gic_base_addr,
	346	unsigned long gic_addrspace_size,
	347	struct gic_intr_map *intr_map, unsigned int intr_map_size,
	348	unsigned int irqbase)
	349	{
	350	unsigned int gicconfig;
7098f748	351	int numvpes, numintrs;
39b8d525 RB	352
	353	_gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
	354	gic_addrspace_size);
0b271f56	355	gic_irq_base = irqbase;
39b8d525 RB	356
	357	GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
	358	numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
	359	GIC_SH_CONFIG_NUMINTRS_SHF;
	360	numintrs = ((numintrs + 1) * 8);
	361
	362	numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
	363	GIC_SH_CONFIG_NUMVPES_SHF;
3234f446	364	numvpes = numvpes + 1;
39b8d525	365
7098f748	366	gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);
0b271f56 SH	367
0b271f56 SH	368	gic_platform_init(numintrs, &gic_irq_controller);
39b8d525	369	}