[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / kernel / head.S

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994, 1995 Waldorf Electronics
 * Written by Ralf Baechle and Andreas Busse
 * Copyright (C) 1994 - 99, 2003, 06 Ralf Baechle
 * Copyright (C) 1996 Paul M. Antoine
 * Modified for DECStation and hence R3000 support by Paul M. Antoine
 * Further modifications by David S. Miller and Harald Koerfgen
 * Copyright (C) 1999 Silicon Graphics, Inc.
 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
 */
#include <linux/init.h>
#include <linux/threads.h>

#include <asm/addrspace.h>
#include <asm/asm.h>
#include <asm/asmmacro.h>
#include <asm/irqflags.h>
#include <asm/regdef.h>
#include <asm/pgtable-bits.h>
#include <asm/mipsregs.h>
#include <asm/stackframe.h>

#include <kernel-entry-init.h>

	/*
	 * inputs are the text nasid in t1, data nasid in t2.
	 */
	.macro MAPPED_KERNEL_SETUP_TLB
#ifdef CONFIG_MAPPED_KERNEL
	/*
	 * This needs to read the nasid - assume 0 for now.
	 * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,
	 * 0+DVG in tlblo_1.
	 */
	dli	t0, 0xffffffffc0000000
	dmtc0	t0, CP0_ENTRYHI
	li	t0, 0x1c000		# Offset of text into node memory
	dsll	t1, NASID_SHFT		# Shift text nasid into place
	dsll	t2, NASID_SHFT		# Same for data nasid
	or	t1, t1, t0		# Physical load address of kernel text
	or	t2, t2, t0		# Physical load address of kernel data
	dsrl	t1, 12			# 4K pfn
	dsrl	t2, 12			# 4K pfn
	dsll	t1, 6			# Get pfn into place
	dsll	t2, 6			# Get pfn into place
	li	t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6)
	or	t0, t0, t1
	mtc0	t0, CP0_ENTRYLO0	# physaddr, VG, cach exlwr
	li	t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6)
	or	t0, t0, t2
	mtc0	t0, CP0_ENTRYLO1	# physaddr, DVG, cach exlwr
	li	t0, 0x1ffe000		# MAPPED_KERN_TLBMASK, TLBPGMASK_16M
	mtc0	t0, CP0_PAGEMASK
	li	t0, 0			# KMAP_INX
	mtc0	t0, CP0_INDEX
	li	t0, 1
	mtc0	t0, CP0_WIRED
	tlbwi
#else
	mtc0	zero, CP0_WIRED
#endif
	.endm

	/*
	 * For the moment disable interrupts, mark the kernel mode and
	 * set ST0_KX so that the CPU does not spit fire when using
	 * 64-bit addresses.  A full initialization of the CPU's status
	 * register is done later in per_cpu_trap_init().
	 */
	.macro	setup_c0_status set clr
	.set	push
#ifdef CONFIG_MIPS_MT_SMTC
	/*
	 * For SMTC, we need to set privilege and disable interrupts only for
	 * the current TC, using the TCStatus register.
	 */
	mfc0	t0, CP0_TCSTATUS
	/* Fortunately CU 0 is in the same place in both registers */
	/* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
	li	t1, ST0_CU0 | 0x08001c00
	or	t0, t1
	/* Clear TKSU, leave IXMT */
	xori	t0, 0x00001800
	mtc0	t0, CP0_TCSTATUS
	_ehb
	/* We need to leave the global IE bit set, but clear EXL...*/
	mfc0	t0, CP0_STATUS
	or	t0, ST0_CU0 | ST0_EXL | ST0_ERL | \set | \clr
	xor	t0, ST0_EXL | ST0_ERL | \clr
	mtc0	t0, CP0_STATUS
#else
	mfc0	t0, CP0_STATUS
	or	t0, ST0_CU0|\set|0x1f|\clr
	xor	t0, 0x1f|\clr
	mtc0	t0, CP0_STATUS
	.set	noreorder
	sll	zero,3				# ehb
#endif
	.set	pop
	.endm

	.macro	setup_c0_status_pri
#ifdef CONFIG_64BIT
	setup_c0_status ST0_KX 0
#else
	setup_c0_status 0 0
#endif
	.endm

	.macro	setup_c0_status_sec
#ifdef CONFIG_64BIT
	setup_c0_status ST0_KX ST0_BEV
#else
	setup_c0_status 0 ST0_BEV
#endif
	.endm

#ifndef CONFIG_NO_EXCEPT_FILL
	/*
	 * Reserved space for exception handlers.
	 * Necessary for machines which link their kernels at KSEG0.
	 */
	.fill	0x400
#endif

EXPORT(_stext)

#ifdef CONFIG_BOOT_RAW
	/*
	 * Give us a fighting chance of running if execution beings at the
	 * kernel load address.	 This is needed because this platform does
	 * not have a ELF loader yet.
	 */
FEXPORT(__kernel_entry)
	j	kernel_entry
#endif

	__REF

NESTED(kernel_entry, 16, sp)			# kernel entry point

	kernel_entry_setup			# cpu specific setup

	setup_c0_status_pri

	/* We might not get launched at the address the kernel is linked to,
	   so we jump there.  */
	PTR_LA	t0, 0f
	jr	t0
0:

#ifdef CONFIG_MIPS_MT_SMTC
	/*
	 * In SMTC kernel, "CLI" is thread-specific, in TCStatus.
	 * We still need to enable interrupts globally in Status,
	 * and clear EXL/ERL.
	 *
	 * TCContext is used to track interrupt levels under
	 * service in SMTC kernel. Clear for boot TC before
	 * allowing any interrupts.
	 */
	mtc0	zero, CP0_TCCONTEXT

	mfc0	t0, CP0_STATUS
	ori	t0, t0, 0xff1f
	xori	t0, t0, 0x001e
	mtc0	t0, CP0_STATUS
#endif /* CONFIG_MIPS_MT_SMTC */

	PTR_LA		t0, __bss_start		# clear .bss
	LONG_S		zero, (t0)
	PTR_LA		t1, __bss_stop - LONGSIZE
1:
	PTR_ADDIU	t0, LONGSIZE
	LONG_S		zero, (t0)
	bne		t0, t1, 1b

	LONG_S		a0, fw_arg0		# firmware arguments
	LONG_S		a1, fw_arg1
	LONG_S		a2, fw_arg2
	LONG_S		a3, fw_arg3

	MTC0		zero, CP0_CONTEXT	# clear context register
	PTR_LA		$28, init_thread_union
	/* Set the SP after an empty pt_regs.  */
	PTR_LI		sp, _THREAD_SIZE - 32 - PT_SIZE
	PTR_ADDU	sp, $28
	back_to_back_c0_hazard
	set_saved_sp	sp, t0, t1
	PTR_SUBU	sp, 4 * SZREG		# init stack pointer

	j		start_kernel
	END(kernel_entry)

	__CPUINIT

#ifdef CONFIG_SMP
/*
 * SMP slave cpus entry point.	Board specific code for bootstrap calls this
 * function after setting up the stack and gp registers.
 */
NESTED(smp_bootstrap, 16, sp)
#ifdef CONFIG_MIPS_MT_SMTC
	/*
	 * Read-modify-writes of Status must be atomic, and this
	 * is one case where CLI is invoked without EXL being
	 * necessarily set. The CLI and setup_c0_status will
	 * in fact be redundant for all but the first TC of
	 * each VPE being booted.
	 */
	DMT	10	# dmt t2 /* t0, t1 are used by CLI and setup_c0_status() */
	jal	mips_ihb
#endif /* CONFIG_MIPS_MT_SMTC */
	setup_c0_status_sec
	smp_slave_setup
#ifdef CONFIG_MIPS_MT_SMTC
	andi	t2, t2, VPECONTROL_TE
	beqz	t2, 2f
	EMT		# emt
2:
#endif /* CONFIG_MIPS_MT_SMTC */
	j	start_secondary
	END(smp_bootstrap)
#endif /* CONFIG_SMP */

	__FINIT
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994, 1995 Waldorf Electronics
	7	* Written by Ralf Baechle and Andreas Busse
192ef366	8	* Copyright (C) 1994 - 99, 2003, 06 Ralf Baechle
1da177e4 LT	9	* Copyright (C) 1996 Paul M. Antoine
	10	* Modified for DECStation and hence R3000 support by Paul M. Antoine
	11	* Further modifications by David S. Miller and Harald Koerfgen
	12	* Copyright (C) 1999 Silicon Graphics, Inc.
	13	* Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
	14	* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
	15	*/
1da177e4 LT	16	#include <linux/init.h>
	17	#include <linux/threads.h>
	18
9267a30d	19	#include <asm/addrspace.h>
1da177e4	20	#include <asm/asm.h>
41c594ab	21	#include <asm/asmmacro.h>
192ef366	22	#include <asm/irqflags.h>
1da177e4	23	#include <asm/regdef.h>
fd3d2764	24	#include <asm/pgtable-bits.h>
1da177e4 LT	25	#include <asm/mipsregs.h>
1da177e4 LT	26	#include <asm/stackframe.h>
7e35952b RB	27
7e35952b RB	28	#include <kernel-entry-init.h>
1da177e4	29
1da177e4 LT	30	/*
	31	* inputs are the text nasid in t1, data nasid in t2.
	32	*/
	33	.macro MAPPED_KERNEL_SETUP_TLB
	34	#ifdef CONFIG_MAPPED_KERNEL
	35	/*
	36	* This needs to read the nasid - assume 0 for now.
	37	* Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,
	38	* 0+DVG in tlblo_1.
	39	*/
	40	dli t0, 0xffffffffc0000000
	41	dmtc0 t0, CP0_ENTRYHI
	42	li t0, 0x1c000 # Offset of text into node memory
	43	dsll t1, NASID_SHFT # Shift text nasid into place
	44	dsll t2, NASID_SHFT # Same for data nasid
	45	or t1, t1, t0 # Physical load address of kernel text
	46	or t2, t2, t0 # Physical load address of kernel data
	47	dsrl t1, 12 # 4K pfn
	48	dsrl t2, 12 # 4K pfn
	49	dsll t1, 6 # Get pfn into place
	50	dsll t2, 6 # Get pfn into place
	51	li t0, ((_PAGE_GLOBAL\|_PAGE_VALID\| _CACHE_CACHABLE_COW) >> 6)
	52	or t0, t0, t1
	53	mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr
	54	li t0, ((_PAGE_GLOBAL\|_PAGE_VALID\| _PAGE_DIRTY\|_CACHE_CACHABLE_COW) >> 6)
	55	or t0, t0, t2
	56	mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr
	57	li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M
	58	mtc0 t0, CP0_PAGEMASK
	59	li t0, 0 # KMAP_INX
	60	mtc0 t0, CP0_INDEX
	61	li t0, 1
	62	mtc0 t0, CP0_WIRED
	63	tlbwi
	64	#else
	65	mtc0 zero, CP0_WIRED
	66	#endif
	67	.endm
	68
	69	/*
	70	* For the moment disable interrupts, mark the kernel mode and
	71	* set ST0_KX so that the CPU does not spit fire when using
	72	* 64-bit addresses. A full initialization of the CPU's status
	73	* register is done later in per_cpu_trap_init().
	74	*/
	75	.macro setup_c0_status set clr
	76	.set push
41c594ab RB	77	#ifdef CONFIG_MIPS_MT_SMTC
	78	/*
	79	* For SMTC, we need to set privilege and disable interrupts only for
	80	* the current TC, using the TCStatus register.
	81	*/
	82	mfc0 t0, CP0_TCSTATUS
	83	/* Fortunately CU 0 is in the same place in both registers */
	84	/* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
	85	li t1, ST0_CU0 \| 0x08001c00
	86	or t0, t1
	87	/* Clear TKSU, leave IXMT */
	88	xori t0, 0x00001800
	89	mtc0 t0, CP0_TCSTATUS
4277ff5e	90	_ehb
41c594ab RB	91	/* We need to leave the global IE bit set, but clear EXL...*/
	92	mfc0 t0, CP0_STATUS
	93	or t0, ST0_CU0 \| ST0_EXL \| ST0_ERL \| \set \| \clr
	94	xor t0, ST0_EXL \| ST0_ERL \| \clr
	95	mtc0 t0, CP0_STATUS
	96	#else
1da177e4 LT	97	mfc0 t0, CP0_STATUS
	98	or t0, ST0_CU0\|\set\|0x1f\|\clr
	99	xor t0, 0x1f\|\clr
	100	mtc0 t0, CP0_STATUS
	101	.set noreorder
	102	sll zero,3 # ehb
41c594ab	103	#endif
1da177e4 LT	104	.set pop
	105	.endm
	106
	107	.macro setup_c0_status_pri
875d43e7	108	#ifdef CONFIG_64BIT
1da177e4 LT	109	setup_c0_status ST0_KX 0
	110	#else
	111	setup_c0_status 0 0
	112	#endif
	113	.endm
	114
	115	.macro setup_c0_status_sec
875d43e7	116	#ifdef CONFIG_64BIT
1da177e4 LT	117	setup_c0_status ST0_KX ST0_BEV
	118	#else
	119	setup_c0_status 0 ST0_BEV
	120	#endif
	121	.endm
	122
9267a30d	123	#ifndef CONFIG_NO_EXCEPT_FILL
1da177e4 LT	124	/*
	125	* Reserved space for exception handlers.
	126	* Necessary for machines which link their kernels at KSEG0.
	127	*/
	128	.fill 0x400
9267a30d	129	#endif
1da177e4	130
1da177e4 LT	131	EXPORT(_stext)
1da177e4 LT	132
396a2ae0	133	#ifdef CONFIG_BOOT_RAW
b490ff42 RB	134	/*
b490ff42 RB	135	* Give us a fighting chance of running if execution beings at the
70342287	136	* kernel load address. This is needed because this platform does
b490ff42 RB	137	* not have a ELF loader yet.
b490ff42 RB	138	*/
ba820c5c RB	139	FEXPORT(__kernel_entry)
ba820c5c RB	140	j kernel_entry
f6e2373a	141	#endif
1da177e4	142
a055917e	143	__REF
396a2ae0	144
1da177e4	145	NESTED(kernel_entry, 16, sp) # kernel entry point
1da177e4	146
7e35952b RB	147	kernel_entry_setup # cpu specific setup
	148
	149	setup_c0_status_pri
1da177e4	150
15ad838d TB	151	/* We might not get launched at the address the kernel is linked to,
	152	so we jump there. */
	153	PTR_LA t0, 0f
	154	jr t0
	155	0:
1da177e4	156
41c594ab RB	157	#ifdef CONFIG_MIPS_MT_SMTC
	158	/*
	159	* In SMTC kernel, "CLI" is thread-specific, in TCStatus.
	160	* We still need to enable interrupts globally in Status,
	161	* and clear EXL/ERL.
	162	*
	163	* TCContext is used to track interrupt levels under
	164	* service in SMTC kernel. Clear for boot TC before
	165	* allowing any interrupts.
	166	*/
	167	mtc0 zero, CP0_TCCONTEXT
	168
	169	mfc0 t0, CP0_STATUS
	170	ori t0, t0, 0xff1f
	171	xori t0, t0, 0x001e
	172	mtc0 t0, CP0_STATUS
	173	#endif /* CONFIG_MIPS_MT_SMTC */
	174
1da177e4 LT	175	PTR_LA t0, __bss_start # clear .bss
	176	LONG_S zero, (t0)
	177	PTR_LA t1, __bss_stop - LONGSIZE
	178	1:
	179	PTR_ADDIU t0, LONGSIZE
	180	LONG_S zero, (t0)
	181	bne t0, t1, 1b
	182
	183	LONG_S a0, fw_arg0 # firmware arguments
	184	LONG_S a1, fw_arg1
	185	LONG_S a2, fw_arg2
	186	LONG_S a3, fw_arg3
	187
1b3a6e97	188	MTC0 zero, CP0_CONTEXT # clear context register
1da177e4	189	PTR_LA $28, init_thread_union
484889fc DD	190	/* Set the SP after an empty pt_regs. */
484889fc DD	191	PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE
242954b5	192	PTR_ADDU sp, $28
c2ea1d56	193	back_to_back_c0_hazard
1da177e4 LT	194	set_saved_sp sp, t0, t1
	195	PTR_SUBU sp, 4 * SZREG # init stack pointer
	196
	197	j start_kernel
	198	END(kernel_entry)
	199
234fcd14	200	__CPUINIT
b490ff42	201
1da177e4 LT	202	#ifdef CONFIG_SMP
1da177e4 LT	203	/*
70342287	204	* SMP slave cpus entry point. Board specific code for bootstrap calls this
1da177e4 LT	205	* function after setting up the stack and gp registers.
	206	*/
	207	NESTED(smp_bootstrap, 16, sp)
41c594ab RB	208	#ifdef CONFIG_MIPS_MT_SMTC
	209	/*
	210	* Read-modify-writes of Status must be atomic, and this
	211	* is one case where CLI is invoked without EXL being
	212	* necessarily set. The CLI and setup_c0_status will
	213	* in fact be redundant for all but the first TC of
	214	* each VPE being booted.
	215	*/
	216	DMT 10 # dmt t2 /* t0, t1 are used by CLI and setup_c0_status() */
	217	jal mips_ihb
	218	#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4	219	setup_c0_status_sec
7e35952b	220	smp_slave_setup
41c594ab RB	221	#ifdef CONFIG_MIPS_MT_SMTC
	222	andi t2, t2, VPECONTROL_TE
	223	beqz t2, 2f
	224	EMT # emt
	225	2:
	226	#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4 LT	227	j start_secondary
	228	END(smp_bootstrap)
	229	#endif /* CONFIG_SMP */
	230
	231	__FINIT