[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / kernel / cevt-txx9.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Based on linux/arch/mips/kernel/cevt-r4k.c,
 *	    linux/arch/mips/jmr3927/rbhma3100/setup.c
 *
 * Copyright 2001 MontaVista Software Inc.
 * Copyright (C) 2000-2001 Toshiba Corporation
 * Copyright (C) 2007 MIPS Technologies, Inc.
 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
 */
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/time.h>
#include <asm/txx9tmr.h>

#define TCR_BASE (TXx9_TMTCR_CCDE | TXx9_TMTCR_CRE | TXx9_TMTCR_TMODE_ITVL)
#define TIMER_CCD	0	/* 1/2 */
#define TIMER_CLK(imclk)	((imclk) / (2 << TIMER_CCD))

struct txx9_clocksource {
	struct clocksource cs;
	struct txx9_tmr_reg __iomem *tmrptr;
};

static cycle_t txx9_cs_read(struct clocksource *cs)
{
	struct txx9_clocksource *txx9_cs =
		container_of(cs, struct txx9_clocksource, cs);
	return __raw_readl(&txx9_cs->tmrptr->trr);
}

/* Use 1 bit smaller width to use full bits in that width */
#define TXX9_CLOCKSOURCE_BITS (TXX9_TIMER_BITS - 1)

static struct txx9_clocksource txx9_clocksource = {
	.cs = {
		.name		= "TXx9",
		.rating		= 200,
		.read		= txx9_cs_read,
		.mask		= CLOCKSOURCE_MASK(TXX9_CLOCKSOURCE_BITS),
		.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
	},
};

void __init txx9_clocksource_init(unsigned long baseaddr,
				  unsigned int imbusclk)
{
	struct txx9_tmr_reg __iomem *tmrptr;

	clocksource_register_hz(&txx9_clocksource.cs, TIMER_CLK(imbusclk));

	tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
	__raw_writel(TCR_BASE, &tmrptr->tcr);
	__raw_writel(0, &tmrptr->tisr);
	__raw_writel(TIMER_CCD, &tmrptr->ccdr);
	__raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr);
	__raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra);
	__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
	txx9_clocksource.tmrptr = tmrptr;
}

struct txx9_clock_event_device {
	struct clock_event_device cd;
	struct txx9_tmr_reg __iomem *tmrptr;
};

static void txx9tmr_stop_and_clear(struct txx9_tmr_reg __iomem *tmrptr)
{
	/* stop and reset counter */
	__raw_writel(TCR_BASE, &tmrptr->tcr);
	/* clear pending interrupt */
	__raw_writel(0, &tmrptr->tisr);
}

static void txx9tmr_set_mode(enum clock_event_mode mode,
			     struct clock_event_device *evt)
{
	struct txx9_clock_event_device *txx9_cd =
		container_of(evt, struct txx9_clock_event_device, cd);
	struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;

	txx9tmr_stop_and_clear(tmrptr);
	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		__raw_writel(TXx9_TMITMR_TIIE | TXx9_TMITMR_TZCE,
			     &tmrptr->itmr);
		/* start timer */
		__raw_writel(((u64)(NSEC_PER_SEC / HZ) * evt->mult) >>
			     evt->shift,
			     &tmrptr->cpra);
		__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:
		__raw_writel(0, &tmrptr->itmr);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		__raw_writel(TXx9_TMITMR_TIIE, &tmrptr->itmr);
		break;
	case CLOCK_EVT_MODE_RESUME:
		__raw_writel(TIMER_CCD, &tmrptr->ccdr);
		__raw_writel(0, &tmrptr->itmr);
		break;
	}
}

static int txx9tmr_set_next_event(unsigned long delta,
				  struct clock_event_device *evt)
{
	struct txx9_clock_event_device *txx9_cd =
		container_of(evt, struct txx9_clock_event_device, cd);
	struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;

	txx9tmr_stop_and_clear(tmrptr);
	/* start timer */
	__raw_writel(delta, &tmrptr->cpra);
	__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
	return 0;
}

static struct txx9_clock_event_device txx9_clock_event_device = {
	.cd = {
		.name		= "TXx9",
		.features	= CLOCK_EVT_FEAT_PERIODIC |
				  CLOCK_EVT_FEAT_ONESHOT,
		.rating		= 200,
		.set_mode	= txx9tmr_set_mode,
		.set_next_event = txx9tmr_set_next_event,
	},
};

static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id)
{
	struct txx9_clock_event_device *txx9_cd = dev_id;
	struct clock_event_device *cd = &txx9_cd->cd;
	struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;

	__raw_writel(0, &tmrptr->tisr); /* ack interrupt */
	cd->event_handler(cd);
	return IRQ_HANDLED;
}

static struct irqaction txx9tmr_irq = {
	.handler	= txx9tmr_interrupt,
	.flags		= IRQF_PERCPU | IRQF_TIMER,
	.name		= "txx9tmr",
	.dev_id		= &txx9_clock_event_device,
};

void __init txx9_clockevent_init(unsigned long baseaddr, int irq,
				 unsigned int imbusclk)
{
	struct clock_event_device *cd = &txx9_clock_event_device.cd;
	struct txx9_tmr_reg __iomem *tmrptr;

	tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
	txx9tmr_stop_and_clear(tmrptr);
	__raw_writel(TIMER_CCD, &tmrptr->ccdr);
	__raw_writel(0, &tmrptr->itmr);
	txx9_clock_event_device.tmrptr = tmrptr;

	clockevent_set_clock(cd, TIMER_CLK(imbusclk));
	cd->max_delta_ns =
		clockevent_delta2ns(0xffffffff >> (32 - TXX9_TIMER_BITS), cd);
	cd->min_delta_ns = clockevent_delta2ns(0xf, cd);
	cd->irq = irq;
	cd->cpumask = cpumask_of(0),
	clockevents_register_device(cd);
	setup_irq(irq, &txx9tmr_irq);
	printk(KERN_INFO "TXx9: clockevent device at 0x%lx, irq %d\n",
	       baseaddr, irq);
}

void __init txx9_tmr_init(unsigned long baseaddr)
{
	struct txx9_tmr_reg __iomem *tmrptr;

	tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
	/* Start once to make CounterResetEnable effective */
	__raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr);
	/* Stop and reset the counter */
	__raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr);
	__raw_writel(0, &tmrptr->tisr);
	__raw_writel(0xffffffff, &tmrptr->cpra);
	__raw_writel(0, &tmrptr->itmr);
	__raw_writel(0, &tmrptr->ccdr);
	__raw_writel(0, &tmrptr->pgmr);
	iounmap(tmrptr);
}
Commit	Line	Data
229f773e AN	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Based on linux/arch/mips/kernel/cevt-r4k.c,
70342287	7	* linux/arch/mips/jmr3927/rbhma3100/setup.c
229f773e AN	8	*
	9	* Copyright 2001 MontaVista Software Inc.
	10	* Copyright (C) 2000-2001 Toshiba Corporation
	11	* Copyright (C) 2007 MIPS Technologies, Inc.
	12	* Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
	13	*/
	14	#include <linux/init.h>
	15	#include <linux/interrupt.h>
ca4d3e67	16	#include <linux/irq.h>
229f773e AN	17	#include <asm/time.h>
	18	#include <asm/txx9tmr.h>
	19
	20	#define TCR_BASE (TXx9_TMTCR_CCDE \| TXx9_TMTCR_CRE \| TXx9_TMTCR_TMODE_ITVL)
	21	#define TIMER_CCD 0 /* 1/2 */
	22	#define TIMER_CLK(imclk) ((imclk) / (2 << TIMER_CCD))
	23
a43da03c AN	24	struct txx9_clocksource {
	25	struct clocksource cs;
	26	struct txx9_tmr_reg __iomem *tmrptr;
	27	};
229f773e	28
8e19608e	29	static cycle_t txx9_cs_read(struct clocksource *cs)
229f773e	30	{
a43da03c AN	31	struct txx9_clocksource *txx9_cs =
	32	container_of(cs, struct txx9_clocksource, cs);
	33	return __raw_readl(&txx9_cs->tmrptr->trr);
229f773e AN	34	}
	35
	36	/* Use 1 bit smaller width to use full bits in that width */
	37	#define TXX9_CLOCKSOURCE_BITS (TXX9_TIMER_BITS - 1)
	38
a43da03c AN	39	static struct txx9_clocksource txx9_clocksource = {
	40	.cs = {
	41	.name = "TXx9",
	42	.rating = 200,
	43	.read = txx9_cs_read,
	44	.mask = CLOCKSOURCE_MASK(TXX9_CLOCKSOURCE_BITS),
	45	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	46	},
229f773e AN	47	};
	48
	49	void __init txx9_clocksource_init(unsigned long baseaddr,
	50	unsigned int imbusclk)
	51	{
	52	struct txx9_tmr_reg __iomem *tmrptr;
	53
75c4fd8c	54	clocksource_register_hz(&txx9_clocksource.cs, TIMER_CLK(imbusclk));
229f773e AN	55
	56	tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
	57	__raw_writel(TCR_BASE, &tmrptr->tcr);
	58	__raw_writel(0, &tmrptr->tisr);
	59	__raw_writel(TIMER_CCD, &tmrptr->ccdr);
	60	__raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr);
	61	__raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra);
	62	__raw_writel(TCR_BASE \| TXx9_TMTCR_TCE, &tmrptr->tcr);
a43da03c	63	txx9_clocksource.tmrptr = tmrptr;
229f773e AN	64	}
229f773e AN	65
a43da03c AN	66	struct txx9_clock_event_device {
	67	struct clock_event_device cd;
	68	struct txx9_tmr_reg __iomem *tmrptr;
	69	};
229f773e AN	70
	71	static void txx9tmr_stop_and_clear(struct txx9_tmr_reg __iomem *tmrptr)
	72	{
	73	/* stop and reset counter */
	74	__raw_writel(TCR_BASE, &tmrptr->tcr);
	75	/* clear pending interrupt */
	76	__raw_writel(0, &tmrptr->tisr);
	77	}
	78
	79	static void txx9tmr_set_mode(enum clock_event_mode mode,
	80	struct clock_event_device *evt)
	81	{
a43da03c AN	82	struct txx9_clock_event_device *txx9_cd =
	83	container_of(evt, struct txx9_clock_event_device, cd);
	84	struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
229f773e AN	85
	86	txx9tmr_stop_and_clear(tmrptr);
	87	switch (mode) {
	88	case CLOCK_EVT_MODE_PERIODIC:
	89	__raw_writel(TXx9_TMITMR_TIIE \| TXx9_TMITMR_TZCE,
	90	&tmrptr->itmr);
	91	/* start timer */
	92	__raw_writel(((u64)(NSEC_PER_SEC / HZ) * evt->mult) >>
	93	evt->shift,
	94	&tmrptr->cpra);
	95	__raw_writel(TCR_BASE \| TXx9_TMTCR_TCE, &tmrptr->tcr);
	96	break;
	97	case CLOCK_EVT_MODE_SHUTDOWN:
	98	case CLOCK_EVT_MODE_UNUSED:
	99	__raw_writel(0, &tmrptr->itmr);
	100	break;
	101	case CLOCK_EVT_MODE_ONESHOT:
	102	__raw_writel(TXx9_TMITMR_TIIE, &tmrptr->itmr);
	103	break;
	104	case CLOCK_EVT_MODE_RESUME:
	105	__raw_writel(TIMER_CCD, &tmrptr->ccdr);
	106	__raw_writel(0, &tmrptr->itmr);
	107	break;
	108	}
	109	}
	110
	111	static int txx9tmr_set_next_event(unsigned long delta,
	112	struct clock_event_device *evt)
	113	{
a43da03c AN	114	struct txx9_clock_event_device *txx9_cd =
	115	container_of(evt, struct txx9_clock_event_device, cd);
	116	struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
229f773e AN	117
	118	txx9tmr_stop_and_clear(tmrptr);
	119	/* start timer */
	120	__raw_writel(delta, &tmrptr->cpra);
	121	__raw_writel(TCR_BASE \| TXx9_TMTCR_TCE, &tmrptr->tcr);
	122	return 0;
	123	}
	124
a43da03c AN	125	static struct txx9_clock_event_device txx9_clock_event_device = {
	126	.cd = {
	127	.name = "TXx9",
	128	.features = CLOCK_EVT_FEAT_PERIODIC \|
	129	CLOCK_EVT_FEAT_ONESHOT,
	130	.rating = 200,
	131	.set_mode = txx9tmr_set_mode,
70342287	132	.set_next_event = txx9tmr_set_next_event,
a43da03c	133	},
229f773e AN	134	};
	135
	136	static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id)
	137	{
a43da03c AN	138	struct txx9_clock_event_device *txx9_cd = dev_id;
	139	struct clock_event_device *cd = &txx9_cd->cd;
	140	struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
229f773e	141
70342287	142	__raw_writel(0, &tmrptr->tisr); /* ack interrupt */
229f773e AN	143	cd->event_handler(cd);
	144	return IRQ_HANDLED;
	145	}
	146
	147	static struct irqaction txx9tmr_irq = {
	148	.handler = txx9tmr_interrupt,
8b5690f8	149	.flags = IRQF_PERCPU \| IRQF_TIMER,
229f773e	150	.name = "txx9tmr",
a43da03c	151	.dev_id = &txx9_clock_event_device,
229f773e AN	152	};
	153
	154	void __init txx9_clockevent_init(unsigned long baseaddr, int irq,
	155	unsigned int imbusclk)
	156	{
a43da03c	157	struct clock_event_device *cd = &txx9_clock_event_device.cd;
229f773e AN	158	struct txx9_tmr_reg __iomem *tmrptr;
	159
	160	tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
	161	txx9tmr_stop_and_clear(tmrptr);
	162	__raw_writel(TIMER_CCD, &tmrptr->ccdr);
	163	__raw_writel(0, &tmrptr->itmr);
a43da03c	164	txx9_clock_event_device.tmrptr = tmrptr;
229f773e AN	165
	166	clockevent_set_clock(cd, TIMER_CLK(imbusclk));
	167	cd->max_delta_ns =
	168	clockevent_delta2ns(0xffffffff >> (32 - TXX9_TIMER_BITS), cd);
	169	cd->min_delta_ns = clockevent_delta2ns(0xf, cd);
	170	cd->irq = irq;
320ab2b0	171	cd->cpumask = cpumask_of(0),
229f773e AN	172	clockevents_register_device(cd);
	173	setup_irq(irq, &txx9tmr_irq);
	174	printk(KERN_INFO "TXx9: clockevent device at 0x%lx, irq %d\n",
	175	baseaddr, irq);
	176	}
	177
	178	void __init txx9_tmr_init(unsigned long baseaddr)
	179	{
	180	struct txx9_tmr_reg __iomem *tmrptr;
	181
	182	tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
8986d2f5 AN	183	/* Start once to make CounterResetEnable effective */
	184	__raw_writel(TXx9_TMTCR_CRE \| TXx9_TMTCR_TCE, &tmrptr->tcr);
	185	/* Stop and reset the counter */
229f773e AN	186	__raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr);
	187	__raw_writel(0, &tmrptr->tisr);
	188	__raw_writel(0xffffffff, &tmrptr->cpra);
	189	__raw_writel(0, &tmrptr->itmr);
	190	__raw_writel(0, &tmrptr->ccdr);
	191	__raw_writel(0, &tmrptr->pgmr);
	192	iounmap(tmrptr);
	193	}