[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / include / asm / mach-ip32 / war.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
 */
#ifndef __ASM_MIPS_MACH_IP32_WAR_H
#define __ASM_MIPS_MACH_IP32_WAR_H

#define R4600_V1_INDEX_ICACHEOP_WAR	0
#define R4600_V1_HIT_CACHEOP_WAR	0
#define R4600_V2_HIT_CACHEOP_WAR	0
#define R5432_CP0_INTERRUPT_WAR		0
#define BCM1250_M3_WAR			0
#define SIBYTE_1956_WAR			0
#define MIPS4K_ICACHE_REFILL_WAR	0
#define MIPS_CACHE_SYNC_WAR		0
#define TX49XX_ICACHE_INDEX_INV_WAR	0
#define ICACHE_REFILLS_WORKAROUND_WAR	1
#define R10000_LLSC_WAR			0
#define MIPS34K_MISSED_ITLB_WAR		0

#endif /* __ASM_MIPS_MACH_IP32_WAR_H */
Commit	Line	Data
baf22c1e RB	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
	7	*/
	8	#ifndef __ASM_MIPS_MACH_IP32_WAR_H
	9	#define __ASM_MIPS_MACH_IP32_WAR_H
	10
	11	#define R4600_V1_INDEX_ICACHEOP_WAR 0
	12	#define R4600_V1_HIT_CACHEOP_WAR 0
	13	#define R4600_V2_HIT_CACHEOP_WAR 0
	14	#define R5432_CP0_INTERRUPT_WAR 0
	15	#define BCM1250_M3_WAR 0
	16	#define SIBYTE_1956_WAR 0
	17	#define MIPS4K_ICACHE_REFILL_WAR 0
	18	#define MIPS_CACHE_SYNC_WAR 0
	19	#define TX49XX_ICACHE_INDEX_INV_WAR 0
70342287	20	#define ICACHE_REFILLS_WORKAROUND_WAR 1
baf22c1e RB	21	#define R10000_LLSC_WAR 0
	22	#define MIPS34K_MISSED_ITLB_WAR 0
	23
	24	#endif /* __ASM_MIPS_MACH_IP32_WAR_H */