[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / m68k / platform / coldfire / sltimers.c

/***************************************************************************/

/*
 *	sltimers.c -- generic ColdFire slice timer support.
 *
 *	Copyright (C) 2009-2010, Philippe De Muyter <phdm@macqel.be>
 *	based on
 *	timers.c -- generic ColdFire hardware timer support.
 *	Copyright (C) 1999-2008, Greg Ungerer <gerg@snapgear.com>
 */

/***************************************************************************/

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/profile.h>
#include <linux/clocksource.h>
#include <asm/io.h>
#include <asm/traps.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfslt.h>
#include <asm/mcfsim.h>

/***************************************************************************/

#ifdef CONFIG_HIGHPROFILE

/*
 *	By default use Slice Timer 1 as the profiler clock timer.
 */
#define	PA(a)	(MCF_MBAR + MCFSLT_TIMER1 + (a))

/*
 *	Choose a reasonably fast profile timer. Make it an odd value to
 *	try and get good coverage of kernel operations.
 */
#define	PROFILEHZ	1013

irqreturn_t mcfslt_profile_tick(int irq, void *dummy)
{
	/* Reset Slice Timer 1 */
	__raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, PA(MCFSLT_SSR));
	if (current->pid)
		profile_tick(CPU_PROFILING);
	return IRQ_HANDLED;
}

static struct irqaction mcfslt_profile_irq = {
	.name	 = "profile timer",
	.flags	 = IRQF_DISABLED | IRQF_TIMER,
	.handler = mcfslt_profile_tick,
};

void mcfslt_profile_init(void)
{
	printk(KERN_INFO "PROFILE: lodging TIMER 1 @ %dHz as profile timer\n",
	       PROFILEHZ);

	setup_irq(MCF_IRQ_PROFILER, &mcfslt_profile_irq);

	/* Set up TIMER 2 as high speed profile clock */
	__raw_writel(MCF_BUSCLK / PROFILEHZ - 1, PA(MCFSLT_STCNT));
	__raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
								PA(MCFSLT_SCR));

}

#endif	/* CONFIG_HIGHPROFILE */

/***************************************************************************/

/*
 *	By default use Slice Timer 0 as the system clock timer.
 */
#define	TA(a)	(MCF_MBAR + MCFSLT_TIMER0 + (a))

static u32 mcfslt_cycles_per_jiffy;
static u32 mcfslt_cnt;

static irqreturn_t mcfslt_tick(int irq, void *dummy)
{
	/* Reset Slice Timer 0 */
	__raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR));
	mcfslt_cnt += mcfslt_cycles_per_jiffy;
	return arch_timer_interrupt(irq, dummy);
}

static struct irqaction mcfslt_timer_irq = {
	.name	 = "timer",
	.flags	 = IRQF_DISABLED | IRQF_TIMER,
	.handler = mcfslt_tick,
};

static cycle_t mcfslt_read_clk(struct clocksource *cs)
{
	unsigned long flags;
	u32 cycles;
	u16 scnt;

	local_irq_save(flags);
	scnt = __raw_readl(TA(MCFSLT_SCNT));
	cycles = mcfslt_cnt;
	local_irq_restore(flags);

	/* subtract because slice timers count down */
	return cycles - scnt;
}

static struct clocksource mcfslt_clk = {
	.name	= "slt",
	.rating	= 250,
	.read	= mcfslt_read_clk,
	.shift	= 20,
	.mask	= CLOCKSOURCE_MASK(32),
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

void hw_timer_init(void)
{
	mcfslt_cycles_per_jiffy = MCF_BUSCLK / HZ;
	/*
	 *	The coldfire slice timer (SLT) runs from STCNT to 0 included,
	 *	then STCNT again and so on.  It counts thus actually
	 *	STCNT + 1 steps for 1 tick, not STCNT.  So if you want
	 *	n cycles, initialize STCNT with n - 1.
	 */
	__raw_writel(mcfslt_cycles_per_jiffy - 1, TA(MCFSLT_STCNT));
	__raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
								TA(MCFSLT_SCR));
	/* initialize mcfslt_cnt knowing that slice timers count down */
	mcfslt_cnt = mcfslt_cycles_per_jiffy;

	setup_irq(MCF_IRQ_TIMER, &mcfslt_timer_irq);

	mcfslt_clk.mult = clocksource_hz2mult(MCF_BUSCLK, mcfslt_clk.shift);
	clocksource_register(&mcfslt_clk);

#ifdef CONFIG_HIGHPROFILE
	mcfslt_profile_init();
#endif
}
Commit	Line	Data
ea49f8ff PDM	1	/***************************************************************************/
	2
	3	/*
	4	* sltimers.c -- generic ColdFire slice timer support.
	5	*
	6	* Copyright (C) 2009-2010, Philippe De Muyter <phdm@macqel.be>
	7	* based on
	8	* timers.c -- generic ColdFire hardware timer support.
	9	* Copyright (C) 1999-2008, Greg Ungerer <gerg@snapgear.com>
	10	*/
	11
	12	/***************************************************************************/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/sched.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/irq.h>
	19	#include <linux/profile.h>
	20	#include <linux/clocksource.h>
	21	#include <asm/io.h>
	22	#include <asm/traps.h>
	23	#include <asm/machdep.h>
	24	#include <asm/coldfire.h>
	25	#include <asm/mcfslt.h>
	26	#include <asm/mcfsim.h>
	27
	28	/***************************************************************************/
	29
	30	#ifdef CONFIG_HIGHPROFILE
	31
	32	/*
	33	* By default use Slice Timer 1 as the profiler clock timer.
	34	*/
	35	#define PA(a) (MCF_MBAR + MCFSLT_TIMER1 + (a))
	36
	37	/*
	38	* Choose a reasonably fast profile timer. Make it an odd value to
	39	* try and get good coverage of kernel operations.
	40	*/
	41	#define PROFILEHZ 1013
	42
	43	irqreturn_t mcfslt_profile_tick(int irq, void *dummy)
	44	{
	45	/* Reset Slice Timer 1 */
	46	__raw_writel(MCFSLT_SSR_BE \| MCFSLT_SSR_TE, PA(MCFSLT_SSR));
	47	if (current->pid)
	48	profile_tick(CPU_PROFILING);
	49	return IRQ_HANDLED;
	50	}
	51
	52	static struct irqaction mcfslt_profile_irq = {
	53	.name = "profile timer",
	54	.flags = IRQF_DISABLED \| IRQF_TIMER,
	55	.handler = mcfslt_profile_tick,
	56	};
	57
	58	void mcfslt_profile_init(void)
	59	{
	60	printk(KERN_INFO "PROFILE: lodging TIMER 1 @ %dHz as profile timer\n",
	61	PROFILEHZ);
	62
	63	setup_irq(MCF_IRQ_PROFILER, &mcfslt_profile_irq);
	64
65	/* Set up TIMER 2 as high speed profile clock */
66	__raw_writel(MCF_BUSCLK / PROFILEHZ - 1, PA(MCFSLT_STCNT));
67	__raw_writel(MCFSLT_SCR_RUN \| MCFSLT_SCR_IEN \| MCFSLT_SCR_TEN,
68	PA(MCFSLT_SCR));
69
70	}
71
72	#endif /* CONFIG_HIGHPROFILE */
73
74	/***************************************************************************/
75
76	/*
77	* By default use Slice Timer 0 as the system clock timer.
78	*/
79	#define TA(a) (MCF_MBAR + MCFSLT_TIMER0 + (a))
80
81	static u32 mcfslt_cycles_per_jiffy;
82	static u32 mcfslt_cnt;
83
84	static irqreturn_t mcfslt_tick(int irq, void *dummy)
85	{
86	/* Reset Slice Timer 0 */
87	__raw_writel(MCFSLT_SSR_BE \| MCFSLT_SSR_TE, TA(MCFSLT_SSR));
88	mcfslt_cnt += mcfslt_cycles_per_jiffy;
89	return arch_timer_interrupt(irq, dummy);
90	}
91
92	static struct irqaction mcfslt_timer_irq = {
93	.name = "timer",
94	.flags = IRQF_DISABLED \| IRQF_TIMER,
95	.handler = mcfslt_tick,
96	};
97
98	static cycle_t mcfslt_read_clk(struct clocksource *cs)
99	{
100	unsigned long flags;
101	u32 cycles;
102	u16 scnt;
103
104	local_irq_save(flags);
105	scnt = __raw_readl(TA(MCFSLT_SCNT));
106	cycles = mcfslt_cnt;
107	local_irq_restore(flags);
108
25985edc	109	/* subtract because slice timers count down */
ea49f8ff PDM	110	return cycles - scnt;
	111	}
	112
	113	static struct clocksource mcfslt_clk = {
	114	.name = "slt",
	115	.rating = 250,
	116	.read = mcfslt_read_clk,
	117	.shift = 20,
	118	.mask = CLOCKSOURCE_MASK(32),
	119	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	120	};
	121
	122	void hw_timer_init(void)
	123	{
	124	mcfslt_cycles_per_jiffy = MCF_BUSCLK / HZ;
	125	/*
	126	* The coldfire slice timer (SLT) runs from STCNT to 0 included,
	127	* then STCNT again and so on. It counts thus actually
	128	* STCNT + 1 steps for 1 tick, not STCNT. So if you want
	129	* n cycles, initialize STCNT with n - 1.
	130	*/
	131	__raw_writel(mcfslt_cycles_per_jiffy - 1, TA(MCFSLT_STCNT));
	132	__raw_writel(MCFSLT_SCR_RUN \| MCFSLT_SCR_IEN \| MCFSLT_SCR_TEN,
	133	TA(MCFSLT_SCR));
	134	/* initialize mcfslt_cnt knowing that slice timers count down */
	135	mcfslt_cnt = mcfslt_cycles_per_jiffy;
	136
	137	setup_irq(MCF_IRQ_TIMER, &mcfslt_timer_irq);
	138
	139	mcfslt_clk.mult = clocksource_hz2mult(MCF_BUSCLK, mcfslt_clk.shift);
	140	clocksource_register(&mcfslt_clk);
	141
	142	#ifdef CONFIG_HIGHPROFILE
	143	mcfslt_profile_init();
	144	#endif
	145	}