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1 | /****************************************************************************/ |
2 | ||
3 | /* | |
4 | * m5307sim.h -- ColdFire 5307 System Integration Module support. | |
5 | * | |
6 | * (C) Copyright 1999, Moreton Bay Ventures Pty Ltd. | |
7 | * (C) Copyright 1999, Lineo (www.lineo.com) | |
8 | * | |
9 | * Modified by David W. Miller for the MCF5307 Eval Board. | |
10 | */ | |
11 | ||
12 | /****************************************************************************/ | |
13 | #ifndef m5307sim_h | |
14 | #define m5307sim_h | |
15 | /****************************************************************************/ | |
16 | ||
17 | /* | |
18 | * Define the 5307 SIM register set addresses. | |
19 | */ | |
20 | #define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ | |
21 | #define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ | |
22 | #define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ | |
23 | #define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ | |
24 | #define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ | |
25 | #define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ | |
26 | #define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/ | |
27 | #define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ | |
28 | #define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ | |
29 | #define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ | |
30 | #define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */ | |
31 | #define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ | |
32 | #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ | |
33 | #define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ | |
34 | #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ | |
35 | #define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ | |
36 | #define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ | |
37 | #define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ | |
38 | #define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ | |
39 | #define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ | |
40 | #define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ | |
41 | #define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ | |
42 | #define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ | |
43 | ||
44 | #define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ | |
45 | #define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ | |
46 | #define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ | |
47 | #define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ | |
48 | #define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ | |
49 | #define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ | |
50 | ||
51 | #ifdef CONFIG_OLDMASK | |
52 | #define MCFSIM_CSBAR 0x98 /* CS Base Address reg (r/w) */ | |
53 | #define MCFSIM_CSBAMR 0x9c /* CS Base Mask reg (r/w) */ | |
54 | #define MCFSIM_CSMR2 0x9e /* CS 2 Mask reg (r/w) */ | |
55 | #define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ | |
56 | #define MCFSIM_CSMR3 0xaa /* CS 3 Mask reg (r/w) */ | |
57 | #define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ | |
58 | #define MCFSIM_CSMR4 0xb6 /* CS 4 Mask reg (r/w) */ | |
59 | #define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ | |
60 | #define MCFSIM_CSMR5 0xc2 /* CS 5 Mask reg (r/w) */ | |
61 | #define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ | |
62 | #define MCFSIM_CSMR6 0xce /* CS 6 Mask reg (r/w) */ | |
63 | #define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ | |
64 | #define MCFSIM_CSMR7 0xda /* CS 7 Mask reg (r/w) */ | |
65 | #define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ | |
66 | #else | |
ab690d9f | 67 | #define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ |
1da177e4 LT |
68 | #define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ |
69 | #define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ | |
ab690d9f | 70 | #define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ |
1da177e4 LT |
71 | #define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ |
72 | #define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ | |
ab690d9f | 73 | #define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */ |
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74 | #define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ |
75 | #define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ | |
ab690d9f | 76 | #define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */ |
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77 | #define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */ |
78 | #define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ | |
ab690d9f | 79 | #define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */ |
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80 | #define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */ |
81 | #define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ | |
ab690d9f | 82 | #define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */ |
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83 | #define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ |
84 | #define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ | |
85 | #endif /* CONFIG_OLDMASK */ | |
86 | ||
87 | #define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ | |
88 | #define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ | |
89 | #define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ | |
90 | #define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ | |
91 | #define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ | |
92 | ||
f7a20ba0 | 93 | #define MCFSIM_PADDR (MCF_MBAR + 0x244) |
94 | #define MCFSIM_PADAT (MCF_MBAR + 0x248) | |
95 | ||
96 | /* | |
97 | * Generic GPIO support | |
98 | */ | |
99 | #define MCFGPIO_PIN_MAX 16 | |
100 | #define MCFGPIO_IRQ_MAX -1 | |
101 | #define MCFGPIO_IRQ_VECBASE -1 | |
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102 | |
103 | ||
104 | /* Definition offset address for CS2-7 -- old mask 5307 */ | |
105 | ||
106 | #define MCF5307_CS2 (0x400000) | |
107 | #define MCF5307_CS3 (0x600000) | |
108 | #define MCF5307_CS4 (0x800000) | |
109 | #define MCF5307_CS5 (0xA00000) | |
110 | #define MCF5307_CS6 (0xC00000) | |
111 | #define MCF5307_CS7 (0xE00000) | |
112 | ||
113 | ||
114 | /* | |
115 | * Some symbol defines for the above... | |
116 | */ | |
117 | #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ | |
118 | #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ | |
119 | #define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ | |
120 | #define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ | |
121 | #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ | |
122 | #define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ | |
123 | #define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ | |
124 | #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ | |
125 | #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ | |
126 | ||
04b75b10 | 127 | |
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128 | /* |
129 | * Some symbol defines for the Parallel Port Pin Assignment Register | |
130 | */ | |
131 | #define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */ | |
132 | /* Clear to select par I/O */ | |
133 | #define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */ | |
134 | /* Clear to select par I/O */ | |
135 | ||
136 | /* | |
137 | * Defines for the IRQPAR Register | |
138 | */ | |
139 | #define IRQ5_LEVEL4 0x80 | |
140 | #define IRQ3_LEVEL6 0x40 | |
141 | #define IRQ1_LEVEL2 0x20 | |
142 | ||
04b75b10 GU |
143 | /* |
144 | * Define system peripheral IRQ usage. | |
145 | */ | |
146 | #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ | |
147 | #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ | |
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148 | |
149 | /* | |
150 | * Define the Cache register flags. | |
151 | */ | |
152 | #define CACR_EC (1<<31) | |
153 | #define CACR_ESB (1<<29) | |
154 | #define CACR_DPI (1<<28) | |
155 | #define CACR_HLCK (1<<27) | |
156 | #define CACR_CINVA (1<<24) | |
157 | #define CACR_DNFB (1<<10) | |
158 | #define CACR_DCM_WTHRU (0<<8) | |
159 | #define CACR_DCM_WBACK (1<<8) | |
160 | #define CACR_DCM_OFF_PRE (2<<8) | |
161 | #define CACR_DCM_OFF_IMP (3<<8) | |
162 | #define CACR_DW (1<<5) | |
163 | ||
164 | #define ACR_BASE_POS 24 | |
165 | #define ACR_MASK_POS 16 | |
166 | #define ACR_ENABLE (1<<15) | |
167 | #define ACR_USER (0<<13) | |
168 | #define ACR_SUPER (1<<13) | |
169 | #define ACR_ANY (2<<13) | |
170 | #define ACR_CM_WTHRU (0<<5) | |
171 | #define ACR_CM_WBACK (1<<5) | |
172 | #define ACR_CM_OFF_PRE (2<<5) | |
173 | #define ACR_CM_OFF_IMP (3<<5) | |
174 | #define ACR_WPROTECT (1<<2) | |
175 | ||
176 | /****************************************************************************/ | |
177 | #endif /* m5307sim_h */ |