projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /****************************************************************************/ |
| 2 | ||
| 3 | /* | |
| 4 | * m527xsim.h -- ColdFire 5270/5271 System Integration Module support. | |
| 5 | * | |
| 6 | * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com) | |
| 7 | */ | |
| 8 | ||
| 9 | /****************************************************************************/ | |
| 10 | #ifndef m527xsim_h | |
| 11 | #define m527xsim_h | |
| 12 | /****************************************************************************/ | |
| 13 | ||
| 733f31b7 GU |
14 | #define CPU_NAME "COLDFIRE(m527x)" |
| 15 | #define CPU_INSTR_PER_JIFFY 3 | |
| 7fc82b65 | 16 | |
| a12cf0a8 | 17 | #include <asm/m52xxacr.h> |
| 1da177e4 LT |
18 | |
| 19 | /* | |
| 20 | * Define the 5270/5271 SIM register set addresses. | |
| 21 | */ | |
| 254eef74 GU |
22 | #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ |
| 23 | #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */ | |
| 24 | ||
| 1da177e4 LT |
25 | #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ |
| 26 | #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ | |
| 27 | #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ | |
| 28 | #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ | |
| 29 | #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ | |
| 30 | #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ | |
| 31 | #define MCFINTC_IRLR 0x18 /* */ | |
| 32 | #define MCFINTC_IACKL 0x19 /* */ | |
| 33 | #define MCFINTC_ICR0 0x40 /* Base ICR register */ | |
| 34 | ||
| 35 | #define MCFINT_VECBASE 64 /* Vector base number */ | |
| 36 | #define MCFINT_UART0 13 /* Interrupt number for UART0 */ | |
| 37 | #define MCFINT_UART1 14 /* Interrupt number for UART1 */ | |
| 38 | #define MCFINT_UART2 15 /* Interrupt number for UART2 */ | |
| 91d60417 | 39 | #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ |
| 1da177e4 LT |
40 | #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ |
| 41 | ||
| 42 | /* | |
| 43 | * SDRAM configuration registers. | |
| 44 | */ | |
| d871629b | 45 | #ifdef CONFIG_M5271 |
| 1da177e4 LT |
46 | #define MCFSIM_DCR 0x40 /* SDRAM control */ |
| 47 | #define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ | |
| 48 | #define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ | |
| 49 | #define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ | |
| 50 | #define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ | |
| d871629b GU |
51 | #endif |
| 52 | #ifdef CONFIG_M5275 | |
| 1da177e4 LT |
53 | #define MCFSIM_DMR 0x40 /* SDRAM mode */ |
| 54 | #define MCFSIM_DCR 0x44 /* SDRAM control */ | |
| 55 | #define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */ | |
| 56 | #define MCFSIM_DCFG2 0x4c /* SDRAM configuration 2 */ | |
| 57 | #define MCFSIM_DBAR0 0x50 /* SDRAM base address 0 */ | |
| 58 | #define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */ | |
| 59 | #define MCFSIM_DBAR1 0x58 /* SDRAM base address 1 */ | |
| 60 | #define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */ | |
| 61 | #endif | |
| 62 | ||
| 57015421 GU |
63 | /* |
| 64 | * UART module. | |
| 65 | */ | |
| 66 | #define MCFUART_BASE1 0x200 /* Base address of UART1 */ | |
| 67 | #define MCFUART_BASE2 0x240 /* Base address of UART2 */ | |
| 68 | #define MCFUART_BASE3 0x280 /* Base address of UART3 */ | |
| f1554da3 | 69 | |
| 70 | #ifdef CONFIG_M5271 | |
| 71 | #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) | |
| 72 | #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) | |
| 73 | #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) | |
| 74 | #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003) | |
| 75 | #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004) | |
| 76 | #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005) | |
| 77 | #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006) | |
| 78 | #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007) | |
| 79 | #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008) | |
| 80 | #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009) | |
| 81 | #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A) | |
| 82 | #define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B) | |
| 83 | ||
| 84 | #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010) | |
| 85 | #define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011) | |
| 86 | #define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012) | |
| 87 | #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013) | |
| 88 | #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014) | |
| 89 | #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015) | |
| 90 | #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016) | |
| 91 | #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017) | |
| 92 | #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018) | |
| 93 | #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019) | |
| 94 | #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A) | |
| 95 | #define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B) | |
| 96 | ||
| 97 | #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020) | |
| 98 | #define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021) | |
| 99 | #define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022) | |
| 100 | #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023) | |
| 101 | #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024) | |
| 102 | #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025) | |
| 103 | #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026) | |
| 104 | #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027) | |
| 105 | #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028) | |
| 106 | #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029) | |
| 107 | #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A) | |
| 108 | #define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B) | |
| 109 | ||
| 110 | #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030) | |
| 111 | #define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031) | |
| 112 | #define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032) | |
| 113 | #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033) | |
| 114 | #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034) | |
| 115 | #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035) | |
| 116 | #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036) | |
| 117 | #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037) | |
| 118 | #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038) | |
| 119 | #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039) | |
| 120 | #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A) | |
| 121 | #define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B) | |
| 122 | ||
| 123 | /* | |
| 124 | * Generic GPIO support | |
| 125 | */ | |
| 126 | #define MCFGPIO_PODR MCFGPIO_PODR_ADDR | |
| 127 | #define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR | |
| 128 | #define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR | |
| 129 | #define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR | |
| 130 | #define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR | |
| 131 | ||
| 132 | #define MCFGPIO_PIN_MAX 100 | |
| 133 | #define MCFGPIO_IRQ_MAX 8 | |
| 134 | #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE | |
| 91d60417 SK |
135 | |
| 136 | #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) | |
| 137 | #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) | |
| f1554da3 | 138 | #endif |
| 139 | ||
| 140 | #ifdef CONFIG_M5275 | |
| 141 | #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004) | |
| 142 | #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100005) | |
| 143 | #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100008) | |
| 144 | #define MCFGPIO_PODR_FEC0H (MCF_IPSBAR + 0x10000A) | |
| 145 | #define MCFGPIO_PODR_FEC0L (MCF_IPSBAR + 0x10000B) | |
| 146 | #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x10000C) | |
| 147 | #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000D) | |
| 148 | #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x10000E) | |
| 149 | #define MCFGPIO_PODR_TIMERH (MCF_IPSBAR + 0x10000F) | |
| 150 | #define MCFGPIO_PODR_TIMERL (MCF_IPSBAR + 0x100010) | |
| 151 | #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100011) | |
| 152 | #define MCFGPIO_PODR_FEC1H (MCF_IPSBAR + 0x100012) | |
| 153 | #define MCFGPIO_PODR_FEC1L (MCF_IPSBAR + 0x100013) | |
| 154 | #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100014) | |
| 155 | #define MCFGPIO_PODR_IRQ (MCF_IPSBAR + 0x100015) | |
| 156 | #define MCFGPIO_PODR_USBH (MCF_IPSBAR + 0x100016) | |
| 157 | #define MCFGPIO_PODR_USBL (MCF_IPSBAR + 0x100017) | |
| 158 | #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100018) | |
| 159 | ||
| 160 | #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100020) | |
| 161 | #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100021) | |
| 162 | #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100024) | |
| 163 | #define MCFGPIO_PDDR_FEC0H (MCF_IPSBAR + 0x100026) | |
| 164 | #define MCFGPIO_PDDR_FEC0L (MCF_IPSBAR + 0x100027) | |
| 165 | #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100028) | |
| 166 | #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x100029) | |
| 167 | #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x10002A) | |
| 168 | #define MCFGPIO_PDDR_TIMERH (MCF_IPSBAR + 0x10002B) | |
| 169 | #define MCFGPIO_PDDR_TIMERL (MCF_IPSBAR + 0x10002C) | |
| 170 | #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x10002D) | |
| 171 | #define MCFGPIO_PDDR_FEC1H (MCF_IPSBAR + 0x10002E) | |
| 172 | #define MCFGPIO_PDDR_FEC1L (MCF_IPSBAR + 0x10002F) | |
| 173 | #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100030) | |
| 174 | #define MCFGPIO_PDDR_IRQ (MCF_IPSBAR + 0x100031) | |
| 175 | #define MCFGPIO_PDDR_USBH (MCF_IPSBAR + 0x100032) | |
| 176 | #define MCFGPIO_PDDR_USBL (MCF_IPSBAR + 0x100033) | |
| 177 | #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100034) | |
| 178 | ||
| 179 | #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x10003C) | |
| 180 | #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x10003D) | |
| 181 | #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100040) | |
| 182 | #define MCFGPIO_PPDSDR_FEC0H (MCF_IPSBAR + 0x100042) | |
| 183 | #define MCFGPIO_PPDSDR_FEC0L (MCF_IPSBAR + 0x100043) | |
| 184 | #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100044) | |
| 185 | #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x100045) | |
| 186 | #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100046) | |
| 187 | #define MCFGPIO_PPDSDR_TIMERH (MCF_IPSBAR + 0x100047) | |
| 188 | #define MCFGPIO_PPDSDR_TIMERL (MCF_IPSBAR + 0x100048) | |
| 189 | #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100049) | |
| 190 | #define MCFGPIO_PPDSDR_FEC1H (MCF_IPSBAR + 0x10004A) | |
| 191 | #define MCFGPIO_PPDSDR_FEC1L (MCF_IPSBAR + 0x10004B) | |
| 192 | #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x10004C) | |
| 193 | #define MCFGPIO_PPDSDR_IRQ (MCF_IPSBAR + 0x10004D) | |
| 194 | #define MCFGPIO_PPDSDR_USBH (MCF_IPSBAR + 0x10004E) | |
| 195 | #define MCFGPIO_PPDSDR_USBL (MCF_IPSBAR + 0x10004F) | |
| 196 | #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100050) | |
| 197 | ||
| 198 | #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100058) | |
| 199 | #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100059) | |
| 200 | #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x10005C) | |
| 201 | #define MCFGPIO_PCLRR_FEC0H (MCF_IPSBAR + 0x10005E) | |
| 202 | #define MCFGPIO_PCLRR_FEC0L (MCF_IPSBAR + 0x10005F) | |
| 203 | #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100060) | |
| 204 | #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x100061) | |
| 205 | #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100062) | |
| 206 | #define MCFGPIO_PCLRR_TIMERH (MCF_IPSBAR + 0x100063) | |
| 207 | #define MCFGPIO_PCLRR_TIMERL (MCF_IPSBAR + 0x100064) | |
| 208 | #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100065) | |
| 209 | #define MCFGPIO_PCLRR_FEC1H (MCF_IPSBAR + 0x100066) | |
| 210 | #define MCFGPIO_PCLRR_FEC1L (MCF_IPSBAR + 0x100067) | |
| 211 | #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100068) | |
| 212 | #define MCFGPIO_PCLRR_IRQ (MCF_IPSBAR + 0x100069) | |
| 213 | #define MCFGPIO_PCLRR_USBH (MCF_IPSBAR + 0x10006A) | |
| 214 | #define MCFGPIO_PCLRR_USBL (MCF_IPSBAR + 0x10006B) | |
| 215 | #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x10006C) | |
| 216 | ||
| 217 | ||
| 218 | /* | |
| 219 | * Generic GPIO support | |
| 220 | */ | |
| 221 | #define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL | |
| 222 | #define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL | |
| 223 | #define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL | |
| 224 | #define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL | |
| 225 | #define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL | |
| 226 | ||
| 227 | #define MCFGPIO_PIN_MAX 148 | |
| 228 | #define MCFGPIO_IRQ_MAX 8 | |
| 229 | #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE | |
| 91d60417 SK |
230 | |
| 231 | #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E) | |
| f1554da3 | 232 | #endif |
| 233 | ||
| 234 | /* | |
| f317c71a | 235 | * PIT timer base addresses. |
| f1554da3 | 236 | */ |
| f317c71a GU |
237 | #define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000) |
| 238 | #define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000) | |
| 239 | #define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000) | |
| 240 | #define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000) | |
| f1554da3 | 241 | |
| f317c71a GU |
242 | /* |
| 243 | * EPort | |
| 244 | */ | |
| f1554da3 | 245 | #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) |
| 246 | #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) | |
| 247 | #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) | |
| 248 | ||
| d871629b GU |
249 | /* |
| 250 | * GPIO pins setups to enable the UARTs. | |
| 251 | */ | |
| 252 | #ifdef CONFIG_M5271 | |
| 253 | #define MCF_GPIO_PAR_UART 0x100048 /* PAR UART address */ | |
| 254 | #define UART0_ENABLE_MASK 0x000f | |
| 255 | #define UART1_ENABLE_MASK 0x0ff0 | |
| 256 | #define UART2_ENABLE_MASK 0x3000 | |
| 257 | #endif | |
| 258 | #ifdef CONFIG_M5275 | |
| 259 | #define MCF_GPIO_PAR_UART 0x10007c /* PAR UART address */ | |
| 260 | #define UART0_ENABLE_MASK 0x000f | |
| 261 | #define UART1_ENABLE_MASK 0x00f0 | |
| 262 | #define UART2_ENABLE_MASK 0x3f00 | |
| 263 | #endif | |
| 264 | ||
| 4c0b008d GU |
265 | /* |
| 266 | * Reset Controll Unit (relative to IPSBAR). | |
| 267 | */ | |
| 268 | #define MCF_RCR 0x110000 | |
| 269 | #define MCF_RSR 0x110001 | |
| 270 | ||
| 271 | #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ | |
| 272 | #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ | |
| 273 | ||
| 1da177e4 LT |
274 | /****************************************************************************/ |
| 275 | #endif /* m527xsim_h */ |