[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / ia64 / kernel / irq_ia64.c

/*
 * linux/arch/ia64/kernel/irq_ia64.c
 *
 * Copyright (C) 1998-2001 Hewlett-Packard Co
 *	Stephane Eranian <eranian@hpl.hp.com>
 *	David Mosberger-Tang <davidm@hpl.hp.com>
 *
 *  6/10/99: Updated to bring in sync with x86 version to facilitate
 *	     support for SMP and different interrupt controllers.
 *
 * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
 *                      PCI to vector allocation routine.
 * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
 *						Added CPU Hotplug handling for IPF.
 */

#include <linux/module.h>

#include <linux/jiffies.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/kernel_stat.h>
#include <linux/ptrace.h>
#include <linux/random.h>	/* for rand_initialize_irq() */
#include <linux/signal.h>
#include <linux/smp.h>
#include <linux/threads.h>
#include <linux/bitops.h>
#include <linux/irq.h>

#include <asm/delay.h>
#include <asm/intrinsics.h>
#include <asm/io.h>
#include <asm/hw_irq.h>
#include <asm/machvec.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/tlbflush.h>

#ifdef CONFIG_PERFMON
# include <asm/perfmon.h>
#endif

#define IRQ_DEBUG	0

#define IRQ_VECTOR_UNASSIGNED	(0)

#define IRQ_UNUSED		(0)
#define IRQ_USED		(1)
#define IRQ_RSVD		(2)

/* These can be overridden in platform_irq_init */
int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;

/* default base addr of IPI table */
void __iomem *ipi_base_addr = ((void __iomem *)
			       (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR));

static cpumask_t vector_allocation_domain(int cpu);

/*
 * Legacy IRQ to IA-64 vector translation table.
 */
__u8 isa_irq_to_vector_map[16] = {
	/* 8259 IRQ translation, first 16 entries */
	0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
	0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
};
EXPORT_SYMBOL(isa_irq_to_vector_map);

DEFINE_SPINLOCK(vector_lock);

struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
	[0 ... NR_IRQS - 1] = {
		.vector = IRQ_VECTOR_UNASSIGNED,
		.domain = CPU_MASK_NONE
	}
};

DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
	[0 ... IA64_NUM_VECTORS - 1] = -1
};

static cpumask_t vector_table[IA64_NUM_VECTORS] = {
	[0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
};

static int irq_status[NR_IRQS] = {
	[0 ... NR_IRQS -1] = IRQ_UNUSED
};

int check_irq_used(int irq)
{
	if (irq_status[irq] == IRQ_USED)
		return 1;

	return -1;
}

static inline int find_unassigned_irq(void)
{
	int irq;

	for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
		if (irq_status[irq] == IRQ_UNUSED)
			return irq;
	return -ENOSPC;
}

static inline int find_unassigned_vector(cpumask_t domain)
{
	cpumask_t mask;
	int pos, vector;

	cpus_and(mask, domain, cpu_online_map);
	if (cpus_empty(mask))
		return -EINVAL;

	for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
		vector = IA64_FIRST_DEVICE_VECTOR + pos;
		cpus_and(mask, domain, vector_table[vector]);
		if (!cpus_empty(mask))
			continue;
		return vector;
	}
	return -ENOSPC;
}

static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
{
	cpumask_t mask;
	int cpu;
	struct irq_cfg *cfg = &irq_cfg[irq];

	BUG_ON((unsigned)irq >= NR_IRQS);
	BUG_ON((unsigned)vector >= IA64_NUM_VECTORS);

	cpus_and(mask, domain, cpu_online_map);
	if (cpus_empty(mask))
		return -EINVAL;
	if ((cfg->vector == vector) && cpus_equal(cfg->domain, domain))
		return 0;
	if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
		return -EBUSY;
	for_each_cpu_mask(cpu, mask)
		per_cpu(vector_irq, cpu)[vector] = irq;
	cfg->vector = vector;
	cfg->domain = domain;
	irq_status[irq] = IRQ_USED;
	cpus_or(vector_table[vector], vector_table[vector], domain);
	return 0;
}

int bind_irq_vector(int irq, int vector, cpumask_t domain)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&vector_lock, flags);
	ret = __bind_irq_vector(irq, vector, domain);
	spin_unlock_irqrestore(&vector_lock, flags);
	return ret;
}

static void __clear_irq_vector(int irq)
{
	int vector, cpu;
	cpumask_t mask;
	cpumask_t domain;
	struct irq_cfg *cfg = &irq_cfg[irq];

	BUG_ON((unsigned)irq >= NR_IRQS);
	BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
	vector = cfg->vector;
	domain = cfg->domain;
	cpus_and(mask, cfg->domain, cpu_online_map);
	for_each_cpu_mask(cpu, mask)
		per_cpu(vector_irq, cpu)[vector] = -1;
	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	cfg->domain = CPU_MASK_NONE;
	irq_status[irq] = IRQ_UNUSED;
	cpus_andnot(vector_table[vector], vector_table[vector], domain);
}

static void clear_irq_vector(int irq)
{
	unsigned long flags;

	spin_lock_irqsave(&vector_lock, flags);
	__clear_irq_vector(irq);
	spin_unlock_irqrestore(&vector_lock, flags);
}

int
ia64_native_assign_irq_vector (int irq)
{
	unsigned long flags;
	int vector, cpu;
	cpumask_t domain = CPU_MASK_NONE;

	vector = -ENOSPC;

	spin_lock_irqsave(&vector_lock, flags);
	for_each_online_cpu(cpu) {
		domain = vector_allocation_domain(cpu);
		vector = find_unassigned_vector(domain);
		if (vector >= 0)
			break;
	}
	if (vector < 0)
		goto out;
	if (irq == AUTO_ASSIGN)
		irq = vector;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
 out:
	spin_unlock_irqrestore(&vector_lock, flags);
	return vector;
}

void
ia64_native_free_irq_vector (int vector)
{
	if (vector < IA64_FIRST_DEVICE_VECTOR ||
	    vector > IA64_LAST_DEVICE_VECTOR)
		return;
	clear_irq_vector(vector);
}

int
reserve_irq_vector (int vector)
{
	if (vector < IA64_FIRST_DEVICE_VECTOR ||
	    vector > IA64_LAST_DEVICE_VECTOR)
		return -EINVAL;
	return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
}

/*
 * Initialize vector_irq on a new cpu. This function must be called
 * with vector_lock held.
 */
void __setup_vector_irq(int cpu)
{
	int irq, vector;

	/* Clear vector_irq */
	for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
		per_cpu(vector_irq, cpu)[vector] = -1;
	/* Mark the inuse vectors */
	for (irq = 0; irq < NR_IRQS; ++irq) {
		if (!cpu_isset(cpu, irq_cfg[irq].domain))
			continue;
		vector = irq_to_vector(irq);
		per_cpu(vector_irq, cpu)[vector] = irq;
	}
}

#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG))

static enum vector_domain_type {
	VECTOR_DOMAIN_NONE,
	VECTOR_DOMAIN_PERCPU
} vector_domain_type = VECTOR_DOMAIN_NONE;

static cpumask_t vector_allocation_domain(int cpu)
{
	if (vector_domain_type == VECTOR_DOMAIN_PERCPU)
		return cpumask_of_cpu(cpu);
	return CPU_MASK_ALL;
}

static int __irq_prepare_move(int irq, int cpu)
{
	struct irq_cfg *cfg = &irq_cfg[irq];
	int vector;
	cpumask_t domain;

	if (cfg->move_in_progress || cfg->move_cleanup_count)
		return -EBUSY;
	if (cfg->vector == IRQ_VECTOR_UNASSIGNED || !cpu_online(cpu))
		return -EINVAL;
	if (cpu_isset(cpu, cfg->domain))
		return 0;
	domain = vector_allocation_domain(cpu);
	vector = find_unassigned_vector(domain);
	if (vector < 0)
		return -ENOSPC;
	cfg->move_in_progress = 1;
	cfg->old_domain = cfg->domain;
	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	cfg->domain = CPU_MASK_NONE;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
	return 0;
}

int irq_prepare_move(int irq, int cpu)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&vector_lock, flags);
	ret = __irq_prepare_move(irq, cpu);
	spin_unlock_irqrestore(&vector_lock, flags);
	return ret;
}

void irq_complete_move(unsigned irq)
{
	struct irq_cfg *cfg = &irq_cfg[irq];
	cpumask_t cleanup_mask;
	int i;

	if (likely(!cfg->move_in_progress))
		return;

	if (unlikely(cpu_isset(smp_processor_id(), cfg->old_domain)))
		return;

	cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
	cfg->move_cleanup_count = cpus_weight(cleanup_mask);
	for_each_cpu_mask(i, cleanup_mask)
		platform_send_ipi(i, IA64_IRQ_MOVE_VECTOR, IA64_IPI_DM_INT, 0);
	cfg->move_in_progress = 0;
}

static irqreturn_t smp_irq_move_cleanup_interrupt(int irq, void *dev_id)
{
	int me = smp_processor_id();
	ia64_vector vector;
	unsigned long flags;

	for (vector = IA64_FIRST_DEVICE_VECTOR;
	     vector < IA64_LAST_DEVICE_VECTOR; vector++) {
		int irq;
		struct irq_desc *desc;
		struct irq_cfg *cfg;
		irq = __get_cpu_var(vector_irq)[vector];
		if (irq < 0)
			continue;

		desc = irq_desc + irq;
		cfg = irq_cfg + irq;
		raw_spin_lock(&desc->lock);
		if (!cfg->move_cleanup_count)
			goto unlock;

		if (!cpu_isset(me, cfg->old_domain))
			goto unlock;

		spin_lock_irqsave(&vector_lock, flags);
		__get_cpu_var(vector_irq)[vector] = -1;
		cpu_clear(me, vector_table[vector]);
		spin_unlock_irqrestore(&vector_lock, flags);
		cfg->move_cleanup_count--;
	unlock:
		raw_spin_unlock(&desc->lock);
	}
	return IRQ_HANDLED;
}

static struct irqaction irq_move_irqaction = {
	.handler =	smp_irq_move_cleanup_interrupt,
	.flags =	IRQF_DISABLED,
	.name =		"irq_move"
};

static int __init parse_vector_domain(char *arg)
{
	if (!arg)
		return -EINVAL;
	if (!strcmp(arg, "percpu")) {
		vector_domain_type = VECTOR_DOMAIN_PERCPU;
		no_int_routing = 1;
	}
	return 0;
}
early_param("vector", parse_vector_domain);
#else
static cpumask_t vector_allocation_domain(int cpu)
{
	return CPU_MASK_ALL;
}
#endif


void destroy_and_reserve_irq(unsigned int irq)
{
	unsigned long flags;

	dynamic_irq_cleanup(irq);

	spin_lock_irqsave(&vector_lock, flags);
	__clear_irq_vector(irq);
	irq_status[irq] = IRQ_RSVD;
	spin_unlock_irqrestore(&vector_lock, flags);
}

/*
 * Dynamic irq allocate and deallocation for MSI
 */
int create_irq(void)
{
	unsigned long flags;
	int irq, vector, cpu;
	cpumask_t domain = CPU_MASK_NONE;

	irq = vector = -ENOSPC;
	spin_lock_irqsave(&vector_lock, flags);
	for_each_online_cpu(cpu) {
		domain = vector_allocation_domain(cpu);
		vector = find_unassigned_vector(domain);
		if (vector >= 0)
			break;
	}
	if (vector < 0)
		goto out;
	irq = find_unassigned_irq();
	if (irq < 0)
		goto out;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
 out:
	spin_unlock_irqrestore(&vector_lock, flags);
	if (irq >= 0)
		dynamic_irq_init(irq);
	return irq;
}

void destroy_irq(unsigned int irq)
{
	dynamic_irq_cleanup(irq);
	clear_irq_vector(irq);
}

#ifdef CONFIG_SMP
#	define IS_RESCHEDULE(vec)	(vec == IA64_IPI_RESCHEDULE)
#	define IS_LOCAL_TLB_FLUSH(vec)	(vec == IA64_IPI_LOCAL_TLB_FLUSH)
#else
#	define IS_RESCHEDULE(vec)	(0)
#	define IS_LOCAL_TLB_FLUSH(vec)	(0)
#endif
/*
 * That's where the IVT branches when we get an external
 * interrupt. This branches to the correct hardware IRQ handler via
 * function ptr.
 */
void
ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
{
	struct pt_regs *old_regs = set_irq_regs(regs);
	unsigned long saved_tpr;

#if IRQ_DEBUG
	{
		unsigned long bsp, sp;

		/*
		 * Note: if the interrupt happened while executing in
		 * the context switch routine (ia64_switch_to), we may
		 * get a spurious stack overflow here.  This is
		 * because the register and the memory stack are not
		 * switched atomically.
		 */
		bsp = ia64_getreg(_IA64_REG_AR_BSP);
		sp = ia64_getreg(_IA64_REG_SP);

		if ((sp - bsp) < 1024) {
			static unsigned char count;
			static long last_time;

			if (time_after(jiffies, last_time + 5 * HZ))
				count = 0;
			if (++count < 5) {
				last_time = jiffies;
				printk("ia64_handle_irq: DANGER: less than "
				       "1KB of free stack space!!\n"
				       "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
			}
		}
	}
#endif /* IRQ_DEBUG */

	/*
	 * Always set TPR to limit maximum interrupt nesting depth to
	 * 16 (without this, it would be ~240, which could easily lead
	 * to kernel stack overflows).
	 */
	irq_enter();
	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	ia64_srlz_d();
	while (vector != IA64_SPURIOUS_INT_VECTOR) {
		int irq = local_vector_to_irq(vector);
		struct irq_desc *desc = irq_to_desc(irq);

		if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
			smp_local_flush_tlb();
			kstat_incr_irqs_this_cpu(irq, desc);
		} else if (unlikely(IS_RESCHEDULE(vector))) {
			kstat_incr_irqs_this_cpu(irq, desc);
		} else {
			ia64_setreg(_IA64_REG_CR_TPR, vector);
			ia64_srlz_d();

			if (unlikely(irq < 0)) {
				printk(KERN_ERR "%s: Unexpected interrupt "
				       "vector %d on CPU %d is not mapped "
				       "to any IRQ!\n", __func__, vector,
				       smp_processor_id());
			} else
				generic_handle_irq(irq);

			/*
			 * Disable interrupts and send EOI:
			 */
			local_irq_disable();
			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
		}
		ia64_eoi();
		vector = ia64_get_ivr();
	}
	/*
	 * This must be done *after* the ia64_eoi().  For example, the keyboard softirq
	 * handler needs to be able to wait for further keyboard interrupts, which can't
	 * come through until ia64_eoi() has been done.
	 */
	irq_exit();
	set_irq_regs(old_regs);
}

#ifdef CONFIG_HOTPLUG_CPU
/*
 * This function emulates a interrupt processing when a cpu is about to be
 * brought down.
 */
void ia64_process_pending_intr(void)
{
	ia64_vector vector;
	unsigned long saved_tpr;
	extern unsigned int vectors_in_migration[NR_IRQS];

	vector = ia64_get_ivr();

	irq_enter();
	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	ia64_srlz_d();

	 /*
	  * Perform normal interrupt style processing
	  */
	while (vector != IA64_SPURIOUS_INT_VECTOR) {
		int irq = local_vector_to_irq(vector);
		struct irq_desc *desc = irq_to_desc(irq);

		if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
			smp_local_flush_tlb();
			kstat_incr_irqs_this_cpu(irq, desc);
		} else if (unlikely(IS_RESCHEDULE(vector))) {
			kstat_incr_irqs_this_cpu(irq, desc);
		} else {
			struct pt_regs *old_regs = set_irq_regs(NULL);

			ia64_setreg(_IA64_REG_CR_TPR, vector);
			ia64_srlz_d();

			/*
			 * Now try calling normal ia64_handle_irq as it would have got called
			 * from a real intr handler. Try passing null for pt_regs, hopefully
			 * it will work. I hope it works!.
			 * Probably could shared code.
			 */
			if (unlikely(irq < 0)) {
				printk(KERN_ERR "%s: Unexpected interrupt "
				       "vector %d on CPU %d not being mapped "
				       "to any IRQ!!\n", __func__, vector,
				       smp_processor_id());
			} else {
				vectors_in_migration[irq]=0;
				generic_handle_irq(irq);
			}
			set_irq_regs(old_regs);

			/*
			 * Disable interrupts and send EOI
			 */
			local_irq_disable();
			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
		}
		ia64_eoi();
		vector = ia64_get_ivr();
	}
	irq_exit();
}
#endif


#ifdef CONFIG_SMP

static irqreturn_t dummy_handler (int irq, void *dev_id)
{
	BUG();
}

static struct irqaction ipi_irqaction = {
	.handler =	handle_IPI,
	.flags =	IRQF_DISABLED,
	.name =		"IPI"
};

/*
 * KVM uses this interrupt to force a cpu out of guest mode
 */
static struct irqaction resched_irqaction = {
	.handler =	dummy_handler,
	.flags =	IRQF_DISABLED,
	.name =		"resched"
};

static struct irqaction tlb_irqaction = {
	.handler =	dummy_handler,
	.flags =	IRQF_DISABLED,
	.name =		"tlb_flush"
};

#endif

void
ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action)
{
	struct irq_desc *desc;
	unsigned int irq;

	irq = vec;
	BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
	desc = irq_desc + irq;
	desc->status |= IRQ_PER_CPU;
	desc->chip = &irq_type_ia64_lsapic;
	if (action)
		setup_irq(irq, action);
}

void __init
ia64_native_register_ipi(void)
{
#ifdef CONFIG_SMP
	register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
	register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
	register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
#endif
}

void __init
init_IRQ (void)
{
	ia64_register_ipi();
	register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
#ifdef CONFIG_SMP
#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG)
	if (vector_domain_type != VECTOR_DOMAIN_NONE)
		register_percpu_irq(IA64_IRQ_MOVE_VECTOR, &irq_move_irqaction);
#endif
#endif
#ifdef CONFIG_PERFMON
	pfm_init_percpu();
#endif
	platform_irq_init();
}

void
ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
{
	void __iomem *ipi_addr;
	unsigned long ipi_data;
	unsigned long phys_cpu_id;

	phys_cpu_id = cpu_physical_id(cpu);

	/*
	 * cpu number is in 8bit ID and 8bit EID
	 */

	ipi_data = (delivery_mode << 8) | (vector & 0xff);
	ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) | ((redirect & 1) << 3));

	writeq(ipi_data, ipi_addr);
}
Commit	Line	Data
1da177e4	1	/*
f30c2269	2	* linux/arch/ia64/kernel/irq_ia64.c
1da177e4 LT	3	*
	4	* Copyright (C) 1998-2001 Hewlett-Packard Co
	5	* Stephane Eranian <eranian@hpl.hp.com>
	6	* David Mosberger-Tang <davidm@hpl.hp.com>
	7	*
	8	* 6/10/99: Updated to bring in sync with x86 version to facilitate
	9	* support for SMP and different interrupt controllers.
	10	*
	11	* 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
	12	* PCI to vector allocation routine.
	13	* 04/14/2004 Ashok Raj <ashok.raj@intel.com>
	14	* Added CPU Hotplug handling for IPF.
	15	*/
	16
1da177e4 LT	17	#include <linux/module.h>
	18
	19	#include <linux/jiffies.h>
	20	#include <linux/errno.h>
	21	#include <linux/init.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/ioport.h>
	24	#include <linux/kernel_stat.h>
1da177e4 LT	25	#include <linux/ptrace.h>
	26	#include <linux/random.h> /* for rand_initialize_irq() */
	27	#include <linux/signal.h>
	28	#include <linux/smp.h>
1da177e4 LT	29	#include <linux/threads.h>
1da177e4 LT	30	#include <linux/bitops.h>
b6cf2583	31	#include <linux/irq.h>
1da177e4 LT	32
	33	#include <asm/delay.h>
	34	#include <asm/intrinsics.h>
	35	#include <asm/io.h>
	36	#include <asm/hw_irq.h>
	37	#include <asm/machvec.h>
	38	#include <asm/pgtable.h>
	39	#include <asm/system.h>
3be44b9c	40	#include <asm/tlbflush.h>
1da177e4 LT	41
	42	#ifdef CONFIG_PERFMON
	43	# include <asm/perfmon.h>
	44	#endif
	45
	46	#define IRQ_DEBUG 0
	47
e1b30a39 YI	48	#define IRQ_VECTOR_UNASSIGNED (0)
	49
	50	#define IRQ_UNUSED (0)
	51	#define IRQ_USED (1)
	52	#define IRQ_RSVD (2)
	53
10083072 MM	54	/* These can be overridden in platform_irq_init */
	55	int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
	56	int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;
	57
1da177e4 LT	58	/* default base addr of IPI table */
	59	void __iomem ipi_base_addr = ((void __iomem )
	60	(__IA64_UNCACHED_OFFSET \| IA64_IPI_DEFAULT_BASE_ADDR));
	61
4994be1b YI	62	static cpumask_t vector_allocation_domain(int cpu);
4994be1b YI	63
1da177e4 LT	64	/*
	65	* Legacy IRQ to IA-64 vector translation table.
	66	*/
	67	__u8 isa_irq_to_vector_map[16] = {
	68	/* 8259 IRQ translation, first 16 entries */
	69	0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
	70	0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
	71	};
	72	EXPORT_SYMBOL(isa_irq_to_vector_map);
	73
e1b30a39 YI	74	DEFINE_SPINLOCK(vector_lock);
	75
	76	struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
4994be1b YI	77	[0 ... NR_IRQS - 1] = {
	78	.vector = IRQ_VECTOR_UNASSIGNED,
	79	.domain = CPU_MASK_NONE
	80	}
e1b30a39 YI	81	};
	82
	83	DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
17764d24	84	[0 ... IA64_NUM_VECTORS - 1] = -1
e1b30a39 YI	85	};
e1b30a39 YI	86
6ffbc823 KK	87	static cpumask_t vector_table[IA64_NUM_VECTORS] = {
6ffbc823 KK	88	[0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
4994be1b YI	89	};
4994be1b YI	90
e1b30a39 YI	91	static int irq_status[NR_IRQS] = {
	92	[0 ... NR_IRQS -1] = IRQ_UNUSED
	93	};
	94
	95	int check_irq_used(int irq)
	96	{
	97	if (irq_status[irq] == IRQ_USED)
	98	return 1;
	99
	100	return -1;
	101	}
	102
e1b30a39 YI	103	static inline int find_unassigned_irq(void)
	104	{
	105	int irq;
	106
	107	for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
	108	if (irq_status[irq] == IRQ_UNUSED)
	109	return irq;
	110	return -ENOSPC;
	111	}
	112
4994be1b	113	static inline int find_unassigned_vector(cpumask_t domain)
e1b30a39	114	{
4994be1b	115	cpumask_t mask;
6ffbc823	116	int pos, vector;
4994be1b YI	117
	118	cpus_and(mask, domain, cpu_online_map);
	119	if (cpus_empty(mask))
	120	return -EINVAL;
e1b30a39	121
4994be1b	122	for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
6ffbc823 KK	123	vector = IA64_FIRST_DEVICE_VECTOR + pos;
6ffbc823 KK	124	cpus_and(mask, domain, vector_table[vector]);
4994be1b YI	125	if (!cpus_empty(mask))
4994be1b YI	126	continue;
6ffbc823	127	return vector;
4994be1b	128	}
e1b30a39 YI	129	return -ENOSPC;
	130	}
	131
4994be1b	132	static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
e1b30a39	133	{
4994be1b	134	cpumask_t mask;
6ffbc823	135	int cpu;
4994be1b	136	struct irq_cfg *cfg = &irq_cfg[irq];
e1b30a39	137
6bde71ec KK	138	BUG_ON((unsigned)irq >= NR_IRQS);
	139	BUG_ON((unsigned)vector >= IA64_NUM_VECTORS);
	140
4994be1b YI	141	cpus_and(mask, domain, cpu_online_map);
	142	if (cpus_empty(mask))
	143	return -EINVAL;
	144	if ((cfg->vector == vector) && cpus_equal(cfg->domain, domain))
e1b30a39	145	return 0;
4994be1b	146	if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
e1b30a39	147	return -EBUSY;
4994be1b	148	for_each_cpu_mask(cpu, mask)
e1b30a39	149	per_cpu(vector_irq, cpu)[vector] = irq;
4994be1b YI	150	cfg->vector = vector;
4994be1b YI	151	cfg->domain = domain;
e1b30a39	152	irq_status[irq] = IRQ_USED;
6ffbc823	153	cpus_or(vector_table[vector], vector_table[vector], domain);
e1b30a39 YI	154	return 0;
	155	}
	156
4994be1b	157	int bind_irq_vector(int irq, int vector, cpumask_t domain)
e1b30a39 YI	158	{
	159	unsigned long flags;
	160	int ret;
	161
	162	spin_lock_irqsave(&vector_lock, flags);
4994be1b	163	ret = __bind_irq_vector(irq, vector, domain);
e1b30a39 YI	164	spin_unlock_irqrestore(&vector_lock, flags);
	165	return ret;
	166	}
	167
cd378f18	168	static void __clear_irq_vector(int irq)
e1b30a39	169	{
6ffbc823	170	int vector, cpu;
4994be1b YI	171	cpumask_t mask;
	172	cpumask_t domain;
	173	struct irq_cfg *cfg = &irq_cfg[irq];
e1b30a39	174
e1b30a39	175	BUG_ON((unsigned)irq >= NR_IRQS);
4994be1b YI	176	BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
	177	vector = cfg->vector;
	178	domain = cfg->domain;
	179	cpus_and(mask, cfg->domain, cpu_online_map);
	180	for_each_cpu_mask(cpu, mask)
17764d24	181	per_cpu(vector_irq, cpu)[vector] = -1;
4994be1b YI	182	cfg->vector = IRQ_VECTOR_UNASSIGNED;
4994be1b YI	183	cfg->domain = CPU_MASK_NONE;
e1b30a39	184	irq_status[irq] = IRQ_UNUSED;
6ffbc823	185	cpus_andnot(vector_table[vector], vector_table[vector], domain);
cd378f18 YI	186	}
	187
	188	static void clear_irq_vector(int irq)
	189	{
	190	unsigned long flags;
	191
	192	spin_lock_irqsave(&vector_lock, flags);
	193	__clear_irq_vector(irq);
e1b30a39 YI	194	spin_unlock_irqrestore(&vector_lock, flags);
e1b30a39 YI	195	}
1da177e4 LT	196
1da177e4 LT	197	int
85cbc503	198	ia64_native_assign_irq_vector (int irq)
1da177e4	199	{
e1b30a39	200	unsigned long flags;
4994be1b	201	int vector, cpu;
373167e8	202	cpumask_t domain = CPU_MASK_NONE;
4994be1b YI	203
4994be1b YI	204	vector = -ENOSPC;
e1b30a39	205
4994be1b	206	spin_lock_irqsave(&vector_lock, flags);
4994be1b YI	207	for_each_online_cpu(cpu) {
	208	domain = vector_allocation_domain(cpu);
	209	vector = find_unassigned_vector(domain);
	210	if (vector >= 0)
	211	break;
	212	}
e1b30a39 YI	213	if (vector < 0)
e1b30a39 YI	214	goto out;
8f5ad1a8 YI	215	if (irq == AUTO_ASSIGN)
8f5ad1a8 YI	216	irq = vector;
4994be1b	217	BUG_ON(__bind_irq_vector(irq, vector, domain));
e1b30a39	218	out:
4994be1b	219	spin_unlock_irqrestore(&vector_lock, flags);
1da177e4 LT	220	return vector;
	221	}
	222
	223	void
85cbc503	224	ia64_native_free_irq_vector (int vector)
1da177e4	225	{
e1b30a39 YI	226	if (vector < IA64_FIRST_DEVICE_VECTOR \|\|
e1b30a39 YI	227	vector > IA64_LAST_DEVICE_VECTOR)
1da177e4	228	return;
e1b30a39	229	clear_irq_vector(vector);
1da177e4 LT	230	}
1da177e4 LT	231
10083072 MM	232	int
	233	reserve_irq_vector (int vector)
	234	{
10083072 MM	235	if (vector < IA64_FIRST_DEVICE_VECTOR \|\|
	236	vector > IA64_LAST_DEVICE_VECTOR)
	237	return -EINVAL;
4994be1b	238	return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
e1b30a39	239	}
10083072	240
e1b30a39 YI	241	/*
	242	* Initialize vector_irq on a new cpu. This function must be called
	243	* with vector_lock held.
	244	*/
	245	void __setup_vector_irq(int cpu)
	246	{
	247	int irq, vector;
	248
	249	/* Clear vector_irq */
	250	for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
17764d24	251	per_cpu(vector_irq, cpu)[vector] = -1;
e1b30a39 YI	252	/* Mark the inuse vectors */
e1b30a39 YI	253	for (irq = 0; irq < NR_IRQS; ++irq) {
4994be1b YI	254	if (!cpu_isset(cpu, irq_cfg[irq].domain))
	255	continue;
	256	vector = irq_to_vector(irq);
	257	per_cpu(vector_irq, cpu)[vector] = irq;
e1b30a39 YI	258	}
	259	}
	260
e5bd762b	261	#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) \|\| defined(CONFIG_IA64_DIG))
a6cd6322	262
d080d397 YI	263	static enum vector_domain_type {
	264	VECTOR_DOMAIN_NONE,
	265	VECTOR_DOMAIN_PERCPU
	266	} vector_domain_type = VECTOR_DOMAIN_NONE;
	267
4994be1b YI	268	static cpumask_t vector_allocation_domain(int cpu)
4994be1b YI	269	{
d080d397 YI	270	if (vector_domain_type == VECTOR_DOMAIN_PERCPU)
d080d397 YI	271	return cpumask_of_cpu(cpu);
4994be1b YI	272	return CPU_MASK_ALL;
	273	}
	274
a6cd6322 KK	275	static int __irq_prepare_move(int irq, int cpu)
	276	{
	277	struct irq_cfg *cfg = &irq_cfg[irq];
	278	int vector;
	279	cpumask_t domain;
	280
	281	if (cfg->move_in_progress \|\| cfg->move_cleanup_count)
	282	return -EBUSY;
	283	if (cfg->vector == IRQ_VECTOR_UNASSIGNED \|\| !cpu_online(cpu))
	284	return -EINVAL;
	285	if (cpu_isset(cpu, cfg->domain))
	286	return 0;
	287	domain = vector_allocation_domain(cpu);
	288	vector = find_unassigned_vector(domain);
	289	if (vector < 0)
	290	return -ENOSPC;
	291	cfg->move_in_progress = 1;
	292	cfg->old_domain = cfg->domain;
	293	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	294	cfg->domain = CPU_MASK_NONE;
	295	BUG_ON(__bind_irq_vector(irq, vector, domain));
	296	return 0;
	297	}
	298
	299	int irq_prepare_move(int irq, int cpu)
	300	{
	301	unsigned long flags;
	302	int ret;
	303
	304	spin_lock_irqsave(&vector_lock, flags);
	305	ret = __irq_prepare_move(irq, cpu);
	306	spin_unlock_irqrestore(&vector_lock, flags);
	307	return ret;
	308	}
	309
	310	void irq_complete_move(unsigned irq)
	311	{
	312	struct irq_cfg *cfg = &irq_cfg[irq];
	313	cpumask_t cleanup_mask;
	314	int i;
	315
	316	if (likely(!cfg->move_in_progress))
	317	return;
	318
	319	if (unlikely(cpu_isset(smp_processor_id(), cfg->old_domain)))
	320	return;
	321
	322	cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
	323	cfg->move_cleanup_count = cpus_weight(cleanup_mask);
	324	for_each_cpu_mask(i, cleanup_mask)
	325	platform_send_ipi(i, IA64_IRQ_MOVE_VECTOR, IA64_IPI_DM_INT, 0);
	326	cfg->move_in_progress = 0;
	327	}
	328
	329	static irqreturn_t smp_irq_move_cleanup_interrupt(int irq, void *dev_id)
	330	{
	331	int me = smp_processor_id();
	332	ia64_vector vector;
	333	unsigned long flags;
	334
	335	for (vector = IA64_FIRST_DEVICE_VECTOR;
	336	vector < IA64_LAST_DEVICE_VECTOR; vector++) {
	337	int irq;
	338	struct irq_desc *desc;
339	struct irq_cfg *cfg;
340	irq = __get_cpu_var(vector_irq)[vector];
341	if (irq < 0)
342	continue;
343
344	desc = irq_desc + irq;
345	cfg = irq_cfg + irq;
239007b8	346	raw_spin_lock(&desc->lock);
a6cd6322 KK	347	if (!cfg->move_cleanup_count)
	348	goto unlock;
	349
	350	if (!cpu_isset(me, cfg->old_domain))
	351	goto unlock;
	352
	353	spin_lock_irqsave(&vector_lock, flags);
	354	__get_cpu_var(vector_irq)[vector] = -1;
	355	cpu_clear(me, vector_table[vector]);
	356	spin_unlock_irqrestore(&vector_lock, flags);
	357	cfg->move_cleanup_count--;
	358	unlock:
239007b8	359	raw_spin_unlock(&desc->lock);
a6cd6322 KK	360	}
	361	return IRQ_HANDLED;
	362	}
	363
	364	static struct irqaction irq_move_irqaction = {
	365	.handler = smp_irq_move_cleanup_interrupt,
	366	.flags = IRQF_DISABLED,
	367	.name = "irq_move"
	368	};
	369
d080d397 YI	370	static int __init parse_vector_domain(char *arg)
	371	{
	372	if (!arg)
	373	return -EINVAL;
	374	if (!strcmp(arg, "percpu")) {
	375	vector_domain_type = VECTOR_DOMAIN_PERCPU;
	376	no_int_routing = 1;
	377	}
074ff856	378	return 0;
d080d397 YI	379	}
	380	early_param("vector", parse_vector_domain);
	381	#else
	382	static cpumask_t vector_allocation_domain(int cpu)
	383	{
	384	return CPU_MASK_ALL;
	385	}
	386	#endif
	387
4994be1b	388
e1b30a39 YI	389	void destroy_and_reserve_irq(unsigned int irq)
e1b30a39 YI	390	{
216fcd29 KK	391	unsigned long flags;
216fcd29 KK	392
e1b30a39 YI	393	dynamic_irq_cleanup(irq);
e1b30a39 YI	394
216fcd29 KK	395	spin_lock_irqsave(&vector_lock, flags);
	396	__clear_irq_vector(irq);
	397	irq_status[irq] = IRQ_RSVD;
	398	spin_unlock_irqrestore(&vector_lock, flags);
10083072 MM	399	}
10083072 MM	400
b6cf2583 EB	401	/*
	402	* Dynamic irq allocate and deallocation for MSI
	403	*/
	404	int create_irq(void)
	405	{
e1b30a39	406	unsigned long flags;
4994be1b	407	int irq, vector, cpu;
373167e8	408	cpumask_t domain = CPU_MASK_NONE;
e1b30a39	409
4994be1b	410	irq = vector = -ENOSPC;
e1b30a39	411	spin_lock_irqsave(&vector_lock, flags);
4994be1b YI	412	for_each_online_cpu(cpu) {
	413	domain = vector_allocation_domain(cpu);
	414	vector = find_unassigned_vector(domain);
	415	if (vector >= 0)
	416	break;
	417	}
e1b30a39 YI	418	if (vector < 0)
	419	goto out;
	420	irq = find_unassigned_irq();
	421	if (irq < 0)
	422	goto out;
4994be1b	423	BUG_ON(__bind_irq_vector(irq, vector, domain));
e1b30a39 YI	424	out:
	425	spin_unlock_irqrestore(&vector_lock, flags);
	426	if (irq >= 0)
	427	dynamic_irq_init(irq);
	428	return irq;
b6cf2583 EB	429	}
	430
	431	void destroy_irq(unsigned int irq)
	432	{
	433	dynamic_irq_cleanup(irq);
e1b30a39	434	clear_irq_vector(irq);
b6cf2583 EB	435	}
b6cf2583 EB	436
1da177e4 LT	437	#ifdef CONFIG_SMP
1da177e4 LT	438	# define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE)
3be44b9c	439	# define IS_LOCAL_TLB_FLUSH(vec) (vec == IA64_IPI_LOCAL_TLB_FLUSH)
1da177e4 LT	440	#else
1da177e4 LT	441	# define IS_RESCHEDULE(vec) (0)
3be44b9c	442	# define IS_LOCAL_TLB_FLUSH(vec) (0)
1da177e4 LT	443	#endif
	444	/*
	445	* That's where the IVT branches when we get an external
	446	* interrupt. This branches to the correct hardware IRQ handler via
	447	* function ptr.
	448	*/
	449	void
	450	ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
	451	{
7d12e780	452	struct pt_regs *old_regs = set_irq_regs(regs);
1da177e4 LT	453	unsigned long saved_tpr;
	454
	455	#if IRQ_DEBUG
	456	{
	457	unsigned long bsp, sp;
	458
	459	/*
	460	* Note: if the interrupt happened while executing in
	461	* the context switch routine (ia64_switch_to), we may
	462	* get a spurious stack overflow here. This is
	463	* because the register and the memory stack are not
	464	* switched atomically.
	465	*/
	466	bsp = ia64_getreg(_IA64_REG_AR_BSP);
	467	sp = ia64_getreg(_IA64_REG_SP);
	468
	469	if ((sp - bsp) < 1024) {
	470	static unsigned char count;
	471	static long last_time;
	472
5cf1f7ce	473	if (time_after(jiffies, last_time + 5 * HZ))
1da177e4 LT	474	count = 0;
	475	if (++count < 5) {
	476	last_time = jiffies;
	477	printk("ia64_handle_irq: DANGER: less than "
	478	"1KB of free stack space!!\n"
	479	"(bsp=0x%lx, sp=%lx)\n", bsp, sp);
	480	}
	481	}
	482	}
	483	#endif /* IRQ_DEBUG */
	484
	485	/*
	486	* Always set TPR to limit maximum interrupt nesting depth to
	487	* 16 (without this, it would be ~240, which could easily lead
	488	* to kernel stack overflows).
	489	*/
	490	irq_enter();
	491	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	492	ia64_srlz_d();
	493	while (vector != IA64_SPURIOUS_INT_VECTOR) {
66f3e6af	494	int irq = local_vector_to_irq(vector);
7c730ccd	495	struct irq_desc *desc = irq_to_desc(irq);
66f3e6af	496
3be44b9c JS	497	if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
3be44b9c JS	498	smp_local_flush_tlb();
66f3e6af	499	kstat_incr_irqs_this_cpu(irq, desc);
7c730ccd	500	} else if (unlikely(IS_RESCHEDULE(vector))) {
66f3e6af	501	kstat_incr_irqs_this_cpu(irq, desc);
7c730ccd	502	} else {
1da177e4 LT	503	ia64_setreg(_IA64_REG_CR_TPR, vector);
	504	ia64_srlz_d();
	505
17764d24 KK	506	if (unlikely(irq < 0)) {
	507	printk(KERN_ERR "%s: Unexpected interrupt "
	508	"vector %d on CPU %d is not mapped "
d4ed8084	509	"to any IRQ!\n", __func__, vector,
17764d24 KK	510	smp_processor_id());
	511	} else
	512	generic_handle_irq(irq);
1da177e4 LT	513
	514	/*
	515	* Disable interrupts and send EOI:
	516	*/
	517	local_irq_disable();
	518	ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
	519	}
	520	ia64_eoi();
	521	vector = ia64_get_ivr();
	522	}
	523	/*
	524	* This must be done after the ia64_eoi(). For example, the keyboard softirq
	525	* handler needs to be able to wait for further keyboard interrupts, which can't
	526	* come through until ia64_eoi() has been done.
	527	*/
	528	irq_exit();
7d12e780	529	set_irq_regs(old_regs);
1da177e4 LT	530	}
	531
	532	#ifdef CONFIG_HOTPLUG_CPU
	533	/*
	534	* This function emulates a interrupt processing when a cpu is about to be
	535	* brought down.
	536	*/
	537	void ia64_process_pending_intr(void)
	538	{
	539	ia64_vector vector;
	540	unsigned long saved_tpr;
	541	extern unsigned int vectors_in_migration[NR_IRQS];
	542
	543	vector = ia64_get_ivr();
	544
66f3e6af JS	545	irq_enter();
	546	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	547	ia64_srlz_d();
1da177e4 LT	548
	549	/*
	550	* Perform normal interrupt style processing
	551	*/
	552	while (vector != IA64_SPURIOUS_INT_VECTOR) {
66f3e6af	553	int irq = local_vector_to_irq(vector);
7c730ccd	554	struct irq_desc *desc = irq_to_desc(irq);
66f3e6af	555
3be44b9c JS	556	if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
3be44b9c JS	557	smp_local_flush_tlb();
66f3e6af	558	kstat_incr_irqs_this_cpu(irq, desc);
7c730ccd	559	} else if (unlikely(IS_RESCHEDULE(vector))) {
66f3e6af	560	kstat_incr_irqs_this_cpu(irq, desc);
7c730ccd	561	} else {
8c1addbc TL	562	struct pt_regs *old_regs = set_irq_regs(NULL);
8c1addbc TL	563
1da177e4 LT	564	ia64_setreg(_IA64_REG_CR_TPR, vector);
	565	ia64_srlz_d();
	566
	567	/*
	568	* Now try calling normal ia64_handle_irq as it would have got called
	569	* from a real intr handler. Try passing null for pt_regs, hopefully
	570	* it will work. I hope it works!.
	571	* Probably could shared code.
	572	*/
17764d24 KK	573	if (unlikely(irq < 0)) {
	574	printk(KERN_ERR "%s: Unexpected interrupt "
	575	"vector %d on CPU %d not being mapped "
d4ed8084	576	"to any IRQ!!\n", __func__, vector,
17764d24 KK	577	smp_processor_id());
	578	} else {
	579	vectors_in_migration[irq]=0;
	580	generic_handle_irq(irq);
	581	}
8c1addbc	582	set_irq_regs(old_regs);
1da177e4 LT	583
	584	/*
	585	* Disable interrupts and send EOI
	586	*/
	587	local_irq_disable();
	588	ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
	589	}
	590	ia64_eoi();
	591	vector = ia64_get_ivr();
	592	}
	593	irq_exit();
	594	}
	595	#endif
	596
	597
	598	#ifdef CONFIG_SMP
1da177e4	599
9b3377f9 JS	600	static irqreturn_t dummy_handler (int irq, void *dev_id)
	601	{
	602	BUG();
	603	}
	604
1da177e4 LT	605	static struct irqaction ipi_irqaction = {
1da177e4 LT	606	.handler = handle_IPI,
121a4226	607	.flags = IRQF_DISABLED,
1da177e4 LT	608	.name = "IPI"
1da177e4 LT	609	};
9b3377f9	610
32f88400 MT	611	/*
	612	* KVM uses this interrupt to force a cpu out of guest mode
	613	*/
9b3377f9 JS	614	static struct irqaction resched_irqaction = {
9b3377f9 JS	615	.handler = dummy_handler,
38515e90	616	.flags = IRQF_DISABLED,
9b3377f9 JS	617	.name = "resched"
9b3377f9 JS	618	};
3be44b9c JS	619
	620	static struct irqaction tlb_irqaction = {
	621	.handler = dummy_handler,
5329571b	622	.flags = IRQF_DISABLED,
3be44b9c JS	623	.name = "tlb_flush"
	624	};
	625
1da177e4 LT	626	#endif
	627
	628	void
85cbc503	629	ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action)
1da177e4	630	{
86bc3dfe	631	struct irq_desc *desc;
1da177e4 LT	632	unsigned int irq;
1da177e4 LT	633
e1b30a39	634	irq = vec;
4994be1b	635	BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
e1b30a39 YI	636	desc = irq_desc + irq;
	637	desc->status \|= IRQ_PER_CPU;
	638	desc->chip = &irq_type_ia64_lsapic;
	639	if (action)
	640	setup_irq(irq, action);
1da177e4 LT	641	}
	642
	643	void __init
85cbc503	644	ia64_native_register_ipi(void)
1da177e4	645	{
1da177e4 LT	646	#ifdef CONFIG_SMP
1da177e4 LT	647	register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
9b3377f9	648	register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
3be44b9c	649	register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
85cbc503 IY	650	#endif
	651	}
	652
	653	void __init
	654	init_IRQ (void)
	655	{
	656	ia64_register_ipi();
	657	register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
	658	#ifdef CONFIG_SMP
a6cd6322	659	#if defined(CONFIG_IA64_GENERIC) \|\| defined(CONFIG_IA64_DIG)
09b366b7	660	if (vector_domain_type != VECTOR_DOMAIN_NONE)
a6cd6322	661	register_percpu_irq(IA64_IRQ_MOVE_VECTOR, &irq_move_irqaction);
a6cd6322	662	#endif
1da177e4 LT	663	#endif
	664	#ifdef CONFIG_PERFMON
	665	pfm_init_percpu();
	666	#endif
	667	platform_irq_init();
	668	}
	669
	670	void
	671	ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
	672	{
	673	void __iomem *ipi_addr;
	674	unsigned long ipi_data;
	675	unsigned long phys_cpu_id;
	676
1da177e4	677	phys_cpu_id = cpu_physical_id(cpu);
1da177e4 LT	678
	679	/*
	680	* cpu number is in 8bit ID and 8bit EID
	681	*/
	682
	683	ipi_data = (delivery_mode << 8) \| (vector & 0xff);
	684	ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) \| ((redirect & 1) << 3));
	685
	686	writeq(ipi_data, ipi_addr);
	687	}