[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / ia64 / include / asm / io.h

#ifndef _ASM_IA64_IO_H
#define _ASM_IA64_IO_H

/*
 * This file contains the definitions for the emulated IO instructions
 * inb/inw/inl/outb/outw/outl and the "string versions" of the same
 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
 * versions of the single-IO instructions (inb_p/inw_p/..).
 *
 * This file is not meant to be obfuscating: it's just complicated to
 * (a) handle it all in a way that makes gcc able to optimize it as
 * well as possible and (b) trying to avoid writing the same thing
 * over and over again with slight variations and possibly making a
 * mistake somewhere.
 *
 * Copyright (C) 1998-2003 Hewlett-Packard Co
 *	David Mosberger-Tang <davidm@hpl.hp.com>
 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
 */

#include <asm/unaligned.h>

/* We don't use IO slowdowns on the ia64, but.. */
#define __SLOW_DOWN_IO	do { } while (0)
#define SLOW_DOWN_IO	do { } while (0)

#define __IA64_UNCACHED_OFFSET	RGN_BASE(RGN_UNCACHED)

/*
 * The legacy I/O space defined by the ia64 architecture supports only 65536 ports, but
 * large machines may have multiple other I/O spaces so we can't place any a priori limit
 * on IO_SPACE_LIMIT.  These additional spaces are described in ACPI.
 */
#define IO_SPACE_LIMIT		0xffffffffffffffffUL

#define MAX_IO_SPACES_BITS		8
#define MAX_IO_SPACES			(1UL << MAX_IO_SPACES_BITS)
#define IO_SPACE_BITS			24
#define IO_SPACE_SIZE			(1UL << IO_SPACE_BITS)

#define IO_SPACE_NR(port)		((port) >> IO_SPACE_BITS)
#define IO_SPACE_BASE(space)		((space) << IO_SPACE_BITS)
#define IO_SPACE_PORT(port)		((port) & (IO_SPACE_SIZE - 1))

#define IO_SPACE_SPARSE_ENCODING(p)	((((p) >> 2) << 12) | ((p) & 0xfff))

struct io_space {
	unsigned long mmio_base;	/* base in MMIO space */
	int sparse;
};

extern struct io_space io_space[];
extern unsigned int num_io_spaces;

# ifdef __KERNEL__

/*
 * All MMIO iomem cookies are in region 6; anything less is a PIO cookie:
 *	0xCxxxxxxxxxxxxxxx	MMIO cookie (return from ioremap)
 *	0x000000001SPPPPPP	PIO cookie (S=space number, P..P=port)
 *
 * ioread/writeX() uses the leading 1 in PIO cookies (PIO_OFFSET) to catch
 * code that uses bare port numbers without the prerequisite pci_iomap().
 */
#define PIO_OFFSET		(1UL << (MAX_IO_SPACES_BITS + IO_SPACE_BITS))
#define PIO_MASK		(PIO_OFFSET - 1)
#define PIO_RESERVED		__IA64_UNCACHED_OFFSET
#define HAVE_ARCH_PIO_SIZE

#include <asm/intrinsics.h>
#include <asm/machvec.h>
#include <asm/page.h>
#include <asm/system.h>
#include <asm-generic/iomap.h>

/*
 * Change virtual addresses to physical addresses and vv.
 */
static inline unsigned long
virt_to_phys (volatile void *address)
{
	return (unsigned long) address - PAGE_OFFSET;
}

static inline void*
phys_to_virt (unsigned long address)
{
	return (void *) (address + PAGE_OFFSET);
}

#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
extern u64 kern_mem_attribute (unsigned long phys_addr, unsigned long size);
extern int valid_phys_addr_range (unsigned long addr, size_t count); /* efi.c */
extern int valid_mmap_phys_addr_range (unsigned long pfn, size_t count);

/*
 * The following two macros are deprecated and scheduled for removal.
 * Please use the PCI-DMA interface defined in <asm/pci.h> instead.
 */
#define bus_to_virt	phys_to_virt
#define virt_to_bus	virt_to_phys
#define page_to_bus	page_to_phys

# endif /* KERNEL */

/*
 * Memory fence w/accept.  This should never be used in code that is
 * not IA-64 specific.
 */
#define __ia64_mf_a()	ia64_mfa()

/**
 * ___ia64_mmiowb - I/O write barrier
 *
 * Ensure ordering of I/O space writes.  This will make sure that writes
 * following the barrier will arrive after all previous writes.  For most
 * ia64 platforms, this is a simple 'mf.a' instruction.
 *
 * See Documentation/DocBook/deviceiobook.tmpl for more information.
 */
static inline void ___ia64_mmiowb(void)
{
	ia64_mfa();
}

static inline void*
__ia64_mk_io_addr (unsigned long port)
{
	struct io_space *space;
	unsigned long offset;

	space = &io_space[IO_SPACE_NR(port)];
	port = IO_SPACE_PORT(port);
	if (space->sparse)
		offset = IO_SPACE_SPARSE_ENCODING(port);
	else
		offset = port;

	return (void *) (space->mmio_base | offset);
}

#define __ia64_inb	___ia64_inb
#define __ia64_inw	___ia64_inw
#define __ia64_inl	___ia64_inl
#define __ia64_outb	___ia64_outb
#define __ia64_outw	___ia64_outw
#define __ia64_outl	___ia64_outl
#define __ia64_readb	___ia64_readb
#define __ia64_readw	___ia64_readw
#define __ia64_readl	___ia64_readl
#define __ia64_readq	___ia64_readq
#define __ia64_readb_relaxed	___ia64_readb
#define __ia64_readw_relaxed	___ia64_readw
#define __ia64_readl_relaxed	___ia64_readl
#define __ia64_readq_relaxed	___ia64_readq
#define __ia64_writeb	___ia64_writeb
#define __ia64_writew	___ia64_writew
#define __ia64_writel	___ia64_writel
#define __ia64_writeq	___ia64_writeq
#define __ia64_mmiowb	___ia64_mmiowb

/*
 * For the in/out routines, we need to do "mf.a" _after_ doing the I/O access to ensure
 * that the access has completed before executing other I/O accesses.  Since we're doing
 * the accesses through an uncachable (UC) translation, the CPU will execute them in
 * program order.  However, we still need to tell the compiler not to shuffle them around
 * during optimization, which is why we use "volatile" pointers.
 */

static inline unsigned int
___ia64_inb (unsigned long port)
{
	volatile unsigned char *addr = __ia64_mk_io_addr(port);
	unsigned char ret;

	ret = *addr;
	__ia64_mf_a();
	return ret;
}

static inline unsigned int
___ia64_inw (unsigned long port)
{
	volatile unsigned short *addr = __ia64_mk_io_addr(port);
	unsigned short ret;

	ret = *addr;
	__ia64_mf_a();
	return ret;
}

static inline unsigned int
___ia64_inl (unsigned long port)
{
	volatile unsigned int *addr = __ia64_mk_io_addr(port);
	unsigned int ret;

	ret = *addr;
	__ia64_mf_a();
	return ret;
}

static inline void
___ia64_outb (unsigned char val, unsigned long port)
{
	volatile unsigned char *addr = __ia64_mk_io_addr(port);

	*addr = val;
	__ia64_mf_a();
}

static inline void
___ia64_outw (unsigned short val, unsigned long port)
{
	volatile unsigned short *addr = __ia64_mk_io_addr(port);

	*addr = val;
	__ia64_mf_a();
}

static inline void
___ia64_outl (unsigned int val, unsigned long port)
{
	volatile unsigned int *addr = __ia64_mk_io_addr(port);

	*addr = val;
	__ia64_mf_a();
}

static inline void
__insb (unsigned long port, void *dst, unsigned long count)
{
	unsigned char *dp = dst;

	while (count--)
		*dp++ = platform_inb(port);
}

static inline void
__insw (unsigned long port, void *dst, unsigned long count)
{
	unsigned short *dp = dst;

	while (count--)
		put_unaligned(platform_inw(port), dp++);
}

static inline void
__insl (unsigned long port, void *dst, unsigned long count)
{
	unsigned int *dp = dst;

	while (count--)
		put_unaligned(platform_inl(port), dp++);
}

static inline void
__outsb (unsigned long port, const void *src, unsigned long count)
{
	const unsigned char *sp = src;

	while (count--)
		platform_outb(*sp++, port);
}

static inline void
__outsw (unsigned long port, const void *src, unsigned long count)
{
	const unsigned short *sp = src;

	while (count--)
		platform_outw(get_unaligned(sp++), port);
}

static inline void
__outsl (unsigned long port, const void *src, unsigned long count)
{
	const unsigned int *sp = src;

	while (count--)
		platform_outl(get_unaligned(sp++), port);
}

/*
 * Unfortunately, some platforms are broken and do not follow the IA-64 architecture
 * specification regarding legacy I/O support.  Thus, we have to make these operations
 * platform dependent...
 */
#define __inb		platform_inb
#define __inw		platform_inw
#define __inl		platform_inl
#define __outb		platform_outb
#define __outw		platform_outw
#define __outl		platform_outl
#define __mmiowb	platform_mmiowb

#define inb(p)		__inb(p)
#define inw(p)		__inw(p)
#define inl(p)		__inl(p)
#define insb(p,d,c)	__insb(p,d,c)
#define insw(p,d,c)	__insw(p,d,c)
#define insl(p,d,c)	__insl(p,d,c)
#define outb(v,p)	__outb(v,p)
#define outw(v,p)	__outw(v,p)
#define outl(v,p)	__outl(v,p)
#define outsb(p,s,c)	__outsb(p,s,c)
#define outsw(p,s,c)	__outsw(p,s,c)
#define outsl(p,s,c)	__outsl(p,s,c)
#define mmiowb()	__mmiowb()

/*
 * The address passed to these functions are ioremap()ped already.
 *
 * We need these to be machine vectors since some platforms don't provide
 * DMA coherence via PIO reads (PCI drivers and the spec imply that this is
 * a good idea).  Writes are ok though for all existing ia64 platforms (and
 * hopefully it'll stay that way).
 */
static inline unsigned char
___ia64_readb (const volatile void __iomem *addr)
{
	return *(volatile unsigned char __force *)addr;
}

static inline unsigned short
___ia64_readw (const volatile void __iomem *addr)
{
	return *(volatile unsigned short __force *)addr;
}

static inline unsigned int
___ia64_readl (const volatile void __iomem *addr)
{
	return *(volatile unsigned int __force *) addr;
}

static inline unsigned long
___ia64_readq (const volatile void __iomem *addr)
{
	return *(volatile unsigned long __force *) addr;
}

static inline void
__writeb (unsigned char val, volatile void __iomem *addr)
{
	*(volatile unsigned char __force *) addr = val;
}

static inline void
__writew (unsigned short val, volatile void __iomem *addr)
{
	*(volatile unsigned short __force *) addr = val;
}

static inline void
__writel (unsigned int val, volatile void __iomem *addr)
{
	*(volatile unsigned int __force *) addr = val;
}

static inline void
__writeq (unsigned long val, volatile void __iomem *addr)
{
	*(volatile unsigned long __force *) addr = val;
}

#define __readb		platform_readb
#define __readw		platform_readw
#define __readl		platform_readl
#define __readq		platform_readq
#define __readb_relaxed	platform_readb_relaxed
#define __readw_relaxed	platform_readw_relaxed
#define __readl_relaxed	platform_readl_relaxed
#define __readq_relaxed	platform_readq_relaxed

#define readb(a)	__readb((a))
#define readw(a)	__readw((a))
#define readl(a)	__readl((a))
#define readq(a)	__readq((a))
#define readb_relaxed(a)	__readb_relaxed((a))
#define readw_relaxed(a)	__readw_relaxed((a))
#define readl_relaxed(a)	__readl_relaxed((a))
#define readq_relaxed(a)	__readq_relaxed((a))
#define __raw_readb	readb
#define __raw_readw	readw
#define __raw_readl	readl
#define __raw_readq	readq
#define __raw_readb_relaxed	readb_relaxed
#define __raw_readw_relaxed	readw_relaxed
#define __raw_readl_relaxed	readl_relaxed
#define __raw_readq_relaxed	readq_relaxed
#define writeb(v,a)	__writeb((v), (a))
#define writew(v,a)	__writew((v), (a))
#define writel(v,a)	__writel((v), (a))
#define writeq(v,a)	__writeq((v), (a))
#define __raw_writeb	writeb
#define __raw_writew	writew
#define __raw_writel	writel
#define __raw_writeq	writeq

#ifndef inb_p
# define inb_p		inb
#endif
#ifndef inw_p
# define inw_p		inw
#endif
#ifndef inl_p
# define inl_p		inl
#endif

#ifndef outb_p
# define outb_p		outb
#endif
#ifndef outw_p
# define outw_p		outw
#endif
#ifndef outl_p
# define outl_p		outl
#endif

# ifdef __KERNEL__

extern void __iomem * ioremap(unsigned long offset, unsigned long size);
extern void __iomem * ioremap_nocache (unsigned long offset, unsigned long size);
extern void iounmap (volatile void __iomem *addr);

/*
 * String version of IO memory access ops:
 */
extern void memcpy_fromio(void *dst, const volatile void __iomem *src, long n);
extern void memcpy_toio(volatile void __iomem *dst, const void *src, long n);
extern void memset_io(volatile void __iomem *s, int c, long n);

# endif /* __KERNEL__ */

/*
 * Enabling BIO_VMERGE_BOUNDARY forces us to turn off I/O MMU bypassing.  It is said that
 * BIO-level virtual merging can give up to 4% performance boost (not verified for ia64).
 * On the other hand, we know that I/O MMU bypassing gives ~8% performance improvement on
 * SPECweb-like workloads on zx1-based machines.  Thus, for now we favor I/O MMU bypassing
 * over BIO-level virtual merging.
 */
extern unsigned long ia64_max_iommu_merge_mask;
#if 1
#define BIO_VMERGE_BOUNDARY	0
#else
/*
 * It makes no sense at all to have this BIO_VMERGE_BOUNDARY macro here.  Should be
 * replaced by dma_merge_mask() or something of that sort.  Note: the only way
 * BIO_VMERGE_BOUNDARY is used is to mask off bits.  Effectively, our definition gets
 * expanded into:
 *
 *	addr & ((ia64_max_iommu_merge_mask + 1) - 1) == (addr & ia64_max_iommu_vmerge_mask)
 *
 * which is precisely what we want.
 */
#define BIO_VMERGE_BOUNDARY	(ia64_max_iommu_merge_mask + 1)
#endif

#endif /* _ASM_IA64_IO_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef _ASM_IA64_IO_H
	2	#define _ASM_IA64_IO_H
	3
	4	/*
	5	* This file contains the definitions for the emulated IO instructions
	6	* inb/inw/inl/outb/outw/outl and the "string versions" of the same
	7	* (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
	8	* versions of the single-IO instructions (inb_p/inw_p/..).
	9	*
	10	* This file is not meant to be obfuscating: it's just complicated to
	11	* (a) handle it all in a way that makes gcc able to optimize it as
	12	* well as possible and (b) trying to avoid writing the same thing
	13	* over and over again with slight variations and possibly making a
	14	* mistake somewhere.
	15	*
	16	* Copyright (C) 1998-2003 Hewlett-Packard Co
	17	* David Mosberger-Tang <davidm@hpl.hp.com>
	18	* Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
	19	* Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
	20	*/
	21
8a549f8b JB	22	#include <asm/unaligned.h>
8a549f8b JB	23
1da177e4 LT	24	/* We don't use IO slowdowns on the ia64, but.. */
	25	#define __SLOW_DOWN_IO do { } while (0)
	26	#define SLOW_DOWN_IO do { } while (0)
	27
0a41e250	28	#define __IA64_UNCACHED_OFFSET RGN_BASE(RGN_UNCACHED)
1da177e4 LT	29
	30	/*
	31	* The legacy I/O space defined by the ia64 architecture supports only 65536 ports, but
	32	* large machines may have multiple other I/O spaces so we can't place any a priori limit
	33	* on IO_SPACE_LIMIT. These additional spaces are described in ACPI.
	34	*/
	35	#define IO_SPACE_LIMIT 0xffffffffffffffffUL
	36
8ea6091f	37	#define MAX_IO_SPACES_BITS 8
1da177e4 LT	38	#define MAX_IO_SPACES (1UL << MAX_IO_SPACES_BITS)
	39	#define IO_SPACE_BITS 24
	40	#define IO_SPACE_SIZE (1UL << IO_SPACE_BITS)
	41
	42	#define IO_SPACE_NR(port) ((port) >> IO_SPACE_BITS)
	43	#define IO_SPACE_BASE(space) ((space) << IO_SPACE_BITS)
	44	#define IO_SPACE_PORT(port) ((port) & (IO_SPACE_SIZE - 1))
	45
b5f3616b	46	#define IO_SPACE_SPARSE_ENCODING(p) ((((p) >> 2) << 12) \| ((p) & 0xfff))
1da177e4 LT	47
	48	struct io_space {
	49	unsigned long mmio_base; /* base in MMIO space */
	50	int sparse;
	51	};
	52
	53	extern struct io_space io_space[];
	54	extern unsigned int num_io_spaces;
	55
	56	# ifdef __KERNEL__
	57
	58	/*
	59	* All MMIO iomem cookies are in region 6; anything less is a PIO cookie:
	60	* 0xCxxxxxxxxxxxxxxx MMIO cookie (return from ioremap)
	61	* 0x000000001SPPPPPP PIO cookie (S=space number, P..P=port)
	62	*
	63	* ioread/writeX() uses the leading 1 in PIO cookies (PIO_OFFSET) to catch
	64	* code that uses bare port numbers without the prerequisite pci_iomap().
	65	*/
	66	#define PIO_OFFSET (1UL << (MAX_IO_SPACES_BITS + IO_SPACE_BITS))
	67	#define PIO_MASK (PIO_OFFSET - 1)
	68	#define PIO_RESERVED __IA64_UNCACHED_OFFSET
	69	#define HAVE_ARCH_PIO_SIZE
	70
	71	#include <asm/intrinsics.h>
	72	#include <asm/machvec.h>
	73	#include <asm/page.h>
	74	#include <asm/system.h>
	75	#include <asm-generic/iomap.h>
	76
	77	/*
	78	* Change virtual addresses to physical addresses and vv.
	79	*/
	80	static inline unsigned long
	81	virt_to_phys (volatile void *address)
	82	{
	83	return (unsigned long) address - PAGE_OFFSET;
	84	}
	85
	86	static inline void*
	87	phys_to_virt (unsigned long address)
	88	{
	89	return (void *) (address + PAGE_OFFSET);
	90	}
	91
	92	#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
32e62c63	93	extern u64 kern_mem_attribute (unsigned long phys_addr, unsigned long size);
136939a2	94	extern int valid_phys_addr_range (unsigned long addr, size_t count); /* efi.c */
06c67bef	95	extern int valid_mmap_phys_addr_range (unsigned long pfn, size_t count);
1da177e4 LT	96
	97	/*
	98	* The following two macros are deprecated and scheduled for removal.
	99	* Please use the PCI-DMA interface defined in <asm/pci.h> instead.
	100	*/
	101	#define bus_to_virt phys_to_virt
	102	#define virt_to_bus virt_to_phys
	103	#define page_to_bus page_to_phys
	104
	105	# endif /* KERNEL */
	106
	107	/*
	108	* Memory fence w/accept. This should never be used in code that is
	109	* not IA-64 specific.
	110	*/
	111	#define __ia64_mf_a() ia64_mfa()
	112
	113	/**
	114	* ___ia64_mmiowb - I/O write barrier
	115	*
	116	* Ensure ordering of I/O space writes. This will make sure that writes
	117	* following the barrier will arrive after all previous writes. For most
	118	* ia64 platforms, this is a simple 'mf.a' instruction.
	119	*
	120	* See Documentation/DocBook/deviceiobook.tmpl for more information.
	121	*/
	122	static inline void ___ia64_mmiowb(void)
	123	{
	124	ia64_mfa();
	125	}
	126
1da177e4 LT	127	static inline void*
	128	__ia64_mk_io_addr (unsigned long port)
	129	{
	130	struct io_space *space;
	131	unsigned long offset;
	132
	133	space = &io_space[IO_SPACE_NR(port)];
	134	port = IO_SPACE_PORT(port);
	135	if (space->sparse)
	136	offset = IO_SPACE_SPARSE_ENCODING(port);
	137	else
	138	offset = port;
	139
	140	return (void *) (space->mmio_base \| offset);
	141	}
	142
	143	#define __ia64_inb ___ia64_inb
	144	#define __ia64_inw ___ia64_inw
	145	#define __ia64_inl ___ia64_inl
	146	#define __ia64_outb ___ia64_outb
	147	#define __ia64_outw ___ia64_outw
	148	#define __ia64_outl ___ia64_outl
	149	#define __ia64_readb ___ia64_readb
	150	#define __ia64_readw ___ia64_readw
	151	#define __ia64_readl ___ia64_readl
	152	#define __ia64_readq ___ia64_readq
	153	#define __ia64_readb_relaxed ___ia64_readb
	154	#define __ia64_readw_relaxed ___ia64_readw
	155	#define __ia64_readl_relaxed ___ia64_readl
	156	#define __ia64_readq_relaxed ___ia64_readq
	157	#define __ia64_writeb ___ia64_writeb
	158	#define __ia64_writew ___ia64_writew
	159	#define __ia64_writel ___ia64_writel
	160	#define __ia64_writeq ___ia64_writeq
	161	#define __ia64_mmiowb ___ia64_mmiowb
	162
	163	/*
	164	* For the in/out routines, we need to do "mf.a" _after_ doing the I/O access to ensure
	165	* that the access has completed before executing other I/O accesses. Since we're doing
	166	* the accesses through an uncachable (UC) translation, the CPU will execute them in
	167	* program order. However, we still need to tell the compiler not to shuffle them around
	168	* during optimization, which is why we use "volatile" pointers.
	169	*/
	170
	171	static inline unsigned int
	172	___ia64_inb (unsigned long port)
	173	{
	174	volatile unsigned char *addr = __ia64_mk_io_addr(port);
	175	unsigned char ret;
	176
	177	ret = *addr;
	178	__ia64_mf_a();
	179	return ret;
	180	}
	181
	182	static inline unsigned int
	183	___ia64_inw (unsigned long port)
	184	{
	185	volatile unsigned short *addr = __ia64_mk_io_addr(port);
	186	unsigned short ret;
	187
	188	ret = *addr;
	189	__ia64_mf_a();
	190	return ret;
191	}
192
193	static inline unsigned int
194	___ia64_inl (unsigned long port)
195	{
196	volatile unsigned int *addr = __ia64_mk_io_addr(port);
197	unsigned int ret;
198
199	ret = *addr;
200	__ia64_mf_a();
201	return ret;
202	}
203
204	static inline void
205	___ia64_outb (unsigned char val, unsigned long port)
206	{
207	volatile unsigned char *addr = __ia64_mk_io_addr(port);
208
209	*addr = val;
210	__ia64_mf_a();
211	}
212
213	static inline void
214	___ia64_outw (unsigned short val, unsigned long port)
215	{
216	volatile unsigned short *addr = __ia64_mk_io_addr(port);
217
218	*addr = val;
219	__ia64_mf_a();
220	}
221
222	static inline void
223	___ia64_outl (unsigned int val, unsigned long port)
224	{
225	volatile unsigned int *addr = __ia64_mk_io_addr(port);
226
227	*addr = val;
228	__ia64_mf_a();
229	}
230
231	static inline void
232	__insb (unsigned long port, void *dst, unsigned long count)
233	{
234	unsigned char *dp = dst;
235
236	while (count--)
237	*dp++ = platform_inb(port);
238	}
239
240	static inline void
241	__insw (unsigned long port, void *dst, unsigned long count)
242	{
243	unsigned short *dp = dst;
244
245	while (count--)
8a549f8b	246	put_unaligned(platform_inw(port), dp++);
1da177e4 LT	247	}
	248
	249	static inline void
	250	__insl (unsigned long port, void *dst, unsigned long count)
	251	{
	252	unsigned int *dp = dst;
	253
	254	while (count--)
8a549f8b	255	put_unaligned(platform_inl(port), dp++);
1da177e4 LT	256	}
	257
	258	static inline void
	259	__outsb (unsigned long port, const void *src, unsigned long count)
	260	{
	261	const unsigned char *sp = src;
	262
	263	while (count--)
	264	platform_outb(*sp++, port);
	265	}
	266
	267	static inline void
	268	__outsw (unsigned long port, const void *src, unsigned long count)
	269	{
	270	const unsigned short *sp = src;
	271
	272	while (count--)
8a549f8b	273	platform_outw(get_unaligned(sp++), port);
1da177e4 LT	274	}
	275
	276	static inline void
	277	__outsl (unsigned long port, const void *src, unsigned long count)
	278	{
	279	const unsigned int *sp = src;
	280
	281	while (count--)
8a549f8b	282	platform_outl(get_unaligned(sp++), port);
1da177e4 LT	283	}
	284
	285	/*
	286	* Unfortunately, some platforms are broken and do not follow the IA-64 architecture
	287	* specification regarding legacy I/O support. Thus, we have to make these operations
	288	* platform dependent...
	289	*/
	290	#define __inb platform_inb
	291	#define __inw platform_inw
	292	#define __inl platform_inl
	293	#define __outb platform_outb
	294	#define __outw platform_outw
	295	#define __outl platform_outl
	296	#define __mmiowb platform_mmiowb
	297
	298	#define inb(p) __inb(p)
	299	#define inw(p) __inw(p)
	300	#define inl(p) __inl(p)
	301	#define insb(p,d,c) __insb(p,d,c)
	302	#define insw(p,d,c) __insw(p,d,c)
	303	#define insl(p,d,c) __insl(p,d,c)
	304	#define outb(v,p) __outb(v,p)
	305	#define outw(v,p) __outw(v,p)
	306	#define outl(v,p) __outl(v,p)
	307	#define outsb(p,s,c) __outsb(p,s,c)
	308	#define outsw(p,s,c) __outsw(p,s,c)
	309	#define outsl(p,s,c) __outsl(p,s,c)
	310	#define mmiowb() __mmiowb()
	311
	312	/*
	313	* The address passed to these functions are ioremap()ped already.
	314	*
	315	* We need these to be machine vectors since some platforms don't provide
	316	* DMA coherence via PIO reads (PCI drivers and the spec imply that this is
	317	* a good idea). Writes are ok though for all existing ia64 platforms (and
	318	* hopefully it'll stay that way).
	319	*/
	320	static inline unsigned char
	321	___ia64_readb (const volatile void __iomem *addr)
	322	{
	323	return (volatile unsigned char __force )addr;
	324	}
	325
	326	static inline unsigned short
	327	___ia64_readw (const volatile void __iomem *addr)
	328	{
	329	return (volatile unsigned short __force )addr;
	330	}
	331
	332	static inline unsigned int
	333	___ia64_readl (const volatile void __iomem *addr)
	334	{
	335	return (volatile unsigned int __force ) addr;
	336	}
	337
	338	static inline unsigned long
	339	___ia64_readq (const volatile void __iomem *addr)
	340	{
	341	return (volatile unsigned long __force ) addr;
	342	}
	343
	344	static inline void
	345	__writeb (unsigned char val, volatile void __iomem *addr)
	346	{
347	(volatile unsigned char __force ) addr = val;
348	}
349
350	static inline void
351	__writew (unsigned short val, volatile void __iomem *addr)
352	{
353	(volatile unsigned short __force ) addr = val;
354	}
355
356	static inline void
357	__writel (unsigned int val, volatile void __iomem *addr)
358	{
359	(volatile unsigned int __force ) addr = val;
360	}
361
362	static inline void
363	__writeq (unsigned long val, volatile void __iomem *addr)
364	{
365	(volatile unsigned long __force ) addr = val;
366	}
367
368	#define __readb platform_readb
369	#define __readw platform_readw
370	#define __readl platform_readl
371	#define __readq platform_readq
372	#define __readb_relaxed platform_readb_relaxed
373	#define __readw_relaxed platform_readw_relaxed
374	#define __readl_relaxed platform_readl_relaxed
375	#define __readq_relaxed platform_readq_relaxed
376
377	#define readb(a) __readb((a))
378	#define readw(a) __readw((a))
379	#define readl(a) __readl((a))
380	#define readq(a) __readq((a))
381	#define readb_relaxed(a) __readb_relaxed((a))
382	#define readw_relaxed(a) __readw_relaxed((a))
383	#define readl_relaxed(a) __readl_relaxed((a))
384	#define readq_relaxed(a) __readq_relaxed((a))
385	#define __raw_readb readb
386	#define __raw_readw readw
387	#define __raw_readl readl
388	#define __raw_readq readq
389	#define __raw_readb_relaxed readb_relaxed
390	#define __raw_readw_relaxed readw_relaxed
391	#define __raw_readl_relaxed readl_relaxed
392	#define __raw_readq_relaxed readq_relaxed
393	#define writeb(v,a) __writeb((v), (a))
394	#define writew(v,a) __writew((v), (a))
395	#define writel(v,a) __writel((v), (a))
396	#define writeq(v,a) __writeq((v), (a))
397	#define __raw_writeb writeb
398	#define __raw_writew writew
399	#define __raw_writel writel
400	#define __raw_writeq writeq
401
402	#ifndef inb_p
403	# define inb_p inb
404	#endif
405	#ifndef inw_p
406	# define inw_p inw
407	#endif
408	#ifndef inl_p
409	# define inl_p inl
410	#endif
411
412	#ifndef outb_p
413	# define outb_p outb
414	#endif
415	#ifndef outw_p
416	# define outw_p outw
417	#endif
418	#ifndef outl_p
419	# define outl_p outl
420	#endif
421
ffc45571 AG	422	# ifdef __KERNEL__
ffc45571 AG	423
e9b0a071 BH	424	extern void __iomem * ioremap(unsigned long offset, unsigned long size);
e9b0a071 BH	425	extern void __iomem * ioremap_nocache (unsigned long offset, unsigned long size);
9b50ffb0	426	extern void iounmap (volatile void __iomem *addr);
1da177e4	427
1da177e4 LT	428	/*
	429	* String version of IO memory access ops:
	430	*/
	431	extern void memcpy_fromio(void dst, const volatile void __iomem src, long n);
	432	extern void memcpy_toio(volatile void __iomem dst, const void src, long n);
	433	extern void memset_io(volatile void __iomem *s, int c, long n);
	434
1da177e4 LT	435	# endif /* __KERNEL__ */
	436
	437	/*
	438	* Enabling BIO_VMERGE_BOUNDARY forces us to turn off I/O MMU bypassing. It is said that
	439	* BIO-level virtual merging can give up to 4% performance boost (not verified for ia64).
	440	* On the other hand, we know that I/O MMU bypassing gives ~8% performance improvement on
	441	* SPECweb-like workloads on zx1-based machines. Thus, for now we favor I/O MMU bypassing
	442	* over BIO-level virtual merging.
	443	*/
	444	extern unsigned long ia64_max_iommu_merge_mask;
	445	#if 1
	446	#define BIO_VMERGE_BOUNDARY 0
	447	#else
	448	/*
	449	* It makes no sense at all to have this BIO_VMERGE_BOUNDARY macro here. Should be
	450	* replaced by dma_merge_mask() or something of that sort. Note: the only way
	451	* BIO_VMERGE_BOUNDARY is used is to mask off bits. Effectively, our definition gets
	452	* expanded into:
	453	*
	454	* addr & ((ia64_max_iommu_merge_mask + 1) - 1) == (addr & ia64_max_iommu_vmerge_mask)
	455	*
	456	* which is precisely what we want.
	457	*/
	458	#define BIO_VMERGE_BOUNDARY (ia64_max_iommu_merge_mask + 1)
	459	#endif
	460
	461	#endif /* _ASM_IA64_IO_H */