Commit | Line | Data |
---|---|---|
6b3087c6 | 1 | /* |
96f1050d | 2 | * IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited) |
6b3087c6 | 3 | * |
96f1050d RG |
4 | * Copyright 2007-2009 Analog Devices Inc. |
5 | * Philippe Gerum <rpm@xenomai.org> | |
6b3087c6 | 6 | * |
96f1050d | 7 | * Licensed under the GPL-2. |
6b3087c6 GY |
8 | */ |
9 | ||
10 | #include <linux/module.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/spinlock.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/cache.h> | |
17 | #include <linux/profile.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/mm.h> | |
20 | #include <linux/cpu.h> | |
21 | #include <linux/smp.h> | |
9c199b59 | 22 | #include <linux/cpumask.h> |
6b3087c6 GY |
23 | #include <linux/seq_file.h> |
24 | #include <linux/irq.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
6b3087c6 GY |
26 | #include <asm/atomic.h> |
27 | #include <asm/cacheflush.h> | |
28 | #include <asm/mmu_context.h> | |
29 | #include <asm/pgtable.h> | |
30 | #include <asm/pgalloc.h> | |
31 | #include <asm/processor.h> | |
32 | #include <asm/ptrace.h> | |
33 | #include <asm/cpu.h> | |
1fa9be72 | 34 | #include <asm/time.h> |
6b3087c6 GY |
35 | #include <linux/err.h> |
36 | ||
555487bb GY |
37 | /* |
38 | * Anomaly notes: | |
39 | * 05000120 - we always define corelock as 32-bit integer in L2 | |
40 | */ | |
6b3087c6 GY |
41 | struct corelock_slot corelock __attribute__ ((__section__(".l2.bss"))); |
42 | ||
c6345ab1 SZ |
43 | #ifdef CONFIG_ICACHE_FLUSH_L1 |
44 | unsigned long blackfin_iflush_l1_entry[NR_CPUS]; | |
45 | #endif | |
46 | ||
6b3087c6 GY |
47 | void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb, |
48 | *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb, | |
49 | *init_saved_dcplb_fault_addr_coreb; | |
50 | ||
6b3087c6 GY |
51 | #define BFIN_IPI_RESCHEDULE 0 |
52 | #define BFIN_IPI_CALL_FUNC 1 | |
53 | #define BFIN_IPI_CPU_STOP 2 | |
54 | ||
55 | struct blackfin_flush_data { | |
56 | unsigned long start; | |
57 | unsigned long end; | |
58 | }; | |
59 | ||
60 | void *secondary_stack; | |
61 | ||
62 | ||
63 | struct smp_call_struct { | |
64 | void (*func)(void *info); | |
65 | void *info; | |
66 | int wait; | |
73a40064 | 67 | cpumask_t *waitmask; |
6b3087c6 GY |
68 | }; |
69 | ||
70 | static struct blackfin_flush_data smp_flush_data; | |
71 | ||
72 | static DEFINE_SPINLOCK(stop_lock); | |
73 | ||
74 | struct ipi_message { | |
6b3087c6 GY |
75 | unsigned long type; |
76 | struct smp_call_struct call_struct; | |
77 | }; | |
78 | ||
73a40064 YL |
79 | /* A magic number - stress test shows this is safe for common cases */ |
80 | #define BFIN_IPI_MSGQ_LEN 5 | |
81 | ||
82 | /* Simple FIFO buffer, overflow leads to panic */ | |
6b3087c6 | 83 | struct ipi_message_queue { |
6b3087c6 GY |
84 | spinlock_t lock; |
85 | unsigned long count; | |
73a40064 YL |
86 | unsigned long head; /* head of the queue */ |
87 | struct ipi_message ipi_message[BFIN_IPI_MSGQ_LEN]; | |
6b3087c6 GY |
88 | }; |
89 | ||
90 | static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue); | |
91 | ||
92 | static void ipi_cpu_stop(unsigned int cpu) | |
93 | { | |
94 | spin_lock(&stop_lock); | |
95 | printk(KERN_CRIT "CPU%u: stopping\n", cpu); | |
96 | dump_stack(); | |
97 | spin_unlock(&stop_lock); | |
98 | ||
99 | cpu_clear(cpu, cpu_online_map); | |
100 | ||
101 | local_irq_disable(); | |
102 | ||
103 | while (1) | |
104 | SSYNC(); | |
105 | } | |
106 | ||
107 | static void ipi_flush_icache(void *info) | |
108 | { | |
109 | struct blackfin_flush_data *fdata = info; | |
110 | ||
111 | /* Invalidate the memory holding the bounds of the flushed region. */ | |
5f362c91 MF |
112 | invalidate_dcache_range((unsigned long)fdata, |
113 | (unsigned long)fdata + sizeof(*fdata)); | |
6b3087c6 | 114 | |
5f362c91 | 115 | flush_icache_range(fdata->start, fdata->end); |
6b3087c6 GY |
116 | } |
117 | ||
118 | static void ipi_call_function(unsigned int cpu, struct ipi_message *msg) | |
119 | { | |
120 | int wait; | |
121 | void (*func)(void *info); | |
122 | void *info; | |
123 | func = msg->call_struct.func; | |
124 | info = msg->call_struct.info; | |
125 | wait = msg->call_struct.wait; | |
6b3087c6 | 126 | func(info); |
c9784ebb YL |
127 | if (wait) { |
128 | #ifdef __ARCH_SYNC_CORE_DCACHE | |
129 | /* | |
130 | * 'wait' usually means synchronization between CPUs. | |
131 | * Invalidate D cache in case shared data was changed | |
132 | * by func() to ensure cache coherence. | |
133 | */ | |
134 | resync_core_dcache(); | |
135 | #endif | |
73a40064 YL |
136 | cpu_clear(cpu, *msg->call_struct.waitmask); |
137 | } | |
6b3087c6 GY |
138 | } |
139 | ||
73a40064 YL |
140 | /* Use IRQ_SUPPLE_0 to request reschedule. |
141 | * When returning from interrupt to user space, | |
142 | * there is chance to reschedule */ | |
143 | static irqreturn_t ipi_handler_int0(int irq, void *dev_instance) | |
144 | { | |
145 | unsigned int cpu = smp_processor_id(); | |
146 | ||
147 | platform_clear_ipi(cpu, IRQ_SUPPLE_0); | |
148 | return IRQ_HANDLED; | |
149 | } | |
150 | ||
151 | static irqreturn_t ipi_handler_int1(int irq, void *dev_instance) | |
6b3087c6 | 152 | { |
86f2008b | 153 | struct ipi_message *msg; |
6b3087c6 GY |
154 | struct ipi_message_queue *msg_queue; |
155 | unsigned int cpu = smp_processor_id(); | |
73a40064 | 156 | unsigned long flags; |
6b3087c6 | 157 | |
73a40064 | 158 | platform_clear_ipi(cpu, IRQ_SUPPLE_1); |
6b3087c6 GY |
159 | |
160 | msg_queue = &__get_cpu_var(ipi_msg_queue); | |
6b3087c6 | 161 | |
73a40064 YL |
162 | spin_lock_irqsave(&msg_queue->lock, flags); |
163 | ||
164 | while (msg_queue->count) { | |
165 | msg = &msg_queue->ipi_message[msg_queue->head]; | |
6b3087c6 | 166 | switch (msg->type) { |
184748cc PZ |
167 | case BFIN_IPI_RESCHEDULE: |
168 | scheduler_ipi(); | |
169 | break; | |
6b3087c6 | 170 | case BFIN_IPI_CALL_FUNC: |
73a40064 | 171 | spin_unlock_irqrestore(&msg_queue->lock, flags); |
6b3087c6 | 172 | ipi_call_function(cpu, msg); |
73a40064 | 173 | spin_lock_irqsave(&msg_queue->lock, flags); |
6b3087c6 GY |
174 | break; |
175 | case BFIN_IPI_CPU_STOP: | |
73a40064 | 176 | spin_unlock_irqrestore(&msg_queue->lock, flags); |
6b3087c6 | 177 | ipi_cpu_stop(cpu); |
73a40064 | 178 | spin_lock_irqsave(&msg_queue->lock, flags); |
6b3087c6 GY |
179 | break; |
180 | default: | |
db52ecc2 JP |
181 | printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n", |
182 | cpu, msg->type); | |
6b3087c6 GY |
183 | break; |
184 | } | |
73a40064 YL |
185 | msg_queue->head++; |
186 | msg_queue->head %= BFIN_IPI_MSGQ_LEN; | |
187 | msg_queue->count--; | |
6b3087c6 | 188 | } |
73a40064 | 189 | spin_unlock_irqrestore(&msg_queue->lock, flags); |
6b3087c6 GY |
190 | return IRQ_HANDLED; |
191 | } | |
192 | ||
193 | static void ipi_queue_init(void) | |
194 | { | |
195 | unsigned int cpu; | |
196 | struct ipi_message_queue *msg_queue; | |
197 | for_each_possible_cpu(cpu) { | |
198 | msg_queue = &per_cpu(ipi_msg_queue, cpu); | |
6b3087c6 GY |
199 | spin_lock_init(&msg_queue->lock); |
200 | msg_queue->count = 0; | |
73a40064 | 201 | msg_queue->head = 0; |
6b3087c6 GY |
202 | } |
203 | } | |
204 | ||
73a40064 YL |
205 | static inline void smp_send_message(cpumask_t callmap, unsigned long type, |
206 | void (*func) (void *info), void *info, int wait) | |
6b3087c6 GY |
207 | { |
208 | unsigned int cpu; | |
6b3087c6 GY |
209 | struct ipi_message_queue *msg_queue; |
210 | struct ipi_message *msg; | |
73a40064 YL |
211 | unsigned long flags, next_msg; |
212 | cpumask_t waitmask = callmap; /* waitmask is shared by all cpus */ | |
6b3087c6 GY |
213 | |
214 | for_each_cpu_mask(cpu, callmap) { | |
215 | msg_queue = &per_cpu(ipi_msg_queue, cpu); | |
216 | spin_lock_irqsave(&msg_queue->lock, flags); | |
73a40064 YL |
217 | if (msg_queue->count < BFIN_IPI_MSGQ_LEN) { |
218 | next_msg = (msg_queue->head + msg_queue->count) | |
219 | % BFIN_IPI_MSGQ_LEN; | |
220 | msg = &msg_queue->ipi_message[next_msg]; | |
221 | msg->type = type; | |
222 | if (type == BFIN_IPI_CALL_FUNC) { | |
223 | msg->call_struct.func = func; | |
224 | msg->call_struct.info = info; | |
225 | msg->call_struct.wait = wait; | |
226 | msg->call_struct.waitmask = &waitmask; | |
227 | } | |
228 | msg_queue->count++; | |
229 | } else | |
230 | panic("IPI message queue overflow\n"); | |
6b3087c6 | 231 | spin_unlock_irqrestore(&msg_queue->lock, flags); |
73a40064 | 232 | platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1); |
6b3087c6 | 233 | } |
73a40064 | 234 | |
6b3087c6 | 235 | if (wait) { |
73a40064 | 236 | while (!cpus_empty(waitmask)) |
6b3087c6 | 237 | blackfin_dcache_invalidate_range( |
73a40064 YL |
238 | (unsigned long)(&waitmask), |
239 | (unsigned long)(&waitmask)); | |
c9784ebb YL |
240 | #ifdef __ARCH_SYNC_CORE_DCACHE |
241 | /* | |
242 | * Invalidate D cache in case shared data was changed by | |
243 | * other processors to ensure cache coherence. | |
244 | */ | |
245 | resync_core_dcache(); | |
246 | #endif | |
6b3087c6 | 247 | } |
73a40064 YL |
248 | } |
249 | ||
250 | int smp_call_function(void (*func)(void *info), void *info, int wait) | |
251 | { | |
252 | cpumask_t callmap; | |
253 | ||
567ebfc9 | 254 | preempt_disable(); |
73a40064 YL |
255 | callmap = cpu_online_map; |
256 | cpu_clear(smp_processor_id(), callmap); | |
567ebfc9 SZ |
257 | if (!cpus_empty(callmap)) |
258 | smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait); | |
73a40064 | 259 | |
567ebfc9 | 260 | preempt_enable(); |
73a40064 | 261 | |
6b3087c6 GY |
262 | return 0; |
263 | } | |
264 | EXPORT_SYMBOL_GPL(smp_call_function); | |
265 | ||
266 | int smp_call_function_single(int cpuid, void (*func) (void *info), void *info, | |
267 | int wait) | |
268 | { | |
269 | unsigned int cpu = cpuid; | |
270 | cpumask_t callmap; | |
6b3087c6 GY |
271 | |
272 | if (cpu_is_offline(cpu)) | |
273 | return 0; | |
274 | cpus_clear(callmap); | |
275 | cpu_set(cpu, callmap); | |
276 | ||
73a40064 | 277 | smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait); |
6b3087c6 | 278 | |
6b3087c6 GY |
279 | return 0; |
280 | } | |
281 | EXPORT_SYMBOL_GPL(smp_call_function_single); | |
282 | ||
283 | void smp_send_reschedule(int cpu) | |
284 | { | |
73a40064 | 285 | /* simply trigger an ipi */ |
6b3087c6 GY |
286 | if (cpu_is_offline(cpu)) |
287 | return; | |
73a40064 | 288 | platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); |
6b3087c6 GY |
289 | |
290 | return; | |
291 | } | |
292 | ||
293 | void smp_send_stop(void) | |
294 | { | |
6b3087c6 | 295 | cpumask_t callmap; |
6b3087c6 | 296 | |
567ebfc9 | 297 | preempt_disable(); |
6b3087c6 GY |
298 | callmap = cpu_online_map; |
299 | cpu_clear(smp_processor_id(), callmap); | |
567ebfc9 SZ |
300 | if (!cpus_empty(callmap)) |
301 | smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0); | |
6b3087c6 | 302 | |
567ebfc9 | 303 | preempt_enable(); |
6b3087c6 | 304 | |
6b3087c6 GY |
305 | return; |
306 | } | |
307 | ||
308 | int __cpuinit __cpu_up(unsigned int cpu) | |
309 | { | |
6b3087c6 | 310 | int ret; |
0b39db28 GY |
311 | static struct task_struct *idle; |
312 | ||
313 | if (idle) | |
314 | free_task(idle); | |
6b3087c6 GY |
315 | |
316 | idle = fork_idle(cpu); | |
317 | if (IS_ERR(idle)) { | |
318 | printk(KERN_ERR "CPU%u: fork() failed\n", cpu); | |
319 | return PTR_ERR(idle); | |
320 | } | |
321 | ||
322 | secondary_stack = task_stack_page(idle) + THREAD_SIZE; | |
6b3087c6 GY |
323 | |
324 | ret = platform_boot_secondary(cpu, idle); | |
325 | ||
6b3087c6 GY |
326 | secondary_stack = NULL; |
327 | ||
328 | return ret; | |
329 | } | |
330 | ||
331 | static void __cpuinit setup_secondary(unsigned int cpu) | |
332 | { | |
6b3087c6 GY |
333 | unsigned long ilat; |
334 | ||
335 | bfin_write_IMASK(0); | |
336 | CSYNC(); | |
337 | ilat = bfin_read_ILAT(); | |
338 | CSYNC(); | |
339 | bfin_write_ILAT(ilat); | |
340 | CSYNC(); | |
341 | ||
6b3087c6 GY |
342 | /* Enable interrupt levels IVG7-15. IARs have been already |
343 | * programmed by the boot CPU. */ | |
40059784 | 344 | bfin_irq_flags |= IMASK_IVG15 | |
6b3087c6 GY |
345 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | |
346 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; | |
6b3087c6 GY |
347 | } |
348 | ||
349 | void __cpuinit secondary_start_kernel(void) | |
350 | { | |
351 | unsigned int cpu = smp_processor_id(); | |
352 | struct mm_struct *mm = &init_mm; | |
353 | ||
354 | if (_bfin_swrst & SWRST_DBL_FAULT_B) { | |
355 | printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n"); | |
356 | #ifdef CONFIG_DEBUG_DOUBLEFAULT | |
357 | printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n", | |
358 | (int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb); | |
359 | printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb); | |
360 | printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb); | |
361 | #endif | |
362 | printk(KERN_NOTICE " The instruction at %pF caused a double exception\n", | |
363 | init_retx_coreb); | |
364 | } | |
365 | ||
366 | /* | |
367 | * We want the D-cache to be enabled early, in case the atomic | |
368 | * support code emulates cache coherence (see | |
369 | * __ARCH_SYNC_CORE_DCACHE). | |
370 | */ | |
371 | init_exception_vectors(); | |
372 | ||
6b3087c6 GY |
373 | local_irq_disable(); |
374 | ||
375 | /* Attach the new idle task to the global mm. */ | |
376 | atomic_inc(&mm->mm_users); | |
377 | atomic_inc(&mm->mm_count); | |
378 | current->active_mm = mm; | |
6b3087c6 GY |
379 | |
380 | preempt_disable(); | |
381 | ||
382 | setup_secondary(cpu); | |
383 | ||
578d36f5 YL |
384 | platform_secondary_init(cpu); |
385 | ||
0d152c27 YL |
386 | /* setup local core timer */ |
387 | bfin_local_timer_setup(); | |
388 | ||
6b3087c6 GY |
389 | local_irq_enable(); |
390 | ||
ab61d2ac | 391 | bfin_setup_caches(cpu); |
392 | ||
578d36f5 YL |
393 | /* |
394 | * Calibrate loops per jiffy value. | |
395 | * IRQs need to be enabled here - D-cache can be invalidated | |
396 | * in timer irq handler, so core B can read correct jiffies. | |
397 | */ | |
398 | calibrate_delay(); | |
6b3087c6 GY |
399 | |
400 | cpu_idle(); | |
401 | } | |
402 | ||
403 | void __init smp_prepare_boot_cpu(void) | |
404 | { | |
405 | } | |
406 | ||
407 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
408 | { | |
409 | platform_prepare_cpus(max_cpus); | |
410 | ipi_queue_init(); | |
73a40064 YL |
411 | platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0); |
412 | platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1); | |
6b3087c6 GY |
413 | } |
414 | ||
415 | void __init smp_cpus_done(unsigned int max_cpus) | |
416 | { | |
417 | unsigned long bogosum = 0; | |
418 | unsigned int cpu; | |
419 | ||
420 | for_each_online_cpu(cpu) | |
c70c754f | 421 | bogosum += loops_per_jiffy; |
6b3087c6 GY |
422 | |
423 | printk(KERN_INFO "SMP: Total of %d processors activated " | |
424 | "(%lu.%02lu BogoMIPS).\n", | |
425 | num_online_cpus(), | |
426 | bogosum / (500000/HZ), | |
427 | (bogosum / (5000/HZ)) % 100); | |
428 | } | |
429 | ||
430 | void smp_icache_flush_range_others(unsigned long start, unsigned long end) | |
431 | { | |
432 | smp_flush_data.start = start; | |
433 | smp_flush_data.end = end; | |
434 | ||
0bf3d933 | 435 | if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0)) |
6b3087c6 GY |
436 | printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n"); |
437 | } | |
438 | EXPORT_SYMBOL_GPL(smp_icache_flush_range_others); | |
439 | ||
47e9dedb | 440 | #ifdef __ARCH_SYNC_CORE_ICACHE |
718340f6 | 441 | unsigned long icache_invld_count[NR_CPUS]; |
47e9dedb SZ |
442 | void resync_core_icache(void) |
443 | { | |
444 | unsigned int cpu = get_cpu(); | |
445 | blackfin_invalidate_entire_icache(); | |
718340f6 | 446 | icache_invld_count[cpu]++; |
47e9dedb SZ |
447 | put_cpu(); |
448 | } | |
449 | EXPORT_SYMBOL(resync_core_icache); | |
450 | #endif | |
451 | ||
6b3087c6 | 452 | #ifdef __ARCH_SYNC_CORE_DCACHE |
718340f6 | 453 | unsigned long dcache_invld_count[NR_CPUS]; |
6b3087c6 GY |
454 | unsigned long barrier_mask __attribute__ ((__section__(".l2.bss"))); |
455 | ||
456 | void resync_core_dcache(void) | |
457 | { | |
458 | unsigned int cpu = get_cpu(); | |
459 | blackfin_invalidate_entire_dcache(); | |
718340f6 | 460 | dcache_invld_count[cpu]++; |
6b3087c6 GY |
461 | put_cpu(); |
462 | } | |
463 | EXPORT_SYMBOL(resync_core_dcache); | |
464 | #endif | |
0b39db28 GY |
465 | |
466 | #ifdef CONFIG_HOTPLUG_CPU | |
467 | int __cpuexit __cpu_disable(void) | |
468 | { | |
469 | unsigned int cpu = smp_processor_id(); | |
470 | ||
471 | if (cpu == 0) | |
472 | return -EPERM; | |
473 | ||
474 | set_cpu_online(cpu, false); | |
475 | return 0; | |
476 | } | |
477 | ||
478 | static DECLARE_COMPLETION(cpu_killed); | |
479 | ||
480 | int __cpuexit __cpu_die(unsigned int cpu) | |
481 | { | |
482 | return wait_for_completion_timeout(&cpu_killed, 5000); | |
483 | } | |
484 | ||
485 | void cpu_die(void) | |
486 | { | |
487 | complete(&cpu_killed); | |
488 | ||
489 | atomic_dec(&init_mm.mm_users); | |
490 | atomic_dec(&init_mm.mm_count); | |
491 | ||
492 | local_irq_disable(); | |
493 | platform_cpu_die(); | |
494 | } | |
495 | #endif |