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Merge branches 'pxa-ian' and 'pxa-xm270' into pxa
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / blackfin / kernel / bfin_gpio.c
CommitLineData
1394f032
BW		 1/*
2 * File: arch/blackfin/kernel/bfin_gpio.c
3 * Based on:
4 * Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
5 *
6 * Created:
7 * Description: GPIO Abstraction Layer
8 *
9 * Modified:
a2c8cfef 10 * Copyright 2008 Analog Devices Inc.
1394f032
BW		 11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30/*
d2b11a46 31* Number BF537/6/4 BF561 BF533/2/1 BF549/8/4/2
1394f032 32*
d2b11a46 33* GPIO_0 PF0 PF0 PF0 PA0...PJ13
1394f032
BW		 34* GPIO_1 PF1 PF1 PF1
35* GPIO_2 PF2 PF2 PF2
36* GPIO_3 PF3 PF3 PF3
37* GPIO_4 PF4 PF4 PF4
38* GPIO_5 PF5 PF5 PF5
39* GPIO_6 PF6 PF6 PF6
40* GPIO_7 PF7 PF7 PF7
41* GPIO_8 PF8 PF8 PF8
42* GPIO_9 PF9 PF9 PF9
43* GPIO_10 PF10 PF10 PF10
44* GPIO_11 PF11 PF11 PF11
45* GPIO_12 PF12 PF12 PF12
46* GPIO_13 PF13 PF13 PF13
47* GPIO_14 PF14 PF14 PF14
48* GPIO_15 PF15 PF15 PF15
49* GPIO_16 PG0 PF16
50* GPIO_17 PG1 PF17
51* GPIO_18 PG2 PF18
52* GPIO_19 PG3 PF19
53* GPIO_20 PG4 PF20
54* GPIO_21 PG5 PF21
55* GPIO_22 PG6 PF22
56* GPIO_23 PG7 PF23
57* GPIO_24 PG8 PF24
58* GPIO_25 PG9 PF25
59* GPIO_26 PG10 PF26
60* GPIO_27 PG11 PF27
61* GPIO_28 PG12 PF28
62* GPIO_29 PG13 PF29
63* GPIO_30 PG14 PF30
64* GPIO_31 PG15 PF31
65* GPIO_32 PH0 PF32
66* GPIO_33 PH1 PF33
67* GPIO_34 PH2 PF34
68* GPIO_35 PH3 PF35
69* GPIO_36 PH4 PF36
70* GPIO_37 PH5 PF37
71* GPIO_38 PH6 PF38
72* GPIO_39 PH7 PF39
73* GPIO_40 PH8 PF40
74* GPIO_41 PH9 PF41
75* GPIO_42 PH10 PF42
76* GPIO_43 PH11 PF43
77* GPIO_44 PH12 PF44
78* GPIO_45 PH13 PF45
79* GPIO_46 PH14 PF46
80* GPIO_47 PH15 PF47
81*/
82
168f1212 83#include <linux/delay.h>
1394f032
BW		 84#include <linux/module.h>
85#include <linux/err.h>
1545a111 86#include <linux/proc_fs.h>
1394f032
BW		 87#include <asm/blackfin.h>
88#include <asm/gpio.h>
c58c2140 89#include <asm/portmux.h>
1394f032
BW		 90#include <linux/irq.h>
91
2b39331a
MH		 92#if ANOMALY_05000311 || ANOMALY_05000323
93enum {
94 AWA_data = SYSCR,
95 AWA_data_clear = SYSCR,
96 AWA_data_set = SYSCR,
97 AWA_toggle = SYSCR,
6ed83942
GY		 98 AWA_maska = BFIN_UART_SCR,
99 AWA_maska_clear = BFIN_UART_SCR,
100 AWA_maska_set = BFIN_UART_SCR,
101 AWA_maska_toggle = BFIN_UART_SCR,
102 AWA_maskb = BFIN_UART_GCTL,
103 AWA_maskb_clear = BFIN_UART_GCTL,
104 AWA_maskb_set = BFIN_UART_GCTL,
105 AWA_maskb_toggle = BFIN_UART_GCTL,
2b39331a
MH		 106 AWA_dir = SPORT1_STAT,
107 AWA_polar = SPORT1_STAT,
108 AWA_edge = SPORT1_STAT,
109 AWA_both = SPORT1_STAT,
110#if ANOMALY_05000311
111 AWA_inen = TIMER_ENABLE,
112#elif ANOMALY_05000323
113 AWA_inen = DMA1_1_CONFIG,
114#endif
115};
116 /* Anomaly Workaround */
117#define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name)
118#else
119#define AWA_DUMMY_READ(...) do { } while (0)
120#endif
121
1394f032
BW		 122#ifdef BF533_FAMILY
123static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
124 (struct gpio_port_t *) FIO_FLAG_D,
125};
126#endif
127
59003145 128#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
1394f032
BW		 129static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
130 (struct gpio_port_t *) PORTFIO,
131 (struct gpio_port_t *) PORTGIO,
132 (struct gpio_port_t *) PORTHIO,
133};
134
135static unsigned short *port_fer[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
136 (unsigned short *) PORTF_FER,
137 (unsigned short *) PORTG_FER,
138 (unsigned short *) PORTH_FER,
139};
1394f032
BW		 140#endif
141
59003145
MH		 142#ifdef BF527_FAMILY
143static unsigned short *port_mux[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
144 (unsigned short *) PORTF_MUX,
145 (unsigned short *) PORTG_MUX,
146 (unsigned short *) PORTH_MUX,
147};
148
149static const
150u8 pmux_offset[][16] =
151 {{ 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */
152 { 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */
153 { 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */
154 };
155#endif
156
1394f032
BW		 157#ifdef BF561_FAMILY
158static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
159 (struct gpio_port_t *) FIO0_FLAG_D,
160 (struct gpio_port_t *) FIO1_FLAG_D,
161 (struct gpio_port_t *) FIO2_FLAG_D,
162};
163#endif
164
d2b11a46
MH		 165#ifdef BF548_FAMILY
166static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
167 (struct gpio_port_t *)PORTA_FER,
168 (struct gpio_port_t *)PORTB_FER,
169 (struct gpio_port_t *)PORTC_FER,
170 (struct gpio_port_t *)PORTD_FER,
171 (struct gpio_port_t *)PORTE_FER,
172 (struct gpio_port_t *)PORTF_FER,
173 (struct gpio_port_t *)PORTG_FER,
174 (struct gpio_port_t *)PORTH_FER,
175 (struct gpio_port_t *)PORTI_FER,
176 (struct gpio_port_t *)PORTJ_FER,
177};
178#endif
179
c58c2140 180static unsigned short reserved_gpio_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
fac3cf43 181static unsigned short reserved_peri_map[gpio_bank(MAX_RESOURCES)];
c58c2140 182
8c613623
MH		 183#define RESOURCE_LABEL_SIZE 16
184
fac3cf43 185static struct str_ident {
8c613623 186 char name[RESOURCE_LABEL_SIZE];
fac3cf43 187} str_ident[MAX_RESOURCES];
1394f032 188
cfefe3c6 189#if defined(CONFIG_PM) && !defined(CONFIG_BF54x)
1394f032
BW		 190static unsigned short wakeup_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
191static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS];
192static struct gpio_port_s gpio_bank_saved[gpio_bank(MAX_BLACKFIN_GPIOS)];
193
194#ifdef BF533_FAMILY
195static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB};
196#endif
197
198#ifdef BF537_FAMILY
199static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX};
200#endif
201
59003145
MH		 202#ifdef BF527_FAMILY
203static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB};
204#endif
205
1394f032
BW		 206#ifdef BF561_FAMILY
207static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB};
208#endif
209
210#endif /* CONFIG_PM */
211
d2b11a46 212#if defined(BF548_FAMILY)
a2c8cfef 213inline int check_gpio(unsigned gpio)
d2b11a46
MH		 214{
215 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
216 || gpio == GPIO_PH14 || gpio == GPIO_PH15
217 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15
218 || gpio > MAX_BLACKFIN_GPIOS)
219 return -EINVAL;
220 return 0;
221}
222#else
a2c8cfef 223inline int check_gpio(unsigned gpio)
1394f032 224{
e7613aab 225 if (gpio >= MAX_BLACKFIN_GPIOS)
1394f032
BW		 226 return -EINVAL;
227 return 0;
228}
d2b11a46 229#endif
1394f032 230
acbcd263
MH		 231void gpio_error(unsigned gpio)
232{
233 printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio);
234}
235
c58c2140
MH		 236static void set_label(unsigned short ident, const char *label)
237{
c58c2140 238 if (label && str_ident) {
8c613623 239 strncpy(str_ident[ident].name, label,
c58c2140 240 RESOURCE_LABEL_SIZE);
8c613623 241 str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
c58c2140
MH		 242 }
243}
244
245static char *get_label(unsigned short ident)
246{
247 if (!str_ident)
248 return "UNKNOWN";
249
8c613623 250 return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN");
c58c2140
MH		 251}
252
253static int cmp_label(unsigned short ident, const char *label)
254{
fac3cf43
MH		 255 if (label == NULL) {
256 dump_stack();
257 printk(KERN_ERR "Please provide none-null label\n");
258 }
259
c58c2140 260 if (label && str_ident)
8c613623 261 return strncmp(str_ident[ident].name,
c58c2140
MH		 262 label, strlen(label));
263 else
264 return -EINVAL;
265}
266
59003145 267#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
a2c8cfef 268static void port_setup(unsigned gpio, unsigned short usage)
1394f032 269{
cda6a20b 270 if (!check_gpio(gpio)) {
d2b11a46 271 if (usage == GPIO_USAGE)
cda6a20b 272 *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
d2b11a46 273 else
cda6a20b
MH		 274 *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
275 SSYNC();
276 }
1394f032 277}
d2b11a46 278#elif defined(BF548_FAMILY)
a2c8cfef 279static void port_setup(unsigned gpio, unsigned short usage)
d2b11a46
MH		 280{
281 if (usage == GPIO_USAGE)
282 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
283 else
284 gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
285 SSYNC();
286}
1394f032
BW		 287#else
288# define port_setup(...) do { } while (0)
289#endif
290
c58c2140 291#ifdef BF537_FAMILY
8c613623
MH		 292static struct {
293 unsigned short res;
294 unsigned short offset;
295} port_mux_lut[] = {
296 {.res = P_PPI0_D13, .offset = 11},
297 {.res = P_PPI0_D14, .offset = 11},
298 {.res = P_PPI0_D15, .offset = 11},
299 {.res = P_SPORT1_TFS, .offset = 11},
300 {.res = P_SPORT1_TSCLK, .offset = 11},
301 {.res = P_SPORT1_DTPRI, .offset = 11},
302 {.res = P_PPI0_D10, .offset = 10},
303 {.res = P_PPI0_D11, .offset = 10},
304 {.res = P_PPI0_D12, .offset = 10},
305 {.res = P_SPORT1_RSCLK, .offset = 10},
306 {.res = P_SPORT1_RFS, .offset = 10},
307 {.res = P_SPORT1_DRPRI, .offset = 10},
308 {.res = P_PPI0_D8, .offset = 9},
309 {.res = P_PPI0_D9, .offset = 9},
310 {.res = P_SPORT1_DRSEC, .offset = 9},
311 {.res = P_SPORT1_DTSEC, .offset = 9},
312 {.res = P_TMR2, .offset = 8},
313 {.res = P_PPI0_FS3, .offset = 8},
314 {.res = P_TMR3, .offset = 7},
315 {.res = P_SPI0_SSEL4, .offset = 7},
316 {.res = P_TMR4, .offset = 6},
317 {.res = P_SPI0_SSEL5, .offset = 6},
318 {.res = P_TMR5, .offset = 5},
319 {.res = P_SPI0_SSEL6, .offset = 5},
320 {.res = P_UART1_RX, .offset = 4},
321 {.res = P_UART1_TX, .offset = 4},
322 {.res = P_TMR6, .offset = 4},
323 {.res = P_TMR7, .offset = 4},
324 {.res = P_UART0_RX, .offset = 3},
325 {.res = P_UART0_TX, .offset = 3},
326 {.res = P_DMAR0, .offset = 3},
327 {.res = P_DMAR1, .offset = 3},
328 {.res = P_SPORT0_DTSEC, .offset = 1},
329 {.res = P_SPORT0_DRSEC, .offset = 1},
330 {.res = P_CAN0_RX, .offset = 1},
331 {.res = P_CAN0_TX, .offset = 1},
332 {.res = P_SPI0_SSEL7, .offset = 1},
333 {.res = P_SPORT0_TFS, .offset = 0},
334 {.res = P_SPORT0_DTPRI, .offset = 0},
335 {.res = P_SPI0_SSEL2, .offset = 0},
336 {.res = P_SPI0_SSEL3, .offset = 0},
c58c2140
MH		 337};
338
339static void portmux_setup(unsigned short per, unsigned short function)
340{
8c613623 341 u16 y, offset, muxreg;
c58c2140 342
8c613623
MH		 343 for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) {
344 if (port_mux_lut[y].res == per) {
c58c2140
MH		 345
346 /* SET PORTMUX REG */
347
8c613623 348 offset = port_mux_lut[y].offset;
c58c2140
MH		 349 muxreg = bfin_read_PORT_MUX();
350
d171c233 351 if (offset != 1)
c58c2140 352 muxreg &= ~(1 << offset);
d171c233 353 else
c58c2140 354 muxreg &= ~(3 << 1);
c58c2140
MH		 355
356 muxreg |= (function << offset);
357 bfin_write_PORT_MUX(muxreg);
358 }
359 }
360}
d2b11a46
MH		 361#elif defined(BF548_FAMILY)
362inline void portmux_setup(unsigned short portno, unsigned short function)
363{
364 u32 pmux;
365
366 pmux = gpio_array[gpio_bank(portno)]->port_mux;
367
368 pmux &= ~(0x3 << (2 * gpio_sub_n(portno)));
369 pmux |= (function & 0x3) << (2 * gpio_sub_n(portno));
370
371 gpio_array[gpio_bank(portno)]->port_mux = pmux;
372}
373
374inline u16 get_portmux(unsigned short portno)
375{
376 u32 pmux;
c58c2140 377
d2b11a46
MH		 378 pmux = gpio_array[gpio_bank(portno)]->port_mux;
379
380 return (pmux >> (2 * gpio_sub_n(portno)) & 0x3);
381}
59003145
MH		 382#elif defined(BF527_FAMILY)
383inline void portmux_setup(unsigned short portno, unsigned short function)
384{
385 u16 pmux, ident = P_IDENT(portno);
386 u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
387
388 pmux = *port_mux[gpio_bank(ident)];
389 pmux &= ~(3 << offset);
390 pmux |= (function & 3) << offset;
391 *port_mux[gpio_bank(ident)] = pmux;
392 SSYNC();
393}
c58c2140
MH		 394#else
395# define portmux_setup(...) do { } while (0)
396#endif
1394f032 397
a161bb05 398static int __init bfin_gpio_init(void)
1394f032 399{
c58c2140 400 printk(KERN_INFO "Blackfin GPIO Controller\n");
1394f032
BW		 401
402 return 0;
403}
1394f032
BW		 404arch_initcall(bfin_gpio_init);
405
406
d2b11a46 407#ifndef BF548_FAMILY
1394f032
BW		 408/***********************************************************
409*
410* FUNCTIONS: Blackfin General Purpose Ports Access Functions
411*
412* INPUTS/OUTPUTS:
413* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
414*
415*
416* DESCRIPTION: These functions abstract direct register access
417* to Blackfin processor General Purpose
418* Ports Regsiters
419*
420* CAUTION: These functions do not belong to the GPIO Driver API
421*************************************************************
422* MODIFICATION HISTORY :
423**************************************************************/
424
425/* Set a specific bit */
426
427#define SET_GPIO(name) \
a2c8cfef 428void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
1394f032
BW		 429{ \
430 unsigned long flags; \
1394f032
BW		 431 local_irq_save(flags); \
432 if (arg) \
433 gpio_bankb[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
434 else \
435 gpio_bankb[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
2b39331a 436 AWA_DUMMY_READ(name); \
1394f032
BW		 437 local_irq_restore(flags); \
438} \
439EXPORT_SYMBOL(set_gpio_ ## name);
440
441SET_GPIO(dir)
442SET_GPIO(inen)
443SET_GPIO(polar)
444SET_GPIO(edge)
445SET_GPIO(both)
446
447
2b39331a
MH		 448#if ANOMALY_05000311 || ANOMALY_05000323
449#define SET_GPIO_SC(name) \
a2c8cfef 450void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
2b39331a
MH		 451{ \
452 unsigned long flags; \
2b39331a
MH		 453 local_irq_save(flags); \
454 if (arg) \
455 gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
456 else \
457 gpio_bankb[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
458 AWA_DUMMY_READ(name); \
459 local_irq_restore(flags); \
460} \
461EXPORT_SYMBOL(set_gpio_ ## name);
462#else
1394f032 463#define SET_GPIO_SC(name) \
a2c8cfef 464void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
1394f032 465{ \
1394f032
BW		 466 if (arg) \
467 gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
468 else \
469 gpio_bankb[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
470} \
471EXPORT_SYMBOL(set_gpio_ ## name);
2b39331a 472#endif
1394f032
BW		 473
474SET_GPIO_SC(maska)
475SET_GPIO_SC(maskb)
1394f032 476SET_GPIO_SC(data)
1394f032 477
2b39331a 478#if ANOMALY_05000311 || ANOMALY_05000323
a2c8cfef 479void set_gpio_toggle(unsigned gpio)
1394f032
BW		 480{
481 unsigned long flags;
1394f032
BW		 482 local_irq_save(flags);
483 gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
2b39331a 484 AWA_DUMMY_READ(toggle);
1394f032
BW		 485 local_irq_restore(flags);
486}
487#else
a2c8cfef 488void set_gpio_toggle(unsigned gpio)
1394f032 489{
1394f032
BW		 490 gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
491}
492#endif
493EXPORT_SYMBOL(set_gpio_toggle);
494
495
496/*Set current PORT date (16-bit word)*/
497
2b39331a 498#if ANOMALY_05000311 || ANOMALY_05000323
1394f032 499#define SET_GPIO_P(name) \
a2c8cfef 500void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
1394f032 501{ \
2b39331a
MH		 502 unsigned long flags; \
503 local_irq_save(flags); \
1394f032 504 gpio_bankb[gpio_bank(gpio)]->name = arg; \
2b39331a
MH		 505 AWA_DUMMY_READ(name); \
506 local_irq_restore(flags); \
1394f032
BW		 507} \
508EXPORT_SYMBOL(set_gpiop_ ## name);
2b39331a
MH		 509#else
510#define SET_GPIO_P(name) \
a2c8cfef 511void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
2b39331a
MH		 512{ \
513 gpio_bankb[gpio_bank(gpio)]->name = arg; \
514} \
515EXPORT_SYMBOL(set_gpiop_ ## name);
516#endif
1394f032 517
2b39331a 518SET_GPIO_P(data)
1394f032
BW		 519SET_GPIO_P(dir)
520SET_GPIO_P(inen)
521SET_GPIO_P(polar)
522SET_GPIO_P(edge)
523SET_GPIO_P(both)
524SET_GPIO_P(maska)
525SET_GPIO_P(maskb)
526
1394f032 527/* Get a specific bit */
2b39331a
MH		 528#if ANOMALY_05000311 || ANOMALY_05000323
529#define GET_GPIO(name) \
a2c8cfef 530unsigned short get_gpio_ ## name(unsigned gpio) \
2b39331a
MH		 531{ \
532 unsigned long flags; \
533 unsigned short ret; \
534 local_irq_save(flags); \
535 ret = 0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \
536 AWA_DUMMY_READ(name); \
537 local_irq_restore(flags); \
538 return ret; \
539} \
540EXPORT_SYMBOL(get_gpio_ ## name);
541#else
1394f032 542#define GET_GPIO(name) \
a2c8cfef 543unsigned short get_gpio_ ## name(unsigned gpio) \
1394f032
BW		 544{ \
545 return (0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio))); \
546} \
547EXPORT_SYMBOL(get_gpio_ ## name);
2b39331a 548#endif
1394f032 549
2b39331a 550GET_GPIO(data)
1394f032
BW		 551GET_GPIO(dir)
552GET_GPIO(inen)
553GET_GPIO(polar)
554GET_GPIO(edge)
555GET_GPIO(both)
556GET_GPIO(maska)
557GET_GPIO(maskb)
558
1394f032
BW		 559/*Get current PORT date (16-bit word)*/
560
2b39331a
MH		 561#if ANOMALY_05000311 || ANOMALY_05000323
562#define GET_GPIO_P(name) \
a2c8cfef 563unsigned short get_gpiop_ ## name(unsigned gpio) \
2b39331a
MH		 564{ \
565 unsigned long flags; \
566 unsigned short ret; \
567 local_irq_save(flags); \
568 ret = (gpio_bankb[gpio_bank(gpio)]->name); \
569 AWA_DUMMY_READ(name); \
570 local_irq_restore(flags); \
571 return ret; \
572} \
573EXPORT_SYMBOL(get_gpiop_ ## name);
574#else
1394f032 575#define GET_GPIO_P(name) \
a2c8cfef 576unsigned short get_gpiop_ ## name(unsigned gpio) \
1394f032
BW		 577{ \
578 return (gpio_bankb[gpio_bank(gpio)]->name);\
579} \
580EXPORT_SYMBOL(get_gpiop_ ## name);
2b39331a 581#endif
1394f032 582
2b39331a 583GET_GPIO_P(data)
1394f032
BW		 584GET_GPIO_P(dir)
585GET_GPIO_P(inen)
586GET_GPIO_P(polar)
587GET_GPIO_P(edge)
588GET_GPIO_P(both)
589GET_GPIO_P(maska)
590GET_GPIO_P(maskb)
591
1394f032
BW		 592
593#ifdef CONFIG_PM
594/***********************************************************
595*
596* FUNCTIONS: Blackfin PM Setup API
597*
598* INPUTS/OUTPUTS:
599* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
600* type -
601* PM_WAKE_RISING
602* PM_WAKE_FALLING
603* PM_WAKE_HIGH
604* PM_WAKE_LOW
605* PM_WAKE_BOTH_EDGES
606*
607* DESCRIPTION: Blackfin PM Driver API
608*
609* CAUTION:
610*************************************************************
611* MODIFICATION HISTORY :
612**************************************************************/
a2c8cfef 613int gpio_pm_wakeup_request(unsigned gpio, unsigned char type)
1394f032
BW		 614{
615 unsigned long flags;
616
617 if ((check_gpio(gpio) < 0) || !type)
618 return -EINVAL;
619
620 local_irq_save(flags);
1394f032
BW		 621 wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio);
622 wakeup_flags_map[gpio] = type;
623 local_irq_restore(flags);
624
625 return 0;
626}
627EXPORT_SYMBOL(gpio_pm_wakeup_request);
628
a2c8cfef 629void gpio_pm_wakeup_free(unsigned gpio)
1394f032
BW		 630{
631 unsigned long flags;
632
633 if (check_gpio(gpio) < 0)
634 return;
635
636 local_irq_save(flags);
637
638 wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
639
640 local_irq_restore(flags);
641}
642EXPORT_SYMBOL(gpio_pm_wakeup_free);
643
a2c8cfef 644static int bfin_gpio_wakeup_type(unsigned gpio, unsigned char type)
1394f032
BW		 645{
646 port_setup(gpio, GPIO_USAGE);
647 set_gpio_dir(gpio, 0);
648 set_gpio_inen(gpio, 1);
649
650 if (type & (PM_WAKE_RISING | PM_WAKE_FALLING))
651 set_gpio_edge(gpio, 1);
652 else
653 set_gpio_edge(gpio, 0);
654
655 if ((type & (PM_WAKE_BOTH_EDGES)) == (PM_WAKE_BOTH_EDGES))
656 set_gpio_both(gpio, 1);
657 else
658 set_gpio_both(gpio, 0);
659
660 if ((type & (PM_WAKE_FALLING | PM_WAKE_LOW)))
661 set_gpio_polar(gpio, 1);
662 else
663 set_gpio_polar(gpio, 0);
664
665 SSYNC();
666
667 return 0;
668}
669
cfefe3c6 670u32 bfin_pm_setup(void)
1394f032 671{
1394f032
BW		 672 u16 bank, mask, i, gpio;
673
1f83b8f1 674 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
1394f032
BW		 675 mask = wakeup_map[gpio_bank(i)];
676 bank = gpio_bank(i);
677
678 gpio_bank_saved[bank].maskb = gpio_bankb[bank]->maskb;
679 gpio_bankb[bank]->maskb = 0;
680
681 if (mask) {
682#ifdef BF537_FAMILY
683 gpio_bank_saved[bank].fer = *port_fer[bank];
684#endif
685 gpio_bank_saved[bank].inen = gpio_bankb[bank]->inen;
686 gpio_bank_saved[bank].polar = gpio_bankb[bank]->polar;
687 gpio_bank_saved[bank].dir = gpio_bankb[bank]->dir;
688 gpio_bank_saved[bank].edge = gpio_bankb[bank]->edge;
689 gpio_bank_saved[bank].both = gpio_bankb[bank]->both;
c58c2140
MH		 690 gpio_bank_saved[bank].reserved =
691 reserved_gpio_map[bank];
1394f032
BW		 692
693 gpio = i;
694
695 while (mask) {
cfefe3c6
MH		 696 if ((mask & 1) && (wakeup_flags_map[gpio] !=
697 PM_WAKE_IGNORE)) {
c58c2140 698 reserved_gpio_map[gpio_bank(gpio)] |=
581d62ab
MH		 699 gpio_bit(gpio);
700 bfin_gpio_wakeup_type(gpio,
701 wakeup_flags_map[gpio]);
1394f032
BW		 702 set_gpio_data(gpio, 0); /*Clear*/
703 }
704 gpio++;
705 mask >>= 1;
706 }
707
cfefe3c6 708 bfin_internal_set_wake(sic_iwr_irqs[bank], 1);
1394f032
BW		 709 gpio_bankb[bank]->maskb_set = wakeup_map[gpio_bank(i)];
710 }
711 }
712
2b39331a
MH		 713 AWA_DUMMY_READ(maskb_set);
714
cfefe3c6 715 return 0;
1394f032
BW		 716}
717
cfefe3c6 718void bfin_pm_restore(void)
1394f032
BW		 719{
720 u16 bank, mask, i;
721
1f83b8f1 722 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
1394f032
BW		 723 mask = wakeup_map[gpio_bank(i)];
724 bank = gpio_bank(i);
725
726 if (mask) {
727#ifdef BF537_FAMILY
728 *port_fer[bank] = gpio_bank_saved[bank].fer;
729#endif
730 gpio_bankb[bank]->inen = gpio_bank_saved[bank].inen;
731 gpio_bankb[bank]->dir = gpio_bank_saved[bank].dir;
732 gpio_bankb[bank]->polar = gpio_bank_saved[bank].polar;
733 gpio_bankb[bank]->edge = gpio_bank_saved[bank].edge;
734 gpio_bankb[bank]->both = gpio_bank_saved[bank].both;
581d62ab 735
c58c2140
MH		 736 reserved_gpio_map[bank] =
737 gpio_bank_saved[bank].reserved;
cfefe3c6 738 bfin_internal_set_wake(sic_iwr_irqs[bank], 0);
1394f032
BW		 739 }
740
741 gpio_bankb[bank]->maskb = gpio_bank_saved[bank].maskb;
742 }
2b39331a 743 AWA_DUMMY_READ(maskb);
1394f032
BW		 744}
745
746#endif
fac3cf43
MH		 747#else /* BF548_FAMILY */
748
a2c8cfef 749unsigned short get_gpio_dir(unsigned gpio)
fac3cf43
MH		 750{
751 return (0x01 & (gpio_array[gpio_bank(gpio)]->port_dir_clear >> gpio_sub_n(gpio)));
752}
753EXPORT_SYMBOL(get_gpio_dir);
754
d2b11a46 755#endif /* BF548_FAMILY */
1394f032 756
d2b11a46
MH		 757/***********************************************************
758*
759* FUNCTIONS: Blackfin Peripheral Resource Allocation
760* and PortMux Setup
761*
762* INPUTS/OUTPUTS:
763* per Peripheral Identifier
764* label String
765*
766* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API
767*
768* CAUTION:
769*************************************************************
770* MODIFICATION HISTORY :
771**************************************************************/
772
773#ifdef BF548_FAMILY
774int peripheral_request(unsigned short per, const char *label)
775{
776 unsigned long flags;
777 unsigned short ident = P_IDENT(per);
778
779 /*
780 * Don't cares are pins with only one dedicated function
781 */
c58c2140 782
d2b11a46
MH		 783 if (per & P_DONTCARE)
784 return 0;
785
786 if (!(per & P_DEFINED))
787 return -ENODEV;
788
789 if (check_gpio(ident) < 0)
790 return -EINVAL;
c58c2140 791
d2b11a46
MH		 792 local_irq_save(flags);
793
794 if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
f85c4abd 795 dump_stack();
d2b11a46
MH		 796 printk(KERN_ERR
797 "%s: Peripheral %d is already reserved as GPIO by %s !\n",
b85d858b 798 __func__, ident, get_label(ident));
d2b11a46
MH		 799 local_irq_restore(flags);
800 return -EBUSY;
801 }
802
803 if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
804
805 u16 funct = get_portmux(ident);
806
d171c233
MF		 807 /*
808 * Pin functions like AMC address strobes my
809 * be requested and used by several drivers
810 */
d2b11a46
MH		 811
812 if (!((per & P_MAYSHARE) && (funct == P_FUNCT2MUX(per)))) {
813
d171c233
MF		 814 /*
815 * Allow that the identical pin function can
816 * be requested from the same driver twice
817 */
d2b11a46 818
d171c233
MF		 819 if (cmp_label(ident, label) == 0)
820 goto anyway;
d2b11a46 821
f85c4abd 822 dump_stack();
d2b11a46
MH		 823 printk(KERN_ERR
824 "%s: Peripheral %d function %d is already reserved by %s !\n",
b85d858b 825 __func__, ident, P_FUNCT2MUX(per), get_label(ident));
d2b11a46
MH		 826 local_irq_restore(flags);
827 return -EBUSY;
828 }
829 }
830
d171c233 831 anyway:
d2b11a46
MH		 832 reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
833
834 portmux_setup(ident, P_FUNCT2MUX(per));
835 port_setup(ident, PERIPHERAL_USAGE);
836
837 local_irq_restore(flags);
838 set_label(ident, label);
839
840 return 0;
841}
842EXPORT_SYMBOL(peripheral_request);
843#else
c58c2140
MH		 844
845int peripheral_request(unsigned short per, const char *label)
846{
847 unsigned long flags;
848 unsigned short ident = P_IDENT(per);
849
850 /*
851 * Don't cares are pins with only one dedicated function
852 */
853
854 if (per & P_DONTCARE)
855 return 0;
856
857 if (!(per & P_DEFINED))
858 return -ENODEV;
859
c58c2140
MH		 860 local_irq_save(flags);
861
cda6a20b
MH		 862 if (!check_gpio(ident)) {
863
d171c233
MF		 864 if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
865 dump_stack();
866 printk(KERN_ERR
867 "%s: Peripheral %d is already reserved as GPIO by %s !\n",
b85d858b 868 __func__, ident, get_label(ident));
d171c233
MF		 869 local_irq_restore(flags);
870 return -EBUSY;
871 }
c58c2140 872
cda6a20b
MH		 873 }
874
c58c2140
MH		 875 if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
876
d171c233
MF		 877 /*
878 * Pin functions like AMC address strobes my
879 * be requested and used by several drivers
880 */
c58c2140 881
d171c233 882 if (!(per & P_MAYSHARE)) {
c58c2140 883
d171c233
MF		 884 /*
885 * Allow that the identical pin function can
886 * be requested from the same driver twice
887 */
c58c2140 888
d171c233
MF		 889 if (cmp_label(ident, label) == 0)
890 goto anyway;
c58c2140 891
f85c4abd 892 dump_stack();
c58c2140
MH		 893 printk(KERN_ERR
894 "%s: Peripheral %d function %d is already"
8c613623 895 " reserved by %s !\n",
b85d858b 896 __func__, ident, P_FUNCT2MUX(per),
c58c2140 897 get_label(ident));
c58c2140
MH		 898 local_irq_restore(flags);
899 return -EBUSY;
900 }
901
902 }
903
d171c233 904 anyway:
c58c2140
MH		 905 portmux_setup(per, P_FUNCT2MUX(per));
906
907 port_setup(ident, PERIPHERAL_USAGE);
908
909 reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
910 local_irq_restore(flags);
911 set_label(ident, label);
912
913 return 0;
914}
915EXPORT_SYMBOL(peripheral_request);
d2b11a46 916#endif
c58c2140 917
68179371 918int peripheral_request_list(const unsigned short per[], const char *label)
c58c2140
MH		 919{
920 u16 cnt;
921 int ret;
922
923 for (cnt = 0; per[cnt] != 0; cnt++) {
314c98d5 924
c58c2140 925 ret = peripheral_request(per[cnt], label);
314c98d5
MH		 926
927 if (ret < 0) {
d171c233 928 for ( ; cnt > 0; cnt--)
314c98d5 929 peripheral_free(per[cnt - 1]);
d171c233
MF		 930
931 return ret;
314c98d5 932 }
c58c2140
MH		 933 }
934
935 return 0;
936}
937EXPORT_SYMBOL(peripheral_request_list);
938
939void peripheral_free(unsigned short per)
940{
941 unsigned long flags;
942 unsigned short ident = P_IDENT(per);
943
944 if (per & P_DONTCARE)
945 return;
946
947 if (!(per & P_DEFINED))
948 return;
949
950 if (check_gpio(ident) < 0)
951 return;
952
953 local_irq_save(flags);
954
d171c233 955 if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) {
c58c2140
MH		 956 local_irq_restore(flags);
957 return;
958 }
959
d171c233 960 if (!(per & P_MAYSHARE))
c58c2140 961 port_setup(ident, GPIO_USAGE);
c58c2140
MH		 962
963 reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident);
964
2acde902
MH		 965 set_label(ident, "free");
966
c58c2140
MH		 967 local_irq_restore(flags);
968}
969EXPORT_SYMBOL(peripheral_free);
970
68179371 971void peripheral_free_list(const unsigned short per[])
c58c2140
MH		 972{
973 u16 cnt;
d171c233 974 for (cnt = 0; per[cnt] != 0; cnt++)
c58c2140 975 peripheral_free(per[cnt]);
c58c2140
MH		 976}
977EXPORT_SYMBOL(peripheral_free_list);
978
1394f032
BW		 979/***********************************************************
980*
981* FUNCTIONS: Blackfin GPIO Driver
982*
983* INPUTS/OUTPUTS:
d2b11a46
MH		 984* gpio PIO Number between 0 and MAX_BLACKFIN_GPIOS
985* label String
1394f032
BW		 986*
987* DESCRIPTION: Blackfin GPIO Driver API
988*
989* CAUTION:
990*************************************************************
991* MODIFICATION HISTORY :
992**************************************************************/
993
acbcd263 994int gpio_request(unsigned gpio, const char *label)
1394f032
BW		 995{
996 unsigned long flags;
997
998 if (check_gpio(gpio) < 0)
999 return -EINVAL;
1000
1001 local_irq_save(flags);
1002
2acde902
MH		 1003 /*
1004 * Allow that the identical GPIO can
1005 * be requested from the same driver twice
1006 * Do nothing and return -
1007 */
1008
1009 if (cmp_label(gpio, label) == 0) {
1010 local_irq_restore(flags);
1011 return 0;
1012 }
1013
c58c2140 1014 if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
f85c4abd 1015 dump_stack();
d2b11a46
MH		 1016 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
1017 gpio, get_label(gpio));
d2b11a46
MH		 1018 local_irq_restore(flags);
1019 return -EBUSY;
1020 }
1021 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
f85c4abd 1022 dump_stack();
d2b11a46
MH		 1023 printk(KERN_ERR
1024 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
1025 gpio, get_label(gpio));
1394f032
BW		 1026 local_irq_restore(flags);
1027 return -EBUSY;
1028 }
d2b11a46 1029
c58c2140 1030 reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
1394f032
BW		 1031
1032 local_irq_restore(flags);
1033
1034 port_setup(gpio, GPIO_USAGE);
d2b11a46 1035 set_label(gpio, label);
1394f032
BW		 1036
1037 return 0;
1038}
1039EXPORT_SYMBOL(gpio_request);
1040
acbcd263 1041void gpio_free(unsigned gpio)
1394f032
BW		 1042{
1043 unsigned long flags;
1044
1045 if (check_gpio(gpio) < 0)
1046 return;
1047
1048 local_irq_save(flags);
1049
c58c2140 1050 if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
1394f032 1051 dump_stack();
f85c4abd 1052 gpio_error(gpio);
1394f032
BW		 1053 local_irq_restore(flags);
1054 return;
1055 }
1056
c58c2140 1057 reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
1394f032 1058
2acde902
MH		 1059 set_label(gpio, "free");
1060
1394f032
BW		 1061 local_irq_restore(flags);
1062}
1063EXPORT_SYMBOL(gpio_free);
1064
acbcd263 1065
d2b11a46 1066#ifdef BF548_FAMILY
acbcd263 1067int gpio_direction_input(unsigned gpio)
d2b11a46
MH		 1068{
1069 unsigned long flags;
1070
acbcd263
MH		 1071 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1072 gpio_error(gpio);
1073 return -EINVAL;
1074 }
1075
d2b11a46
MH		 1076 local_irq_save(flags);
1077 gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
1078 gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
1079 local_irq_restore(flags);
acbcd263
MH		 1080
1081 return 0;
d2b11a46
MH		 1082}
1083EXPORT_SYMBOL(gpio_direction_input);
1084
acbcd263 1085int gpio_direction_output(unsigned gpio, int value)
d2b11a46
MH		 1086{
1087 unsigned long flags;
1088
acbcd263
MH		 1089 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1090 gpio_error(gpio);
1091 return -EINVAL;
1092 }
d2b11a46
MH		 1093
1094 local_irq_save(flags);
1095 gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio);
acbcd263 1096 gpio_set_value(gpio, value);
d2b11a46
MH		 1097 gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio);
1098 local_irq_restore(flags);
acbcd263
MH		 1099
1100 return 0;
d2b11a46
MH		 1101}
1102EXPORT_SYMBOL(gpio_direction_output);
1103
acbcd263 1104void gpio_set_value(unsigned gpio, int arg)
d2b11a46
MH		 1105{
1106 if (arg)
1107 gpio_array[gpio_bank(gpio)]->port_set = gpio_bit(gpio);
1108 else
1109 gpio_array[gpio_bank(gpio)]->port_clear = gpio_bit(gpio);
d2b11a46
MH		 1110}
1111EXPORT_SYMBOL(gpio_set_value);
1112
acbcd263 1113int gpio_get_value(unsigned gpio)
d2b11a46
MH		 1114{
1115 return (1 & (gpio_array[gpio_bank(gpio)]->port_data >> gpio_sub_n(gpio)));
1116}
1117EXPORT_SYMBOL(gpio_get_value);
1118
affee2b2
MH		 1119void bfin_gpio_irq_prepare(unsigned gpio)
1120{
1121 unsigned long flags;
1122
1123 port_setup(gpio, GPIO_USAGE);
1124
1125 local_irq_save(flags);
1126 gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
1127 gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
1128 local_irq_restore(flags);
1129}
1130
d2b11a46
MH		 1131#else
1132
803a8d2a
MH		 1133int gpio_get_value(unsigned gpio)
1134{
1135 unsigned long flags;
1136 int ret;
1137
1138 if (unlikely(get_gpio_edge(gpio))) {
1139 local_irq_save(flags);
1140 set_gpio_edge(gpio, 0);
1141 ret = get_gpio_data(gpio);
1142 set_gpio_edge(gpio, 1);
1143 local_irq_restore(flags);
1144
1145 return ret;
1146 } else
1147 return get_gpio_data(gpio);
1148}
1149EXPORT_SYMBOL(gpio_get_value);
1150
1151
acbcd263 1152int gpio_direction_input(unsigned gpio)
1394f032
BW		 1153{
1154 unsigned long flags;
1155
acbcd263
MH		 1156 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1157 gpio_error(gpio);
1158 return -EINVAL;
1159 }
1394f032
BW		 1160
1161 local_irq_save(flags);
1162 gpio_bankb[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
1163 gpio_bankb[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
2b39331a 1164 AWA_DUMMY_READ(inen);
1394f032 1165 local_irq_restore(flags);
acbcd263
MH		 1166
1167 return 0;
1394f032
BW		 1168}
1169EXPORT_SYMBOL(gpio_direction_input);
1170
acbcd263 1171int gpio_direction_output(unsigned gpio, int value)
1394f032
BW		 1172{
1173 unsigned long flags;
1174
acbcd263
MH		 1175 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1176 gpio_error(gpio);
1177 return -EINVAL;
1178 }
1394f032
BW		 1179
1180 local_irq_save(flags);
1181 gpio_bankb[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
a2c8cfef
MH		 1182
1183 if (value)
1184 gpio_bankb[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
1185 else
1186 gpio_bankb[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
1187
1394f032 1188 gpio_bankb[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
2b39331a 1189 AWA_DUMMY_READ(dir);
1394f032 1190 local_irq_restore(flags);
acbcd263
MH		 1191
1192 return 0;
1394f032
BW		 1193}
1194EXPORT_SYMBOL(gpio_direction_output);
168f1212
MF		 1195
1196/* If we are booting from SPI and our board lacks a strong enough pull up,
1197 * the core can reset and execute the bootrom faster than the resistor can
1198 * pull the signal logically high. To work around this (common) error in
1199 * board design, we explicitly set the pin back to GPIO mode, force /CS
1200 * high, and wait for the electrons to do their thing.
1201 *
1202 * This function only makes sense to be called from reset code, but it
1203 * lives here as we need to force all the GPIO states w/out going through
1204 * BUG() checks and such.
1205 */
1206void bfin_gpio_reset_spi0_ssel1(void)
1207{
4d5f4ed3
MH		 1208 u16 gpio = P_IDENT(P_SPI0_SSEL1);
1209
1210 port_setup(gpio, GPIO_USAGE);
1211 gpio_bankb[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
a2c8cfef 1212 AWA_DUMMY_READ(data_set);
168f1212
MF		 1213 udelay(1);
1214}
d2b11a46 1215
affee2b2
MH		 1216void bfin_gpio_irq_prepare(unsigned gpio)
1217{
1218 port_setup(gpio, GPIO_USAGE);
1219}
1220
d2b11a46 1221#endif /*BF548_FAMILY */
1545a111
MF		 1222
1223#if defined(CONFIG_PROC_FS)
1224static int gpio_proc_read(char *buf, char **start, off_t offset,
1225 int len, int *unused_i, void *unused_v)
1226{
1227 int c, outlen = 0;
1228
1229 for (c = 0; c < MAX_RESOURCES; c++) {
1230 if (!check_gpio(c) && (reserved_gpio_map[gpio_bank(c)] & gpio_bit(c)))
fac3cf43 1231 len = sprintf(buf, "GPIO_%d: %s \t\tGPIO %s\n", c,
1545a111
MF		 1232 get_label(c), get_gpio_dir(c) ? "OUTPUT" : "INPUT");
1233 else if (reserved_peri_map[gpio_bank(c)] & gpio_bit(c))
fac3cf43 1234 len = sprintf(buf, "GPIO_%d: %s \t\tPeripheral\n", c, get_label(c));
1545a111
MF		 1235 else
1236 continue;
1237 buf += len;
1238 outlen += len;
1239 }
1240 return outlen;
1241}
1242
1243static __init int gpio_register_proc(void)
1244{
1245 struct proc_dir_entry *proc_gpio;
1246
1247 proc_gpio = create_proc_entry("gpio", S_IRUGO, NULL);
1248 if (proc_gpio)
1249 proc_gpio->read_proc = gpio_proc_read;
1250 return proc_gpio != NULL;
1251}
1545a111
MF		 1252__initcall(gpio_register_proc);
1253#endif
kernel source for telekom puls (alcatel/mediatek)