Commit | Line | Data |
---|---|---|
9e1b9b80 AJ |
1 | config SYMBOL_PREFIX |
2 | string | |
3 | default "_" | |
4 | ||
1394f032 | 5 | config MMU |
bac7d89e | 6 | def_bool n |
1394f032 BW |
7 | |
8 | config FPU | |
bac7d89e | 9 | def_bool n |
1394f032 BW |
10 | |
11 | config RWSEM_GENERIC_SPINLOCK | |
bac7d89e | 12 | def_bool y |
1394f032 BW |
13 | |
14 | config RWSEM_XCHGADD_ALGORITHM | |
bac7d89e | 15 | def_bool n |
1394f032 BW |
16 | |
17 | config BLACKFIN | |
bac7d89e | 18 | def_bool y |
652afdc3 | 19 | select HAVE_ARCH_KGDB |
e8f263df | 20 | select HAVE_ARCH_TRACEHOOK |
1ee76d7e | 21 | select HAVE_FUNCTION_GRAPH_TRACER |
1c873be7 | 22 | select HAVE_FUNCTION_TRACER |
aebfef03 | 23 | select HAVE_FUNCTION_TRACE_MCOUNT_TEST |
ec7748b5 | 24 | select HAVE_IDE |
d86bfb16 BS |
25 | select HAVE_KERNEL_GZIP if RAMKERNEL |
26 | select HAVE_KERNEL_BZIP2 if RAMKERNEL | |
27 | select HAVE_KERNEL_LZMA if RAMKERNEL | |
42d4b839 | 28 | select HAVE_OPROFILE |
a4f0b32c | 29 | select ARCH_WANT_OPTIONAL_GPIOLIB |
1394f032 | 30 | |
ddf9ddac MF |
31 | config GENERIC_CSUM |
32 | def_bool y | |
33 | ||
70f12567 MF |
34 | config GENERIC_BUG |
35 | def_bool y | |
36 | depends on BUG | |
37 | ||
e3defffe | 38 | config ZONE_DMA |
bac7d89e | 39 | def_bool y |
e3defffe | 40 | |
1394f032 | 41 | config GENERIC_FIND_NEXT_BIT |
bac7d89e | 42 | def_bool y |
1394f032 | 43 | |
1394f032 | 44 | config GENERIC_HARDIRQS |
bac7d89e | 45 | def_bool y |
1394f032 BW |
46 | |
47 | config GENERIC_IRQ_PROBE | |
bac7d89e | 48 | def_bool y |
1394f032 | 49 | |
796dada9 MH |
50 | config GENERIC_HARDIRQS_NO__DO_IRQ |
51 | def_bool y | |
52 | ||
b2d1583f | 53 | config GENERIC_GPIO |
bac7d89e | 54 | def_bool y |
1394f032 BW |
55 | |
56 | config FORCE_MAX_ZONEORDER | |
57 | int | |
58 | default "14" | |
59 | ||
60 | config GENERIC_CALIBRATE_DELAY | |
bac7d89e | 61 | def_bool y |
1394f032 | 62 | |
6fa68e7a MF |
63 | config LOCKDEP_SUPPORT |
64 | def_bool y | |
65 | ||
c7b412f4 MF |
66 | config STACKTRACE_SUPPORT |
67 | def_bool y | |
68 | ||
8f86001f MF |
69 | config TRACE_IRQFLAGS_SUPPORT |
70 | def_bool y | |
1394f032 | 71 | |
1394f032 | 72 | source "init/Kconfig" |
dc52ddc0 | 73 | |
1394f032 BW |
74 | source "kernel/Kconfig.preempt" |
75 | ||
dc52ddc0 MH |
76 | source "kernel/Kconfig.freezer" |
77 | ||
1394f032 BW |
78 | menu "Blackfin Processor Options" |
79 | ||
80 | comment "Processor and Board Settings" | |
81 | ||
82 | choice | |
83 | prompt "CPU" | |
84 | default BF533 | |
85 | ||
2f6f4bcd BW |
86 | config BF512 |
87 | bool "BF512" | |
88 | help | |
89 | BF512 Processor Support. | |
90 | ||
91 | config BF514 | |
92 | bool "BF514" | |
93 | help | |
94 | BF514 Processor Support. | |
95 | ||
96 | config BF516 | |
97 | bool "BF516" | |
98 | help | |
99 | BF516 Processor Support. | |
100 | ||
101 | config BF518 | |
102 | bool "BF518" | |
103 | help | |
104 | BF518 Processor Support. | |
105 | ||
59003145 MH |
106 | config BF522 |
107 | bool "BF522" | |
108 | help | |
109 | BF522 Processor Support. | |
110 | ||
1545a111 MF |
111 | config BF523 |
112 | bool "BF523" | |
113 | help | |
114 | BF523 Processor Support. | |
115 | ||
116 | config BF524 | |
117 | bool "BF524" | |
118 | help | |
119 | BF524 Processor Support. | |
120 | ||
59003145 MH |
121 | config BF525 |
122 | bool "BF525" | |
123 | help | |
124 | BF525 Processor Support. | |
125 | ||
1545a111 MF |
126 | config BF526 |
127 | bool "BF526" | |
128 | help | |
129 | BF526 Processor Support. | |
130 | ||
59003145 MH |
131 | config BF527 |
132 | bool "BF527" | |
133 | help | |
134 | BF527 Processor Support. | |
135 | ||
1394f032 BW |
136 | config BF531 |
137 | bool "BF531" | |
138 | help | |
139 | BF531 Processor Support. | |
140 | ||
141 | config BF532 | |
142 | bool "BF532" | |
143 | help | |
144 | BF532 Processor Support. | |
145 | ||
146 | config BF533 | |
147 | bool "BF533" | |
148 | help | |
149 | BF533 Processor Support. | |
150 | ||
151 | config BF534 | |
152 | bool "BF534" | |
153 | help | |
154 | BF534 Processor Support. | |
155 | ||
156 | config BF536 | |
157 | bool "BF536" | |
158 | help | |
159 | BF536 Processor Support. | |
160 | ||
161 | config BF537 | |
162 | bool "BF537" | |
163 | help | |
164 | BF537 Processor Support. | |
165 | ||
dc26aec2 MH |
166 | config BF538 |
167 | bool "BF538" | |
168 | help | |
169 | BF538 Processor Support. | |
170 | ||
171 | config BF539 | |
172 | bool "BF539" | |
173 | help | |
174 | BF539 Processor Support. | |
175 | ||
5df326ac | 176 | config BF542_std |
24a07a12 RH |
177 | bool "BF542" |
178 | help | |
179 | BF542 Processor Support. | |
180 | ||
2f89c063 MF |
181 | config BF542M |
182 | bool "BF542m" | |
183 | help | |
184 | BF542 Processor Support. | |
185 | ||
5df326ac | 186 | config BF544_std |
24a07a12 RH |
187 | bool "BF544" |
188 | help | |
189 | BF544 Processor Support. | |
190 | ||
2f89c063 MF |
191 | config BF544M |
192 | bool "BF544m" | |
193 | help | |
194 | BF544 Processor Support. | |
195 | ||
5df326ac | 196 | config BF547_std |
7c7fd170 MF |
197 | bool "BF547" |
198 | help | |
199 | BF547 Processor Support. | |
200 | ||
2f89c063 MF |
201 | config BF547M |
202 | bool "BF547m" | |
203 | help | |
204 | BF547 Processor Support. | |
205 | ||
5df326ac | 206 | config BF548_std |
24a07a12 RH |
207 | bool "BF548" |
208 | help | |
209 | BF548 Processor Support. | |
210 | ||
2f89c063 MF |
211 | config BF548M |
212 | bool "BF548m" | |
213 | help | |
214 | BF548 Processor Support. | |
215 | ||
5df326ac | 216 | config BF549_std |
24a07a12 RH |
217 | bool "BF549" |
218 | help | |
219 | BF549 Processor Support. | |
220 | ||
2f89c063 MF |
221 | config BF549M |
222 | bool "BF549m" | |
223 | help | |
224 | BF549 Processor Support. | |
225 | ||
1394f032 BW |
226 | config BF561 |
227 | bool "BF561" | |
228 | help | |
cd88b4dc | 229 | BF561 Processor Support. |
1394f032 BW |
230 | |
231 | endchoice | |
232 | ||
46fa5eec GY |
233 | config SMP |
234 | depends on BF561 | |
0d152c27 | 235 | select TICKSOURCE_CORETMR |
46fa5eec GY |
236 | bool "Symmetric multi-processing support" |
237 | ---help--- | |
238 | This enables support for systems with more than one CPU, | |
239 | like the dual core BF561. If you have a system with only one | |
240 | CPU, say N. If you have a system with more than one CPU, say Y. | |
241 | ||
242 | If you don't know what to do here, say N. | |
243 | ||
244 | config NR_CPUS | |
245 | int | |
246 | depends on SMP | |
247 | default 2 if BF561 | |
248 | ||
0b39db28 GY |
249 | config HOTPLUG_CPU |
250 | bool "Support for hot-pluggable CPUs" | |
251 | depends on SMP && HOTPLUG | |
252 | default y | |
253 | ||
46fa5eec GY |
254 | config IRQ_PER_CPU |
255 | bool | |
256 | depends on SMP | |
257 | default y | |
258 | ||
ead9b115 GY |
259 | config HAVE_LEGACY_PER_CPU_AREA |
260 | def_bool y | |
261 | depends on SMP | |
262 | ||
0c0497c2 MF |
263 | config BF_REV_MIN |
264 | int | |
2f89c063 | 265 | default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) |
0c0497c2 | 266 | default 2 if (BF537 || BF536 || BF534) |
2f89c063 | 267 | default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) |
2f6f4bcd | 268 | default 4 if (BF538 || BF539) |
0c0497c2 MF |
269 | |
270 | config BF_REV_MAX | |
271 | int | |
2f89c063 MF |
272 | default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) |
273 | default 3 if (BF537 || BF536 || BF534 || BF54xM) | |
2f6f4bcd | 274 | default 5 if (BF561 || BF538 || BF539) |
0c0497c2 MF |
275 | default 6 if (BF533 || BF532 || BF531) |
276 | ||
1394f032 BW |
277 | choice |
278 | prompt "Silicon Rev" | |
f8b55651 MF |
279 | default BF_REV_0_0 if (BF51x || BF52x) |
280 | default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) | |
2f89c063 | 281 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) |
24a07a12 RH |
282 | |
283 | config BF_REV_0_0 | |
284 | bool "0.0" | |
2f89c063 | 285 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
59003145 MH |
286 | |
287 | config BF_REV_0_1 | |
d07f4380 | 288 | bool "0.1" |
3d15f302 | 289 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
1394f032 BW |
290 | |
291 | config BF_REV_0_2 | |
292 | bool "0.2" | |
2f89c063 | 293 | depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) |
1394f032 BW |
294 | |
295 | config BF_REV_0_3 | |
296 | bool "0.3" | |
2f89c063 | 297 | depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) |
1394f032 BW |
298 | |
299 | config BF_REV_0_4 | |
300 | bool "0.4" | |
dc26aec2 | 301 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 BW |
302 | |
303 | config BF_REV_0_5 | |
304 | bool "0.5" | |
dc26aec2 | 305 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 | 306 | |
49f7253c MF |
307 | config BF_REV_0_6 |
308 | bool "0.6" | |
309 | depends on (BF533 || BF532 || BF531) | |
310 | ||
de3025f4 JZ |
311 | config BF_REV_ANY |
312 | bool "any" | |
313 | ||
314 | config BF_REV_NONE | |
315 | bool "none" | |
316 | ||
1394f032 BW |
317 | endchoice |
318 | ||
24a07a12 RH |
319 | config BF53x |
320 | bool | |
321 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
322 | default y | |
323 | ||
1394f032 BW |
324 | config MEM_GENERIC_BOARD |
325 | bool | |
326 | depends on GENERIC_BOARD | |
327 | default y | |
328 | ||
329 | config MEM_MT48LC64M4A2FB_7E | |
330 | bool | |
331 | depends on (BFIN533_STAMP) | |
332 | default y | |
333 | ||
334 | config MEM_MT48LC16M16A2TG_75 | |
335 | bool | |
336 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
60584344 HK |
337 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \ |
338 | || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \ | |
339 | || BFIN527_BLUETECHNIX_CM) | |
1394f032 BW |
340 | default y |
341 | ||
342 | config MEM_MT48LC32M8A2_75 | |
343 | bool | |
084f9ebf | 344 | depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) |
1394f032 BW |
345 | default y |
346 | ||
347 | config MEM_MT48LC8M32B2B5_7 | |
348 | bool | |
349 | depends on (BFIN561_BLUETECHNIX_CM) | |
350 | default y | |
351 | ||
59003145 MH |
352 | config MEM_MT48LC32M16A2TG_75 |
353 | bool | |
6924dfb0 | 354 | depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP) |
59003145 MH |
355 | default y |
356 | ||
ee48efb5 GY |
357 | config MEM_MT48H32M16LFCJ_75 |
358 | bool | |
359 | depends on (BFIN526_EZBRD) | |
360 | default y | |
361 | ||
2f6f4bcd | 362 | source "arch/blackfin/mach-bf518/Kconfig" |
59003145 | 363 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
364 | source "arch/blackfin/mach-bf533/Kconfig" |
365 | source "arch/blackfin/mach-bf561/Kconfig" | |
366 | source "arch/blackfin/mach-bf537/Kconfig" | |
dc26aec2 | 367 | source "arch/blackfin/mach-bf538/Kconfig" |
24a07a12 | 368 | source "arch/blackfin/mach-bf548/Kconfig" |
1394f032 BW |
369 | |
370 | menu "Board customizations" | |
371 | ||
372 | config CMDLINE_BOOL | |
373 | bool "Default bootloader kernel arguments" | |
374 | ||
375 | config CMDLINE | |
376 | string "Initial kernel command string" | |
377 | depends on CMDLINE_BOOL | |
378 | default "console=ttyBF0,57600" | |
379 | help | |
380 | If you don't have a boot loader capable of passing a command line string | |
381 | to the kernel, you may specify one here. As a minimum, you should specify | |
382 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
383 | ||
5f004c20 MF |
384 | config BOOT_LOAD |
385 | hex "Kernel load address for booting" | |
386 | default "0x1000" | |
387 | range 0x1000 0x20000000 | |
388 | help | |
389 | This option allows you to set the load address of the kernel. | |
390 | This can be useful if you are on a board which has a small amount | |
391 | of memory or you wish to reserve some memory at the beginning of | |
392 | the address space. | |
393 | ||
394 | Note that you need to keep this value above 4k (0x1000) as this | |
395 | memory region is used to capture NULL pointer references as well | |
396 | as some core kernel functions. | |
397 | ||
8cc7117e MH |
398 | config ROM_BASE |
399 | hex "Kernel ROM Base" | |
86249911 | 400 | depends on ROMKERNEL |
d86bfb16 | 401 | default "0x20040040" |
8cc7117e MH |
402 | range 0x20000000 0x20400000 if !(BF54x || BF561) |
403 | range 0x20000000 0x30000000 if (BF54x || BF561) | |
404 | help | |
d86bfb16 BS |
405 | Make sure your ROM base does not include any file-header |
406 | information that is prepended to the kernel. | |
407 | ||
408 | For example, the bootable U-Boot format (created with | |
409 | mkimage) has a 64 byte header (0x40). So while the image | |
410 | you write to flash might start at say 0x20080000, you have | |
411 | to add 0x40 to get the kernel's ROM base as it will come | |
412 | after the header. | |
8cc7117e | 413 | |
f16295e7 | 414 | comment "Clock/PLL Setup" |
1394f032 BW |
415 | |
416 | config CLKIN_HZ | |
2fb6cb41 | 417 | int "Frequency of the crystal on the board in Hz" |
d0cb9b4e | 418 | default "10000000" if BFIN532_IP0X |
1394f032 | 419 | default "11059200" if BFIN533_STAMP |
d0cb9b4e MF |
420 | default "24576000" if PNAV10 |
421 | default "25000000" # most people use this | |
1394f032 | 422 | default "27000000" if BFIN533_EZKIT |
1394f032 | 423 | default "30000000" if BFIN561_EZKIT |
1394f032 BW |
424 | help |
425 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
2fb6cb41 SZ |
426 | Warning: This value should match the crystal on the board. Otherwise, |
427 | peripherals won't work properly. | |
1394f032 | 428 | |
f16295e7 RG |
429 | config BFIN_KERNEL_CLOCK |
430 | bool "Re-program Clocks while Kernel boots?" | |
431 | default n | |
432 | help | |
433 | This option decides if kernel clocks are re-programed from the | |
434 | bootloader settings. If the clocks are not set, the SDRAM settings | |
435 | are also not changed, and the Bootloader does 100% of the hardware | |
436 | configuration. | |
437 | ||
438 | config PLL_BYPASS | |
e4e9a7ad MF |
439 | bool "Bypass PLL" |
440 | depends on BFIN_KERNEL_CLOCK | |
441 | default n | |
f16295e7 RG |
442 | |
443 | config CLKIN_HALF | |
444 | bool "Half Clock In" | |
445 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
446 | default n | |
447 | help | |
448 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
449 | ||
450 | config VCO_MULT | |
451 | int "VCO Multiplier" | |
452 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
453 | range 1 64 | |
454 | default "22" if BFIN533_EZKIT | |
455 | default "45" if BFIN533_STAMP | |
6924dfb0 | 456 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) |
f16295e7 | 457 | default "22" if BFIN533_BLUETECHNIX_CM |
60584344 | 458 | default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
f16295e7 | 459 | default "20" if BFIN561_EZKIT |
2f6f4bcd | 460 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) |
f16295e7 RG |
461 | help |
462 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
463 | PLL Frequency = (Crystal Frequency) * (this setting) | |
464 | ||
465 | choice | |
466 | prompt "Core Clock Divider" | |
467 | depends on BFIN_KERNEL_CLOCK | |
468 | default CCLK_DIV_1 | |
469 | help | |
470 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
471 | Core Frequency = (PLL frequency) / (this setting) | |
472 | ||
473 | config CCLK_DIV_1 | |
474 | bool "1" | |
475 | ||
476 | config CCLK_DIV_2 | |
477 | bool "2" | |
478 | ||
479 | config CCLK_DIV_4 | |
480 | bool "4" | |
481 | ||
482 | config CCLK_DIV_8 | |
483 | bool "8" | |
484 | endchoice | |
485 | ||
486 | config SCLK_DIV | |
487 | int "System Clock Divider" | |
488 | depends on BFIN_KERNEL_CLOCK | |
489 | range 1 15 | |
5f004c20 | 490 | default 5 |
f16295e7 RG |
491 | help |
492 | This sets the frequency of the system clock (including SDRAM or DDR). | |
493 | This can be between 1 and 15 | |
494 | System Clock = (PLL frequency) / (this setting) | |
495 | ||
5f004c20 MF |
496 | choice |
497 | prompt "DDR SDRAM Chip Type" | |
498 | depends on BFIN_KERNEL_CLOCK | |
499 | depends on BF54x | |
500 | default MEM_MT46V32M16_5B | |
501 | ||
502 | config MEM_MT46V32M16_6T | |
503 | bool "MT46V32M16_6T" | |
504 | ||
505 | config MEM_MT46V32M16_5B | |
506 | bool "MT46V32M16_5B" | |
507 | endchoice | |
508 | ||
73feb5c0 MH |
509 | choice |
510 | prompt "DDR/SDRAM Timing" | |
511 | depends on BFIN_KERNEL_CLOCK | |
512 | default BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
513 | help | |
514 | This option allows you to specify Blackfin SDRAM/DDR Timing parameters | |
515 | The calculated SDRAM timing parameters may not be 100% | |
516 | accurate - This option is therefore marked experimental. | |
517 | ||
518 | config BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
519 | bool "Calculate Timings (EXPERIMENTAL)" | |
520 | depends on EXPERIMENTAL | |
521 | ||
522 | config BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
523 | bool "Provide accurate Timings based on target SCLK" | |
524 | help | |
525 | Please consult the Blackfin Hardware Reference Manuals as well | |
526 | as the memory device datasheet. | |
527 | http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram | |
528 | endchoice | |
529 | ||
530 | menu "Memory Init Control" | |
531 | depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
532 | ||
533 | config MEM_DDRCTL0 | |
534 | depends on BF54x | |
535 | hex "DDRCTL0" | |
536 | default 0x0 | |
537 | ||
538 | config MEM_DDRCTL1 | |
539 | depends on BF54x | |
540 | hex "DDRCTL1" | |
541 | default 0x0 | |
542 | ||
543 | config MEM_DDRCTL2 | |
544 | depends on BF54x | |
545 | hex "DDRCTL2" | |
546 | default 0x0 | |
547 | ||
548 | config MEM_EBIU_DDRQUE | |
549 | depends on BF54x | |
550 | hex "DDRQUE" | |
551 | default 0x0 | |
552 | ||
553 | config MEM_SDRRC | |
554 | depends on !BF54x | |
555 | hex "SDRRC" | |
556 | default 0x0 | |
557 | ||
558 | config MEM_SDGCTL | |
559 | depends on !BF54x | |
560 | hex "SDGCTL" | |
561 | default 0x0 | |
562 | endmenu | |
563 | ||
f16295e7 RG |
564 | # |
565 | # Max & Min Speeds for various Chips | |
566 | # | |
567 | config MAX_VCO_HZ | |
568 | int | |
2f6f4bcd BW |
569 | default 400000000 if BF512 |
570 | default 400000000 if BF514 | |
571 | default 400000000 if BF516 | |
572 | default 400000000 if BF518 | |
7b06263b MF |
573 | default 400000000 if BF522 |
574 | default 600000000 if BF523 | |
1545a111 | 575 | default 400000000 if BF524 |
f16295e7 | 576 | default 600000000 if BF525 |
1545a111 | 577 | default 400000000 if BF526 |
f16295e7 RG |
578 | default 600000000 if BF527 |
579 | default 400000000 if BF531 | |
580 | default 400000000 if BF532 | |
581 | default 750000000 if BF533 | |
582 | default 500000000 if BF534 | |
583 | default 400000000 if BF536 | |
584 | default 600000000 if BF537 | |
f72eecb9 RG |
585 | default 533333333 if BF538 |
586 | default 533333333 if BF539 | |
f16295e7 | 587 | default 600000000 if BF542 |
f72eecb9 | 588 | default 533333333 if BF544 |
1545a111 MF |
589 | default 600000000 if BF547 |
590 | default 600000000 if BF548 | |
f72eecb9 | 591 | default 533333333 if BF549 |
f16295e7 RG |
592 | default 600000000 if BF561 |
593 | ||
594 | config MIN_VCO_HZ | |
595 | int | |
596 | default 50000000 | |
597 | ||
598 | config MAX_SCLK_HZ | |
599 | int | |
f72eecb9 | 600 | default 133333333 |
f16295e7 RG |
601 | |
602 | config MIN_SCLK_HZ | |
603 | int | |
604 | default 27000000 | |
605 | ||
606 | comment "Kernel Timer/Scheduler" | |
607 | ||
608 | source kernel/Kconfig.hz | |
609 | ||
8b5f79f9 | 610 | config GENERIC_TIME |
10f03f1a | 611 | def_bool y |
8b5f79f9 VM |
612 | |
613 | config GENERIC_CLOCKEVENTS | |
614 | bool "Generic clock events" | |
8b5f79f9 VM |
615 | default y |
616 | ||
0d152c27 | 617 | menu "Clock event device" |
1fa9be72 | 618 | depends on GENERIC_CLOCKEVENTS |
1fa9be72 | 619 | config TICKSOURCE_GPTMR0 |
0d152c27 YL |
620 | bool "GPTimer0" |
621 | depends on !SMP | |
1fa9be72 | 622 | select BFIN_GPTIMERS |
1fa9be72 GY |
623 | |
624 | config TICKSOURCE_CORETMR | |
0d152c27 YL |
625 | bool "Core timer" |
626 | default y | |
627 | endmenu | |
1fa9be72 | 628 | |
0d152c27 | 629 | menu "Clock souce" |
8b5f79f9 | 630 | depends on GENERIC_CLOCKEVENTS |
0d152c27 YL |
631 | config CYCLES_CLOCKSOURCE |
632 | bool "CYCLES" | |
633 | default y | |
8b5f79f9 | 634 | depends on !BFIN_SCRATCH_REG_CYCLES |
1fa9be72 | 635 | depends on !SMP |
8b5f79f9 VM |
636 | help |
637 | If you say Y here, you will enable support for using the 'cycles' | |
638 | registers as a clock source. Doing so means you will be unable to | |
639 | safely write to the 'cycles' register during runtime. You will | |
640 | still be able to read it (such as for performance monitoring), but | |
641 | writing the registers will most likely crash the kernel. | |
642 | ||
1fa9be72 | 643 | config GPTMR0_CLOCKSOURCE |
0d152c27 | 644 | bool "GPTimer0" |
3aca47c0 | 645 | select BFIN_GPTIMERS |
1fa9be72 | 646 | depends on !TICKSOURCE_GPTMR0 |
0d152c27 | 647 | endmenu |
1fa9be72 | 648 | |
10f03f1a JS |
649 | config ARCH_USES_GETTIMEOFFSET |
650 | depends on !GENERIC_CLOCKEVENTS | |
651 | def_bool y | |
652 | ||
8b5f79f9 VM |
653 | source kernel/time/Kconfig |
654 | ||
5f004c20 | 655 | comment "Misc" |
971d5bc4 | 656 | |
f0b5d12f MF |
657 | choice |
658 | prompt "Blackfin Exception Scratch Register" | |
659 | default BFIN_SCRATCH_REG_RETN | |
660 | help | |
661 | Select the resource to reserve for the Exception handler: | |
662 | - RETN: Non-Maskable Interrupt (NMI) | |
663 | - RETE: Exception Return (JTAG/ICE) | |
664 | - CYCLES: Performance counter | |
665 | ||
666 | If you are unsure, please select "RETN". | |
667 | ||
668 | config BFIN_SCRATCH_REG_RETN | |
669 | bool "RETN" | |
670 | help | |
671 | Use the RETN register in the Blackfin exception handler | |
672 | as a stack scratch register. This means you cannot | |
673 | safely use NMI on the Blackfin while running Linux, but | |
674 | you can debug the system with a JTAG ICE and use the | |
675 | CYCLES performance registers. | |
676 | ||
677 | If you are unsure, please select "RETN". | |
678 | ||
679 | config BFIN_SCRATCH_REG_RETE | |
680 | bool "RETE" | |
681 | help | |
682 | Use the RETE register in the Blackfin exception handler | |
683 | as a stack scratch register. This means you cannot | |
684 | safely use a JTAG ICE while debugging a Blackfin board, | |
685 | but you can safely use the CYCLES performance registers | |
686 | and the NMI. | |
687 | ||
688 | If you are unsure, please select "RETN". | |
689 | ||
690 | config BFIN_SCRATCH_REG_CYCLES | |
691 | bool "CYCLES" | |
692 | help | |
693 | Use the CYCLES register in the Blackfin exception handler | |
694 | as a stack scratch register. This means you cannot | |
695 | safely use the CYCLES performance registers on a Blackfin | |
696 | board at anytime, but you can debug the system with a JTAG | |
697 | ICE and use the NMI. | |
698 | ||
699 | If you are unsure, please select "RETN". | |
700 | ||
701 | endchoice | |
702 | ||
1394f032 BW |
703 | endmenu |
704 | ||
705 | ||
706 | menu "Blackfin Kernel Optimizations" | |
46fa5eec | 707 | depends on !SMP |
1394f032 | 708 | |
1394f032 BW |
709 | comment "Memory Optimizations" |
710 | ||
711 | config I_ENTRY_L1 | |
712 | bool "Locate interrupt entry code in L1 Memory" | |
713 | default y | |
714 | help | |
01dd2fbf ML |
715 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
716 | into L1 instruction memory. (less latency) | |
1394f032 BW |
717 | |
718 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 719 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 BW |
720 | default y |
721 | help | |
01dd2fbf | 722 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
cfefe3c6 | 723 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
01dd2fbf | 724 | (less latency) |
1394f032 BW |
725 | |
726 | config DO_IRQ_L1 | |
727 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
728 | default y | |
729 | help | |
01dd2fbf ML |
730 | If enabled, the frequently called do_irq dispatcher function is linked |
731 | into L1 instruction memory. (less latency) | |
1394f032 BW |
732 | |
733 | config CORE_TIMER_IRQ_L1 | |
734 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
735 | default y | |
736 | help | |
01dd2fbf ML |
737 | If enabled, the frequently called timer_interrupt() function is linked |
738 | into L1 instruction memory. (less latency) | |
1394f032 BW |
739 | |
740 | config IDLE_L1 | |
741 | bool "Locate frequently idle function in L1 Memory" | |
742 | default y | |
743 | help | |
01dd2fbf ML |
744 | If enabled, the frequently called idle function is linked |
745 | into L1 instruction memory. (less latency) | |
1394f032 BW |
746 | |
747 | config SCHEDULE_L1 | |
748 | bool "Locate kernel schedule function in L1 Memory" | |
749 | default y | |
750 | help | |
01dd2fbf ML |
751 | If enabled, the frequently called kernel schedule is linked |
752 | into L1 instruction memory. (less latency) | |
1394f032 BW |
753 | |
754 | config ARITHMETIC_OPS_L1 | |
755 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
756 | default y | |
757 | help | |
01dd2fbf ML |
758 | If enabled, arithmetic functions are linked |
759 | into L1 instruction memory. (less latency) | |
1394f032 BW |
760 | |
761 | config ACCESS_OK_L1 | |
762 | bool "Locate access_ok function in L1 Memory" | |
763 | default y | |
764 | help | |
01dd2fbf ML |
765 | If enabled, the access_ok function is linked |
766 | into L1 instruction memory. (less latency) | |
1394f032 BW |
767 | |
768 | config MEMSET_L1 | |
769 | bool "Locate memset function in L1 Memory" | |
770 | default y | |
771 | help | |
01dd2fbf ML |
772 | If enabled, the memset function is linked |
773 | into L1 instruction memory. (less latency) | |
1394f032 BW |
774 | |
775 | config MEMCPY_L1 | |
776 | bool "Locate memcpy function in L1 Memory" | |
777 | default y | |
778 | help | |
01dd2fbf ML |
779 | If enabled, the memcpy function is linked |
780 | into L1 instruction memory. (less latency) | |
1394f032 | 781 | |
479ba603 RG |
782 | config STRCMP_L1 |
783 | bool "locate strcmp function in L1 Memory" | |
784 | default y | |
785 | help | |
786 | If enabled, the strcmp function is linked | |
787 | into L1 instruction memory (less latency). | |
788 | ||
789 | config STRNCMP_L1 | |
790 | bool "locate strncmp function in L1 Memory" | |
791 | default y | |
792 | help | |
793 | If enabled, the strncmp function is linked | |
794 | into L1 instruction memory (less latency). | |
795 | ||
796 | config STRCPY_L1 | |
797 | bool "locate strcpy function in L1 Memory" | |
798 | default y | |
799 | help | |
800 | If enabled, the strcpy function is linked | |
801 | into L1 instruction memory (less latency). | |
802 | ||
803 | config STRNCPY_L1 | |
804 | bool "locate strncpy function in L1 Memory" | |
805 | default y | |
806 | help | |
807 | If enabled, the strncpy function is linked | |
808 | into L1 instruction memory (less latency). | |
809 | ||
1394f032 BW |
810 | config SYS_BFIN_SPINLOCK_L1 |
811 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
812 | default y | |
813 | help | |
01dd2fbf ML |
814 | If enabled, sys_bfin_spinlock function is linked |
815 | into L1 instruction memory. (less latency) | |
1394f032 BW |
816 | |
817 | config IP_CHECKSUM_L1 | |
818 | bool "Locate IP Checksum function in L1 Memory" | |
819 | default n | |
820 | help | |
01dd2fbf ML |
821 | If enabled, the IP Checksum function is linked |
822 | into L1 instruction memory. (less latency) | |
1394f032 BW |
823 | |
824 | config CACHELINE_ALIGNED_L1 | |
825 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
826 | default y if !BF54x |
827 | default n if BF54x | |
1394f032 BW |
828 | depends on !BF531 |
829 | help | |
692105b8 | 830 | If enabled, cacheline_aligned data is linked |
01dd2fbf | 831 | into L1 data memory. (less latency) |
1394f032 BW |
832 | |
833 | config SYSCALL_TAB_L1 | |
834 | bool "Locate Syscall Table L1 Data Memory" | |
835 | default n | |
836 | depends on !BF531 | |
837 | help | |
01dd2fbf ML |
838 | If enabled, the Syscall LUT is linked |
839 | into L1 data memory. (less latency) | |
1394f032 BW |
840 | |
841 | config CPLB_SWITCH_TAB_L1 | |
842 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
843 | default n | |
844 | depends on !BF531 | |
845 | help | |
01dd2fbf ML |
846 | If enabled, the CPLB Switch Tables are linked |
847 | into L1 data memory. (less latency) | |
1394f032 | 848 | |
ca87b7ad GY |
849 | config APP_STACK_L1 |
850 | bool "Support locating application stack in L1 Scratch Memory" | |
851 | default y | |
852 | help | |
853 | If enabled the application stack can be located in L1 | |
854 | scratch memory (less latency). | |
855 | ||
856 | Currently only works with FLAT binaries. | |
857 | ||
6ad2b84c MF |
858 | config EXCEPTION_L1_SCRATCH |
859 | bool "Locate exception stack in L1 Scratch Memory" | |
860 | default n | |
f82e0a0c | 861 | depends on !APP_STACK_L1 |
6ad2b84c MF |
862 | help |
863 | Whenever an exception occurs, use the L1 Scratch memory for | |
864 | stack storage. You cannot place the stacks of FLAT binaries | |
865 | in L1 when using this option. | |
866 | ||
867 | If you don't use L1 Scratch, then you should say Y here. | |
868 | ||
251383c7 RG |
869 | comment "Speed Optimizations" |
870 | config BFIN_INS_LOWOVERHEAD | |
871 | bool "ins[bwl] low overhead, higher interrupt latency" | |
872 | default y | |
873 | help | |
874 | Reads on the Blackfin are speculative. In Blackfin terms, this means | |
875 | they can be interrupted at any time (even after they have been issued | |
876 | on to the external bus), and re-issued after the interrupt occurs. | |
877 | For memory - this is not a big deal, since memory does not change if | |
878 | it sees a read. | |
879 | ||
880 | If a FIFO is sitting on the end of the read, it will see two reads, | |
881 | when the core only sees one since the FIFO receives both the read | |
882 | which is cancelled (and not delivered to the core) and the one which | |
883 | is re-issued (which is delivered to the core). | |
884 | ||
885 | To solve this, interrupts are turned off before reads occur to | |
886 | I/O space. This option controls which the overhead/latency of | |
887 | controlling interrupts during this time | |
888 | "n" turns interrupts off every read | |
889 | (higher overhead, but lower interrupt latency) | |
890 | "y" turns interrupts off every loop | |
891 | (low overhead, but longer interrupt latency) | |
892 | ||
893 | default behavior is to leave this set to on (type "Y"). If you are experiencing | |
894 | interrupt latency issues, it is safe and OK to turn this off. | |
895 | ||
1394f032 BW |
896 | endmenu |
897 | ||
1394f032 BW |
898 | choice |
899 | prompt "Kernel executes from" | |
900 | help | |
901 | Choose the memory type that the kernel will be running in. | |
902 | ||
903 | config RAMKERNEL | |
904 | bool "RAM" | |
905 | help | |
906 | The kernel will be resident in RAM when running. | |
907 | ||
908 | config ROMKERNEL | |
909 | bool "ROM" | |
910 | help | |
911 | The kernel will be resident in FLASH/ROM when running. | |
912 | ||
913 | endchoice | |
914 | ||
915 | source "mm/Kconfig" | |
916 | ||
780431e3 MF |
917 | config BFIN_GPTIMERS |
918 | tristate "Enable Blackfin General Purpose Timers API" | |
919 | default n | |
920 | help | |
921 | Enable support for the General Purpose Timers API. If you | |
922 | are unsure, say N. | |
923 | ||
924 | To compile this driver as a module, choose M here: the module | |
4737f097 | 925 | will be called gptimers. |
780431e3 | 926 | |
1394f032 | 927 | choice |
d292b000 | 928 | prompt "Uncached DMA region" |
1394f032 | 929 | default DMA_UNCACHED_1M |
86ad7932 CC |
930 | config DMA_UNCACHED_4M |
931 | bool "Enable 4M DMA region" | |
1394f032 BW |
932 | config DMA_UNCACHED_2M |
933 | bool "Enable 2M DMA region" | |
934 | config DMA_UNCACHED_1M | |
935 | bool "Enable 1M DMA region" | |
c45c0659 BS |
936 | config DMA_UNCACHED_512K |
937 | bool "Enable 512K DMA region" | |
938 | config DMA_UNCACHED_256K | |
939 | bool "Enable 256K DMA region" | |
940 | config DMA_UNCACHED_128K | |
941 | bool "Enable 128K DMA region" | |
1394f032 BW |
942 | config DMA_UNCACHED_NONE |
943 | bool "Disable DMA region" | |
944 | endchoice | |
945 | ||
946 | ||
947 | comment "Cache Support" | |
41ba653f | 948 | |
3bebca2d | 949 | config BFIN_ICACHE |
1394f032 | 950 | bool "Enable ICACHE" |
41ba653f | 951 | default y |
41ba653f JZ |
952 | config BFIN_EXTMEM_ICACHEABLE |
953 | bool "Enable ICACHE for external memory" | |
954 | depends on BFIN_ICACHE | |
955 | default y | |
956 | config BFIN_L2_ICACHEABLE | |
957 | bool "Enable ICACHE for L2 SRAM" | |
958 | depends on BFIN_ICACHE | |
959 | depends on BF54x || BF561 | |
960 | default n | |
961 | ||
3bebca2d | 962 | config BFIN_DCACHE |
1394f032 | 963 | bool "Enable DCACHE" |
41ba653f | 964 | default y |
3bebca2d | 965 | config BFIN_DCACHE_BANKA |
1394f032 | 966 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 967 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 968 | default n |
41ba653f JZ |
969 | config BFIN_EXTMEM_DCACHEABLE |
970 | bool "Enable DCACHE for external memory" | |
3bebca2d | 971 | depends on BFIN_DCACHE |
41ba653f JZ |
972 | default y |
973 | choice | |
974 | prompt "External memory DCACHE policy" | |
975 | depends on BFIN_EXTMEM_DCACHEABLE | |
976 | default BFIN_EXTMEM_WRITEBACK if !SMP | |
977 | default BFIN_EXTMEM_WRITETHROUGH if SMP | |
978 | config BFIN_EXTMEM_WRITEBACK | |
1394f032 | 979 | bool "Write back" |
46fa5eec | 980 | depends on !SMP |
1394f032 BW |
981 | help |
982 | Write Back Policy: | |
983 | Cached data will be written back to SDRAM only when needed. | |
984 | This can give a nice increase in performance, but beware of | |
985 | broken drivers that do not properly invalidate/flush their | |
986 | cache. | |
987 | ||
988 | Write Through Policy: | |
989 | Cached data will always be written back to SDRAM when the | |
990 | cache is updated. This is a completely safe setting, but | |
991 | performance is worse than Write Back. | |
992 | ||
993 | If you are unsure of the options and you want to be safe, | |
994 | then go with Write Through. | |
995 | ||
41ba653f | 996 | config BFIN_EXTMEM_WRITETHROUGH |
1394f032 BW |
997 | bool "Write through" |
998 | help | |
999 | Write Back Policy: | |
1000 | Cached data will be written back to SDRAM only when needed. | |
1001 | This can give a nice increase in performance, but beware of | |
1002 | broken drivers that do not properly invalidate/flush their | |
1003 | cache. | |
1004 | ||
1005 | Write Through Policy: | |
1006 | Cached data will always be written back to SDRAM when the | |
1007 | cache is updated. This is a completely safe setting, but | |
1008 | performance is worse than Write Back. | |
1009 | ||
1010 | If you are unsure of the options and you want to be safe, | |
1011 | then go with Write Through. | |
1012 | ||
1013 | endchoice | |
1014 | ||
41ba653f JZ |
1015 | config BFIN_L2_DCACHEABLE |
1016 | bool "Enable DCACHE for L2 SRAM" | |
1017 | depends on BFIN_DCACHE | |
9c954f89 | 1018 | depends on (BF54x || BF561) && !SMP |
41ba653f | 1019 | default n |
5ba76675 | 1020 | choice |
41ba653f JZ |
1021 | prompt "L2 SRAM DCACHE policy" |
1022 | depends on BFIN_L2_DCACHEABLE | |
1023 | default BFIN_L2_WRITEBACK | |
1024 | config BFIN_L2_WRITEBACK | |
5ba76675 | 1025 | bool "Write back" |
5ba76675 | 1026 | |
41ba653f | 1027 | config BFIN_L2_WRITETHROUGH |
5ba76675 | 1028 | bool "Write through" |
5ba76675 | 1029 | endchoice |
f099f39a | 1030 | |
41ba653f JZ |
1031 | |
1032 | comment "Memory Protection Unit" | |
b97b8a99 BS |
1033 | config MPU |
1034 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
1035 | default n | |
1036 | help | |
1037 | Use the processor's MPU to protect applications from accessing | |
1038 | memory they do not own. This comes at a performance penalty | |
1039 | and is recommended only for debugging. | |
1040 | ||
692105b8 | 1041 | comment "Asynchronous Memory Configuration" |
1394f032 | 1042 | |
ddf416b2 | 1043 | menu "EBIU_AMGCTL Global Control" |
1394f032 BW |
1044 | config C_AMCKEN |
1045 | bool "Enable CLKOUT" | |
1046 | default y | |
1047 | ||
1048 | config C_CDPRIO | |
1049 | bool "DMA has priority over core for ext. accesses" | |
1050 | default n | |
1051 | ||
1052 | config C_B0PEN | |
1053 | depends on BF561 | |
1054 | bool "Bank 0 16 bit packing enable" | |
1055 | default y | |
1056 | ||
1057 | config C_B1PEN | |
1058 | depends on BF561 | |
1059 | bool "Bank 1 16 bit packing enable" | |
1060 | default y | |
1061 | ||
1062 | config C_B2PEN | |
1063 | depends on BF561 | |
1064 | bool "Bank 2 16 bit packing enable" | |
1065 | default y | |
1066 | ||
1067 | config C_B3PEN | |
1068 | depends on BF561 | |
1069 | bool "Bank 3 16 bit packing enable" | |
1070 | default n | |
1071 | ||
1072 | choice | |
692105b8 | 1073 | prompt "Enable Asynchronous Memory Banks" |
1394f032 BW |
1074 | default C_AMBEN_ALL |
1075 | ||
1076 | config C_AMBEN | |
1077 | bool "Disable All Banks" | |
1078 | ||
1079 | config C_AMBEN_B0 | |
1080 | bool "Enable Bank 0" | |
1081 | ||
1082 | config C_AMBEN_B0_B1 | |
1083 | bool "Enable Bank 0 & 1" | |
1084 | ||
1085 | config C_AMBEN_B0_B1_B2 | |
1086 | bool "Enable Bank 0 & 1 & 2" | |
1087 | ||
1088 | config C_AMBEN_ALL | |
1089 | bool "Enable All Banks" | |
1090 | endchoice | |
1091 | endmenu | |
1092 | ||
1093 | menu "EBIU_AMBCTL Control" | |
1094 | config BANK_0 | |
c8342f87 | 1095 | hex "Bank 0 (AMBCTL0.L)" |
1394f032 | 1096 | default 0x7BB0 |
c8342f87 MF |
1097 | help |
1098 | These are the low 16 bits of the EBIU_AMBCTL0 MMR which are | |
1099 | used to control the Asynchronous Memory Bank 0 settings. | |
1394f032 BW |
1100 | |
1101 | config BANK_1 | |
c8342f87 | 1102 | hex "Bank 1 (AMBCTL0.H)" |
1394f032 | 1103 | default 0x7BB0 |
197fba56 | 1104 | default 0x5558 if BF54x |
c8342f87 MF |
1105 | help |
1106 | These are the high 16 bits of the EBIU_AMBCTL0 MMR which are | |
1107 | used to control the Asynchronous Memory Bank 1 settings. | |
1394f032 BW |
1108 | |
1109 | config BANK_2 | |
c8342f87 | 1110 | hex "Bank 2 (AMBCTL1.L)" |
1394f032 | 1111 | default 0x7BB0 |
c8342f87 MF |
1112 | help |
1113 | These are the low 16 bits of the EBIU_AMBCTL1 MMR which are | |
1114 | used to control the Asynchronous Memory Bank 2 settings. | |
1394f032 BW |
1115 | |
1116 | config BANK_3 | |
c8342f87 | 1117 | hex "Bank 3 (AMBCTL1.H)" |
1394f032 | 1118 | default 0x99B3 |
c8342f87 MF |
1119 | help |
1120 | These are the high 16 bits of the EBIU_AMBCTL1 MMR which are | |
1121 | used to control the Asynchronous Memory Bank 3 settings. | |
1122 | ||
1394f032 BW |
1123 | endmenu |
1124 | ||
e40540b3 SZ |
1125 | config EBIU_MBSCTLVAL |
1126 | hex "EBIU Bank Select Control Register" | |
1127 | depends on BF54x | |
1128 | default 0 | |
1129 | ||
1130 | config EBIU_MODEVAL | |
1131 | hex "Flash Memory Mode Control Register" | |
1132 | depends on BF54x | |
1133 | default 1 | |
1134 | ||
1135 | config EBIU_FCTLVAL | |
1136 | hex "Flash Memory Bank Control Register" | |
1137 | depends on BF54x | |
1138 | default 6 | |
1394f032 BW |
1139 | endmenu |
1140 | ||
1141 | ############################################################################# | |
1142 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
1143 | ||
1144 | config PCI | |
1145 | bool "PCI support" | |
a95ca3b2 | 1146 | depends on BROKEN |
1394f032 BW |
1147 | help |
1148 | Support for PCI bus. | |
1149 | ||
1150 | source "drivers/pci/Kconfig" | |
1151 | ||
1394f032 BW |
1152 | source "drivers/pcmcia/Kconfig" |
1153 | ||
1154 | source "drivers/pci/hotplug/Kconfig" | |
1155 | ||
1156 | endmenu | |
1157 | ||
1158 | menu "Executable file formats" | |
1159 | ||
1160 | source "fs/Kconfig.binfmt" | |
1161 | ||
1162 | endmenu | |
1163 | ||
1164 | menu "Power management options" | |
ad46163a | 1165 | |
1394f032 BW |
1166 | source "kernel/power/Kconfig" |
1167 | ||
f4cb5700 JB |
1168 | config ARCH_SUSPEND_POSSIBLE |
1169 | def_bool y | |
f4cb5700 | 1170 | |
1394f032 | 1171 | choice |
1efc80b5 | 1172 | prompt "Standby Power Saving Mode" |
1394f032 | 1173 | depends on PM |
cfefe3c6 MH |
1174 | default PM_BFIN_SLEEP_DEEPER |
1175 | config PM_BFIN_SLEEP_DEEPER | |
1176 | bool "Sleep Deeper" | |
1177 | help | |
1178 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic | |
1179 | power dissipation by disabling the clock to the processor core (CCLK). | |
1180 | Furthermore, Standby sets the internal power supply voltage (VDDINT) | |
1181 | to 0.85 V to provide the greatest power savings, while preserving the | |
1182 | processor state. | |
1183 | The PLL and system clock (SCLK) continue to operate at a very low | |
1184 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, | |
1185 | the SDRAM is put into Self Refresh Mode. Typically an external event | |
1186 | such as GPIO interrupt or RTC activity wakes up the processor. | |
1187 | Various Peripherals such as UART, SPORT, PPI may not function as | |
1188 | normal during Sleep Deeper, due to the reduced SCLK frequency. | |
1189 | When in the sleep mode, system DMA access to L1 memory is not supported. | |
1190 | ||
1efc80b5 MH |
1191 | If unsure, select "Sleep Deeper". |
1192 | ||
cfefe3c6 MH |
1193 | config PM_BFIN_SLEEP |
1194 | bool "Sleep" | |
1195 | help | |
1196 | Sleep Mode (High Power Savings) - The sleep mode reduces power | |
1197 | dissipation by disabling the clock to the processor core (CCLK). | |
1198 | The PLL and system clock (SCLK), however, continue to operate in | |
1199 | this mode. Typically an external event or RTC activity will wake | |
1efc80b5 MH |
1200 | up the processor. When in the sleep mode, system DMA access to L1 |
1201 | memory is not supported. | |
1202 | ||
1203 | If unsure, select "Sleep Deeper". | |
cfefe3c6 | 1204 | endchoice |
1394f032 | 1205 | |
1efc80b5 MH |
1206 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
1207 | depends on PM | |
1208 | ||
1efc80b5 MH |
1209 | config PM_BFIN_WAKE_PH6 |
1210 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" | |
2f6f4bcd | 1211 | depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) |
1efc80b5 MH |
1212 | default n |
1213 | help | |
1214 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) | |
1215 | ||
1efc80b5 MH |
1216 | config PM_BFIN_WAKE_GP |
1217 | bool "Allow Wake-Up from GPIOs" | |
1218 | depends on PM && BF54x | |
1219 | default n | |
1220 | help | |
1221 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) | |
19986289 MH |
1222 | (all processors, except ADSP-BF549). This option sets |
1223 | the general-purpose wake-up enable (GPWE) control bit to enable | |
1224 | wake-up upon detection of an active low signal on the /GPW (PH7) pin. | |
1225 | On ADSP-BF549 this option enables the the same functionality on the | |
1226 | /MRXON pin also PH7. | |
1227 | ||
1394f032 BW |
1228 | endmenu |
1229 | ||
1394f032 BW |
1230 | menu "CPU Frequency scaling" |
1231 | ||
1232 | source "drivers/cpufreq/Kconfig" | |
1233 | ||
5ad2ca5f MH |
1234 | config BFIN_CPU_FREQ |
1235 | bool | |
1236 | depends on CPU_FREQ | |
1237 | select CPU_FREQ_TABLE | |
1238 | default y | |
1239 | ||
14b03204 MH |
1240 | config CPU_VOLTAGE |
1241 | bool "CPU Voltage scaling" | |
73feb5c0 | 1242 | depends on EXPERIMENTAL |
14b03204 MH |
1243 | depends on CPU_FREQ |
1244 | default n | |
1245 | help | |
1246 | Say Y here if you want CPU voltage scaling according to the CPU frequency. | |
1247 | This option violates the PLL BYPASS recommendation in the Blackfin Processor | |
73feb5c0 | 1248 | manuals. There is a theoretical risk that during VDDINT transitions |
14b03204 MH |
1249 | the PLL may unlock. |
1250 | ||
1394f032 BW |
1251 | endmenu |
1252 | ||
1394f032 BW |
1253 | source "net/Kconfig" |
1254 | ||
1255 | source "drivers/Kconfig" | |
1256 | ||
872d024b MF |
1257 | source "drivers/firmware/Kconfig" |
1258 | ||
1394f032 BW |
1259 | source "fs/Kconfig" |
1260 | ||
74ce8322 | 1261 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
1262 | |
1263 | source "security/Kconfig" | |
1264 | ||
1265 | source "crypto/Kconfig" | |
1266 | ||
1267 | source "lib/Kconfig" |