Commit | Line | Data |
---|---|---|
60ffc30d CM |
1 | /* |
2 | * Based on arch/arm/include/asm/ptrace.h | |
3 | * | |
4 | * Copyright (C) 1996-2003 Russell King | |
5 | * Copyright (C) 2012 ARM Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #ifndef __ASM_PTRACE_H | |
20 | #define __ASM_PTRACE_H | |
21 | ||
4262a727 | 22 | #include <uapi/asm/ptrace.h> |
60ffc30d | 23 | |
60ffc30d | 24 | /* AArch32-specific ptrace requests */ |
27aa55c5 WD |
25 | #define COMPAT_PTRACE_GETREGS 12 |
26 | #define COMPAT_PTRACE_SETREGS 13 | |
27 | #define COMPAT_PTRACE_GET_THREAD_AREA 22 | |
28 | #define COMPAT_PTRACE_SET_SYSCALL 23 | |
60ffc30d CM |
29 | #define COMPAT_PTRACE_GETVFPREGS 27 |
30 | #define COMPAT_PTRACE_SETVFPREGS 28 | |
27aa55c5 WD |
31 | #define COMPAT_PTRACE_GETHBPREGS 29 |
32 | #define COMPAT_PTRACE_SETHBPREGS 30 | |
9ec218b8 MZ |
33 | |
34 | /* AArch32 CPSR bits */ | |
35 | #define COMPAT_PSR_MODE_MASK 0x0000001f | |
60ffc30d | 36 | #define COMPAT_PSR_MODE_USR 0x00000010 |
9ec218b8 MZ |
37 | #define COMPAT_PSR_MODE_FIQ 0x00000011 |
38 | #define COMPAT_PSR_MODE_IRQ 0x00000012 | |
39 | #define COMPAT_PSR_MODE_SVC 0x00000013 | |
40 | #define COMPAT_PSR_MODE_ABT 0x00000017 | |
41 | #define COMPAT_PSR_MODE_HYP 0x0000001a | |
42 | #define COMPAT_PSR_MODE_UND 0x0000001b | |
43 | #define COMPAT_PSR_MODE_SYS 0x0000001f | |
60ffc30d | 44 | #define COMPAT_PSR_T_BIT 0x00000020 |
10a3cc2f MZ |
45 | #define COMPAT_PSR_F_BIT 0x00000040 |
46 | #define COMPAT_PSR_I_BIT 0x00000080 | |
47 | #define COMPAT_PSR_A_BIT 0x00000100 | |
48 | #define COMPAT_PSR_E_BIT 0x00000200 | |
49 | #define COMPAT_PSR_J_BIT 0x01000000 | |
50 | #define COMPAT_PSR_Q_BIT 0x08000000 | |
51 | #define COMPAT_PSR_V_BIT 0x10000000 | |
52 | #define COMPAT_PSR_C_BIT 0x20000000 | |
53 | #define COMPAT_PSR_Z_BIT 0x40000000 | |
54 | #define COMPAT_PSR_N_BIT 0x80000000 | |
60ffc30d | 55 | #define COMPAT_PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */ |
60ffc30d CM |
56 | /* |
57 | * These are 'magic' values for PTRACE_PEEKUSR that return info about where a | |
58 | * process is located in memory. | |
59 | */ | |
7606c37d CM |
60 | #define COMPAT_PT_TEXT_ADDR 0x10000 |
61 | #define COMPAT_PT_DATA_ADDR 0x10004 | |
62 | #define COMPAT_PT_TEXT_END_ADDR 0x10008 | |
6fa3eb70 S |
63 | |
64 | /* | |
65 | * used to skip a system call when tracer changes its number to -1 | |
66 | * with ptrace(PTRACE_SET_SYSCALL) | |
67 | */ | |
68 | #define RET_SKIP_SYSCALL -1 | |
69 | #define RET_SKIP_SYSCALL_TRACE -2 | |
70 | #define IS_SKIP_SYSCALL(no) ((int)(no & 0xffffffff) == -1) | |
71 | ||
60ffc30d CM |
72 | #ifndef __ASSEMBLY__ |
73 | ||
60ffc30d CM |
74 | /* sizeof(struct user) for AArch32 */ |
75 | #define COMPAT_USER_SZ 296 | |
88483ec6 MZ |
76 | |
77 | /* Architecturally defined mapping between AArch32 and AArch64 registers */ | |
78 | #define compat_usr(x) regs[(x)] | |
60ffc30d | 79 | #define compat_sp regs[13] |
60ffc30d | 80 | #define compat_lr regs[14] |
88483ec6 MZ |
81 | #define compat_sp_hyp regs[15] |
82 | #define compat_sp_irq regs[16] | |
83 | #define compat_lr_irq regs[17] | |
84 | #define compat_sp_svc regs[18] | |
85 | #define compat_lr_svc regs[19] | |
86 | #define compat_sp_abt regs[20] | |
87 | #define compat_lr_abt regs[21] | |
88 | #define compat_sp_und regs[22] | |
89 | #define compat_lr_und regs[23] | |
90 | #define compat_r8_fiq regs[24] | |
91 | #define compat_r9_fiq regs[25] | |
92 | #define compat_r10_fiq regs[26] | |
93 | #define compat_r11_fiq regs[27] | |
94 | #define compat_r12_fiq regs[28] | |
95 | #define compat_sp_fiq regs[29] | |
96 | #define compat_lr_fiq regs[30] | |
60ffc30d CM |
97 | |
98 | /* | |
99 | * This struct defines the way the registers are stored on the stack during an | |
100 | * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for | |
101 | * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs. | |
102 | */ | |
103 | struct pt_regs { | |
104 | union { | |
105 | struct user_pt_regs user_regs; | |
106 | struct { | |
107 | u64 regs[31]; | |
108 | u64 sp; | |
109 | u64 pc; | |
110 | u64 pstate; | |
111 | }; | |
112 | }; | |
113 | u64 orig_x0; | |
114 | u64 syscallno; | |
115 | }; | |
116 | ||
117 | #define arch_has_single_step() (1) | |
118 | ||
119 | #ifdef CONFIG_COMPAT | |
120 | #define compat_thumb_mode(regs) \ | |
121 | (((regs)->pstate & COMPAT_PSR_T_BIT)) | |
122 | #else | |
123 | #define compat_thumb_mode(regs) (0) | |
124 | #endif | |
125 | ||
126 | #define user_mode(regs) \ | |
127 | (((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t) | |
128 | ||
129 | #define compat_user_mode(regs) \ | |
130 | (((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \ | |
131 | (PSR_MODE32_BIT | PSR_MODE_EL0t)) | |
132 | ||
133 | #define processor_mode(regs) \ | |
134 | ((regs)->pstate & PSR_MODE_MASK) | |
135 | ||
136 | #define interrupts_enabled(regs) \ | |
137 | (!((regs)->pstate & PSR_I_BIT)) | |
138 | ||
139 | #define fast_interrupts_enabled(regs) \ | |
140 | (!((regs)->pstate & PSR_F_BIT)) | |
141 | ||
142 | #define user_stack_pointer(regs) \ | |
6fa3eb70 S |
143 | (!compat_user_mode(regs) ? (regs)->sp : (regs)->compat_sp) |
144 | ||
145 | static inline unsigned long regs_return_value(struct pt_regs *regs) | |
146 | { | |
147 | return regs->regs[0]; | |
148 | } | |
60ffc30d CM |
149 | |
150 | /* | |
151 | * Are the current registers suitable for user mode? (used to maintain | |
152 | * security in signal handlers) | |
153 | */ | |
154 | static inline int valid_user_regs(struct user_pt_regs *regs) | |
155 | { | |
156 | if (user_mode(regs) && (regs->pstate & PSR_I_BIT) == 0) { | |
157 | regs->pstate &= ~(PSR_F_BIT | PSR_A_BIT); | |
158 | ||
159 | /* The T bit is reserved for AArch64 */ | |
160 | if (!(regs->pstate & PSR_MODE32_BIT)) | |
161 | regs->pstate &= ~COMPAT_PSR_T_BIT; | |
162 | ||
163 | return 1; | |
164 | } | |
165 | ||
166 | /* | |
167 | * Force PSR to something logical... | |
168 | */ | |
169 | regs->pstate &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | \ | |
170 | COMPAT_PSR_T_BIT | PSR_MODE32_BIT; | |
171 | ||
172 | if (!(regs->pstate & PSR_MODE32_BIT)) { | |
173 | regs->pstate &= ~COMPAT_PSR_T_BIT; | |
174 | regs->pstate |= PSR_MODE_EL0t; | |
175 | } | |
176 | ||
177 | return 0; | |
178 | } | |
179 | ||
6fa3eb70 | 180 | #define instruction_pointer(regs) ((unsigned long)(regs)->pc) |
60ffc30d CM |
181 | |
182 | #ifdef CONFIG_SMP | |
183 | extern unsigned long profile_pc(struct pt_regs *regs); | |
184 | #else | |
185 | #define profile_pc(regs) instruction_pointer(regs) | |
186 | #endif | |
187 | ||
6fa3eb70 S |
188 | /* |
189 | * True if instr is a 32-bit thumb instruction. This works if instr | |
190 | * is the first or only half-word of a thumb instruction. It also works | |
191 | * when instr holds all 32-bits of a wide thumb instruction if stored | |
192 | * in the form (first_half<<16)|(second_half) | |
193 | */ | |
194 | #define is_wide_instruction(instr) ((unsigned)(instr) >= 0xe800) | |
60ffc30d | 195 | |
60ffc30d | 196 | #endif /* __ASSEMBLY__ */ |
60ffc30d | 197 | #endif |