Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/vfp/vfpmodule.c | |
3 | * | |
4 | * Copyright (C) 2004 ARM Limited. | |
5 | * Written by Deep Blue Solutions Limited. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 | 11 | #include <linux/types.h> |
90b44199 | 12 | #include <linux/cpu.h> |
746a9d19 | 13 | #include <linux/cpu_pm.h> |
998de4ac | 14 | #include <linux/hardirq.h> |
1da177e4 | 15 | #include <linux/kernel.h> |
90b44199 | 16 | #include <linux/notifier.h> |
1da177e4 LT |
17 | #include <linux/signal.h> |
18 | #include <linux/sched.h> | |
90b44199 | 19 | #include <linux/smp.h> |
1da177e4 | 20 | #include <linux/init.h> |
2498814f WD |
21 | #include <linux/uaccess.h> |
22 | #include <linux/user.h> | |
d6551e88 | 23 | |
15d07dc9 | 24 | #include <asm/cp15.h> |
5aaf2544 | 25 | #include <asm/cputype.h> |
9f97da78 | 26 | #include <asm/system_info.h> |
d6551e88 | 27 | #include <asm/thread_notify.h> |
1da177e4 LT |
28 | #include <asm/vfp.h> |
29 | ||
30 | #include "vfpinstr.h" | |
31 | #include "vfp.h" | |
32 | ||
33 | /* | |
34 | * Our undef handlers (in entry.S) | |
35 | */ | |
36 | void vfp_testing_entry(void); | |
37 | void vfp_support_entry(void); | |
5d4cae5f | 38 | void vfp_null_entry(void); |
1da177e4 | 39 | |
5d4cae5f | 40 | void (*vfp_vector)(void) = vfp_null_entry; |
af61bdf0 | 41 | |
f8f2a852 RK |
42 | /* |
43 | * Dual-use variable. | |
44 | * Used in startup: set to non-zero if VFP checks fail | |
45 | * After startup, holds VFP architecture | |
46 | */ | |
47 | unsigned int VFP_arch; | |
48 | ||
af61bdf0 RK |
49 | /* |
50 | * The pointer to the vfpstate structure of the thread which currently | |
51 | * owns the context held in the VFP hardware, or NULL if the hardware | |
52 | * context is invalid. | |
f8f2a852 RK |
53 | * |
54 | * For UP, this is sufficient to tell which thread owns the VFP context. | |
55 | * However, for SMP, we also need to check the CPU number stored in the | |
56 | * saved state too to catch migrations. | |
af61bdf0 RK |
57 | */ |
58 | union vfp_state *vfp_current_hw_state[NR_CPUS]; | |
1da177e4 LT |
59 | |
60 | /* | |
f8f2a852 RK |
61 | * Is 'thread's most up to date state stored in this CPUs hardware? |
62 | * Must be called from non-preemptible context. | |
1da177e4 | 63 | */ |
f8f2a852 RK |
64 | static bool vfp_state_in_hw(unsigned int cpu, struct thread_info *thread) |
65 | { | |
66 | #ifdef CONFIG_SMP | |
67 | if (thread->vfpstate.hard.cpu != cpu) | |
68 | return false; | |
69 | #endif | |
70 | return vfp_current_hw_state[cpu] == &thread->vfpstate; | |
71 | } | |
72 | ||
73 | /* | |
74 | * Force a reload of the VFP context from the thread structure. We do | |
75 | * this by ensuring that access to the VFP hardware is disabled, and | |
48af9fea | 76 | * clear vfp_current_hw_state. Must be called from non-preemptible context. |
f8f2a852 RK |
77 | */ |
78 | static void vfp_force_reload(unsigned int cpu, struct thread_info *thread) | |
79 | { | |
80 | if (vfp_state_in_hw(cpu, thread)) { | |
6fa3eb70 | 81 | #ifndef CONFIG_VFP_OPT |
f8f2a852 | 82 | fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); |
6fa3eb70 | 83 | #endif |
f8f2a852 RK |
84 | vfp_current_hw_state[cpu] = NULL; |
85 | } | |
86 | #ifdef CONFIG_SMP | |
87 | thread->vfpstate.hard.cpu = NR_CPUS; | |
88 | #endif | |
89 | } | |
1da177e4 | 90 | |
0d782dc4 RK |
91 | /* |
92 | * Per-thread VFP initialization. | |
93 | */ | |
94 | static void vfp_thread_flush(struct thread_info *thread) | |
95 | { | |
96 | union vfp_state *vfp = &thread->vfpstate; | |
97 | unsigned int cpu; | |
98 | ||
0d782dc4 RK |
99 | /* |
100 | * Disable VFP to ensure we initialize it first. We must ensure | |
19dad35f RK |
101 | * that the modification of vfp_current_hw_state[] and hardware |
102 | * disable are done for the same CPU and without preemption. | |
103 | * | |
104 | * Do this first to ensure that preemption won't overwrite our | |
105 | * state saving should access to the VFP be enabled at this point. | |
0d782dc4 RK |
106 | */ |
107 | cpu = get_cpu(); | |
af61bdf0 RK |
108 | if (vfp_current_hw_state[cpu] == vfp) |
109 | vfp_current_hw_state[cpu] = NULL; | |
6fa3eb70 | 110 | #ifndef CONFIG_VFP_OPT |
0d782dc4 | 111 | fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); |
6fa3eb70 | 112 | #endif |
0d782dc4 | 113 | put_cpu(); |
19dad35f RK |
114 | |
115 | memset(vfp, 0, sizeof(union vfp_state)); | |
116 | ||
117 | vfp->hard.fpexc = FPEXC_EN; | |
118 | vfp->hard.fpscr = FPSCR_ROUND_NEAREST; | |
119 | #ifdef CONFIG_SMP | |
120 | vfp->hard.cpu = NR_CPUS; | |
121 | #endif | |
0d782dc4 RK |
122 | } |
123 | ||
797245f5 | 124 | static void vfp_thread_exit(struct thread_info *thread) |
0d782dc4 RK |
125 | { |
126 | /* release case: Per-thread VFP cleanup. */ | |
127 | union vfp_state *vfp = &thread->vfpstate; | |
797245f5 | 128 | unsigned int cpu = get_cpu(); |
0d782dc4 | 129 | |
af61bdf0 RK |
130 | if (vfp_current_hw_state[cpu] == vfp) |
131 | vfp_current_hw_state[cpu] = NULL; | |
797245f5 | 132 | put_cpu(); |
0d782dc4 RK |
133 | } |
134 | ||
c98c0977 CM |
135 | static void vfp_thread_copy(struct thread_info *thread) |
136 | { | |
137 | struct thread_info *parent = current_thread_info(); | |
138 | ||
139 | vfp_sync_hwstate(parent); | |
140 | thread->vfpstate = parent->vfpstate; | |
f8f2a852 RK |
141 | #ifdef CONFIG_SMP |
142 | thread->vfpstate.hard.cpu = NR_CPUS; | |
143 | #endif | |
c98c0977 CM |
144 | } |
145 | ||
0d782dc4 RK |
146 | /* |
147 | * When this function is called with the following 'cmd's, the following | |
148 | * is true while this function is being run: | |
149 | * THREAD_NOFTIFY_SWTICH: | |
150 | * - the previously running thread will not be scheduled onto another CPU. | |
151 | * - the next thread to be run (v) will not be running on another CPU. | |
152 | * - thread->cpu is the local CPU number | |
153 | * - not preemptible as we're called in the middle of a thread switch | |
154 | * THREAD_NOTIFY_FLUSH: | |
155 | * - the thread (v) will be running on the local CPU, so | |
156 | * v === current_thread_info() | |
157 | * - thread->cpu is the local CPU number at the time it is accessed, | |
158 | * but may change at any time. | |
159 | * - we could be preempted if tree preempt rcu is enabled, so | |
160 | * it is unsafe to use thread->cpu. | |
797245f5 RK |
161 | * THREAD_NOTIFY_EXIT |
162 | * - the thread (v) will be running on the local CPU, so | |
163 | * v === current_thread_info() | |
164 | * - thread->cpu is the local CPU number at the time it is accessed, | |
165 | * but may change at any time. | |
166 | * - we could be preempted if tree preempt rcu is enabled, so | |
167 | * it is unsafe to use thread->cpu. | |
0d782dc4 | 168 | */ |
d6551e88 | 169 | static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v) |
1da177e4 | 170 | { |
d6551e88 | 171 | struct thread_info *thread = v; |
2e82669a | 172 | u32 fpexc; |
6fa3eb70 | 173 | #ifndef CONFIG_VFP_OPT |
2e82669a CM |
174 | #ifdef CONFIG_SMP |
175 | unsigned int cpu; | |
176 | #endif | |
6fa3eb70 | 177 | #endif |
2e82669a CM |
178 | switch (cmd) { |
179 | case THREAD_NOTIFY_SWITCH: | |
180 | fpexc = fmrx(FPEXC); | |
6fa3eb70 | 181 | #ifndef CONFIG_VFP_OPT |
c6428464 | 182 | #ifdef CONFIG_SMP |
2e82669a | 183 | cpu = thread->cpu; |
0d782dc4 | 184 | |
c6428464 CM |
185 | /* |
186 | * On SMP, if VFP is enabled, save the old state in | |
187 | * case the thread migrates to a different CPU. The | |
188 | * restoring is done lazily. | |
189 | */ | |
f8f2a852 | 190 | if ((fpexc & FPEXC_EN) && vfp_current_hw_state[cpu]) |
af61bdf0 | 191 | vfp_save_state(vfp_current_hw_state[cpu], fpexc); |
c6428464 CM |
192 | #endif |
193 | ||
681a4991 RK |
194 | /* |
195 | * Always disable VFP so we can lazily save/restore the | |
196 | * old state. | |
197 | */ | |
228adef1 | 198 | fmxr(FPEXC, fpexc & ~FPEXC_EN); |
6fa3eb70 | 199 | #endif |
2e82669a | 200 | break; |
681a4991 | 201 | |
2e82669a | 202 | case THREAD_NOTIFY_FLUSH: |
0d782dc4 | 203 | vfp_thread_flush(thread); |
2e82669a CM |
204 | break; |
205 | ||
206 | case THREAD_NOTIFY_EXIT: | |
797245f5 | 207 | vfp_thread_exit(thread); |
c98c0977 CM |
208 | break; |
209 | ||
210 | case THREAD_NOTIFY_COPY: | |
211 | vfp_thread_copy(thread); | |
2e82669a CM |
212 | break; |
213 | } | |
681a4991 | 214 | |
d6551e88 | 215 | return NOTIFY_DONE; |
1da177e4 LT |
216 | } |
217 | ||
d6551e88 RK |
218 | static struct notifier_block vfp_notifier_block = { |
219 | .notifier_call = vfp_notifier, | |
220 | }; | |
221 | ||
1da177e4 LT |
222 | /* |
223 | * Raise a SIGFPE for the current process. | |
224 | * sicode describes the signal being raised. | |
225 | */ | |
2bbd7e9b | 226 | static void vfp_raise_sigfpe(unsigned int sicode, struct pt_regs *regs) |
1da177e4 LT |
227 | { |
228 | siginfo_t info; | |
229 | ||
230 | memset(&info, 0, sizeof(info)); | |
231 | ||
232 | info.si_signo = SIGFPE; | |
233 | info.si_code = sicode; | |
35d59fc5 | 234 | info.si_addr = (void __user *)(instruction_pointer(regs) - 4); |
1da177e4 LT |
235 | |
236 | /* | |
237 | * This is the same as NWFPE, because it's not clear what | |
238 | * this is used for | |
239 | */ | |
240 | current->thread.error_code = 0; | |
241 | current->thread.trap_no = 6; | |
242 | ||
da41119a | 243 | send_sig_info(SIGFPE, &info, current); |
1da177e4 LT |
244 | } |
245 | ||
c98929c0 | 246 | static void vfp_panic(char *reason, u32 inst) |
1da177e4 LT |
247 | { |
248 | int i; | |
249 | ||
dc457078 NP |
250 | pr_err("VFP: Error: %s\n", reason); |
251 | pr_err("VFP: EXC 0x%08x SCR 0x%08x INST 0x%08x\n", | |
c98929c0 | 252 | fmrx(FPEXC), fmrx(FPSCR), inst); |
1da177e4 | 253 | for (i = 0; i < 32; i += 2) |
dc457078 | 254 | pr_err("VFP: s%2u: 0x%08x s%2u: 0x%08x\n", |
1da177e4 LT |
255 | i, vfp_get_float(i), i+1, vfp_get_float(i+1)); |
256 | } | |
257 | ||
258 | /* | |
259 | * Process bitmask of exception conditions. | |
260 | */ | |
261 | static void vfp_raise_exceptions(u32 exceptions, u32 inst, u32 fpscr, struct pt_regs *regs) | |
262 | { | |
263 | int si_code = 0; | |
264 | ||
265 | pr_debug("VFP: raising exceptions %08x\n", exceptions); | |
266 | ||
7c6f2514 | 267 | if (exceptions == VFP_EXCEPTION_ERROR) { |
c98929c0 | 268 | vfp_panic("unhandled bounce", inst); |
1da177e4 LT |
269 | vfp_raise_sigfpe(0, regs); |
270 | return; | |
271 | } | |
272 | ||
273 | /* | |
dbead405 | 274 | * If any of the status flags are set, update the FPSCR. |
1da177e4 LT |
275 | * Comparison instructions always return at least one of |
276 | * these flags set. | |
277 | */ | |
dbead405 CM |
278 | if (exceptions & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V)) |
279 | fpscr &= ~(FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V); | |
280 | ||
1da177e4 LT |
281 | fpscr |= exceptions; |
282 | ||
283 | fmxr(FPSCR, fpscr); | |
284 | ||
285 | #define RAISE(stat,en,sig) \ | |
286 | if (exceptions & stat && fpscr & en) \ | |
287 | si_code = sig; | |
288 | ||
289 | /* | |
290 | * These are arranged in priority order, least to highest. | |
291 | */ | |
e0f205d9 | 292 | RAISE(FPSCR_DZC, FPSCR_DZE, FPE_FLTDIV); |
1da177e4 LT |
293 | RAISE(FPSCR_IXC, FPSCR_IXE, FPE_FLTRES); |
294 | RAISE(FPSCR_UFC, FPSCR_UFE, FPE_FLTUND); | |
295 | RAISE(FPSCR_OFC, FPSCR_OFE, FPE_FLTOVF); | |
296 | RAISE(FPSCR_IOC, FPSCR_IOE, FPE_FLTINV); | |
297 | ||
298 | if (si_code) | |
299 | vfp_raise_sigfpe(si_code, regs); | |
300 | } | |
301 | ||
302 | /* | |
303 | * Emulate a VFP instruction. | |
304 | */ | |
305 | static u32 vfp_emulate_instruction(u32 inst, u32 fpscr, struct pt_regs *regs) | |
306 | { | |
7c6f2514 | 307 | u32 exceptions = VFP_EXCEPTION_ERROR; |
1da177e4 LT |
308 | |
309 | pr_debug("VFP: emulate: INST=0x%08x SCR=0x%08x\n", inst, fpscr); | |
310 | ||
311 | if (INST_CPRTDO(inst)) { | |
312 | if (!INST_CPRT(inst)) { | |
313 | /* | |
314 | * CPDO | |
315 | */ | |
316 | if (vfp_single(inst)) { | |
317 | exceptions = vfp_single_cpdo(inst, fpscr); | |
318 | } else { | |
319 | exceptions = vfp_double_cpdo(inst, fpscr); | |
320 | } | |
321 | } else { | |
322 | /* | |
323 | * A CPRT instruction can not appear in FPINST2, nor | |
324 | * can it cause an exception. Therefore, we do not | |
325 | * have to emulate it. | |
326 | */ | |
327 | } | |
328 | } else { | |
329 | /* | |
330 | * A CPDT instruction can not appear in FPINST2, nor can | |
331 | * it cause an exception. Therefore, we do not have to | |
332 | * emulate it. | |
333 | */ | |
334 | } | |
928bd1b4 | 335 | return exceptions & ~VFP_NAN_FLAG; |
1da177e4 LT |
336 | } |
337 | ||
338 | /* | |
339 | * Package up a bounce condition. | |
340 | */ | |
c98929c0 | 341 | void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs) |
1da177e4 | 342 | { |
c98929c0 | 343 | u32 fpscr, orig_fpscr, fpsid, exceptions; |
1da177e4 LT |
344 | |
345 | pr_debug("VFP: bounce: trigger %08x fpexc %08x\n", trigger, fpexc); | |
346 | ||
347 | /* | |
c98929c0 CM |
348 | * At this point, FPEXC can have the following configuration: |
349 | * | |
350 | * EX DEX IXE | |
351 | * 0 1 x - synchronous exception | |
352 | * 1 x 0 - asynchronous exception | |
353 | * 1 x 1 - sychronous on VFP subarch 1 and asynchronous on later | |
354 | * 0 0 1 - synchronous on VFP9 (non-standard subarch 1 | |
355 | * implementation), undefined otherwise | |
356 | * | |
357 | * Clear various bits and enable access to the VFP so we can | |
358 | * handle the bounce. | |
1da177e4 | 359 | */ |
c98929c0 | 360 | fmxr(FPEXC, fpexc & ~(FPEXC_EX|FPEXC_DEX|FPEXC_FP2V|FPEXC_VV|FPEXC_TRAP_MASK)); |
1da177e4 | 361 | |
c98929c0 | 362 | fpsid = fmrx(FPSID); |
1da177e4 LT |
363 | orig_fpscr = fpscr = fmrx(FPSCR); |
364 | ||
365 | /* | |
c98929c0 | 366 | * Check for the special VFP subarch 1 and FPSCR.IXE bit case |
1da177e4 | 367 | */ |
c98929c0 CM |
368 | if ((fpsid & FPSID_ARCH_MASK) == (1 << FPSID_ARCH_BIT) |
369 | && (fpscr & FPSCR_IXE)) { | |
370 | /* | |
371 | * Synchronous exception, emulate the trigger instruction | |
372 | */ | |
1da177e4 LT |
373 | goto emulate; |
374 | } | |
375 | ||
c98929c0 | 376 | if (fpexc & FPEXC_EX) { |
85d6943a | 377 | #ifndef CONFIG_CPU_FEROCEON |
c98929c0 CM |
378 | /* |
379 | * Asynchronous exception. The instruction is read from FPINST | |
380 | * and the interrupted instruction has to be restarted. | |
381 | */ | |
382 | trigger = fmrx(FPINST); | |
383 | regs->ARM_pc -= 4; | |
85d6943a | 384 | #endif |
c98929c0 CM |
385 | } else if (!(fpexc & FPEXC_DEX)) { |
386 | /* | |
387 | * Illegal combination of bits. It can be caused by an | |
388 | * unallocated VFP instruction but with FPSCR.IXE set and not | |
389 | * on VFP subarch 1. | |
390 | */ | |
391 | vfp_raise_exceptions(VFP_EXCEPTION_ERROR, trigger, fpscr, regs); | |
f2255be8 | 392 | goto exit; |
c98929c0 | 393 | } |
1da177e4 LT |
394 | |
395 | /* | |
c98929c0 CM |
396 | * Modify fpscr to indicate the number of iterations remaining. |
397 | * If FPEXC.EX is 0, FPEXC.DEX is 1 and the FPEXC.VV bit indicates | |
398 | * whether FPEXC.VECITR or FPSCR.LEN is used. | |
1da177e4 | 399 | */ |
c98929c0 | 400 | if (fpexc & (FPEXC_EX | FPEXC_VV)) { |
1da177e4 LT |
401 | u32 len; |
402 | ||
403 | len = fpexc + (1 << FPEXC_LENGTH_BIT); | |
404 | ||
405 | fpscr &= ~FPSCR_LENGTH_MASK; | |
406 | fpscr |= (len & FPEXC_LENGTH_MASK) << (FPSCR_LENGTH_BIT - FPEXC_LENGTH_BIT); | |
407 | } | |
408 | ||
409 | /* | |
410 | * Handle the first FP instruction. We used to take note of the | |
411 | * FPEXC bounce reason, but this appears to be unreliable. | |
412 | * Emulate the bounced instruction instead. | |
413 | */ | |
c98929c0 | 414 | exceptions = vfp_emulate_instruction(trigger, fpscr, regs); |
1da177e4 | 415 | if (exceptions) |
c98929c0 | 416 | vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs); |
1da177e4 LT |
417 | |
418 | /* | |
c98929c0 CM |
419 | * If there isn't a second FP instruction, exit now. Note that |
420 | * the FPEXC.FP2V bit is valid only if FPEXC.EX is 1. | |
1da177e4 | 421 | */ |
5e4ba617 | 422 | if ((fpexc & (FPEXC_EX | FPEXC_FP2V)) != (FPEXC_EX | FPEXC_FP2V)) |
f2255be8 | 423 | goto exit; |
1da177e4 LT |
424 | |
425 | /* | |
426 | * The barrier() here prevents fpinst2 being read | |
427 | * before the condition above. | |
428 | */ | |
429 | barrier(); | |
430 | trigger = fmrx(FPINST2); | |
1da177e4 LT |
431 | |
432 | emulate: | |
c98929c0 | 433 | exceptions = vfp_emulate_instruction(trigger, orig_fpscr, regs); |
1da177e4 LT |
434 | if (exceptions) |
435 | vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs); | |
f2255be8 GD |
436 | exit: |
437 | preempt_enable(); | |
1da177e4 | 438 | } |
efe90d27 | 439 | |
8e140362 RK |
440 | static void vfp_enable(void *unused) |
441 | { | |
998de4ac WD |
442 | u32 access; |
443 | ||
444 | BUG_ON(preemptible()); | |
445 | access = get_copro_access(); | |
8e140362 RK |
446 | |
447 | /* | |
448 | * Enable full access to VFP (cp10 and cp11) | |
449 | */ | |
450 | set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11)); | |
451 | } | |
452 | ||
746a9d19 | 453 | #ifdef CONFIG_CPU_PM |
328f5cc3 | 454 | static int vfp_pm_suspend(void) |
fc0b7a20 BD |
455 | { |
456 | struct thread_info *ti = current_thread_info(); | |
457 | u32 fpexc = fmrx(FPEXC); | |
458 | ||
459 | /* if vfp is on, then save state for resumption */ | |
460 | if (fpexc & FPEXC_EN) { | |
dc457078 | 461 | pr_debug("%s: saving vfp state\n", __func__); |
fc0b7a20 BD |
462 | vfp_save_state(&ti->vfpstate, fpexc); |
463 | ||
6fa3eb70 | 464 | #ifndef CONFIG_VFP_OPT |
fc0b7a20 BD |
465 | /* disable, just in case */ |
466 | fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); | |
6fa3eb70 | 467 | #endif |
24b35521 CC |
468 | } else if (vfp_current_hw_state[ti->cpu]) { |
469 | #ifndef CONFIG_SMP | |
470 | fmxr(FPEXC, fpexc | FPEXC_EN); | |
471 | vfp_save_state(vfp_current_hw_state[ti->cpu], fpexc); | |
6fa3eb70 | 472 | #ifndef CONFIG_VFP_OPT |
24b35521 | 473 | fmxr(FPEXC, fpexc); |
6fa3eb70 | 474 | #endif |
24b35521 | 475 | #endif |
fc0b7a20 BD |
476 | } |
477 | ||
478 | /* clear any information we had about last context state */ | |
a84b895a | 479 | vfp_current_hw_state[ti->cpu] = NULL; |
fc0b7a20 BD |
480 | |
481 | return 0; | |
482 | } | |
483 | ||
328f5cc3 | 484 | static void vfp_pm_resume(void) |
fc0b7a20 | 485 | { |
6fa3eb70 S |
486 | #ifdef CONFIG_VFP_OPT |
487 | struct thread_info *ti = current_thread_info(); | |
488 | u32 *vfpstate = (u32 *)(&ti->vfpstate); | |
489 | u32 temp = 0; | |
490 | u32 fpexc = 0, fpscr = 0, fpinst = 0, fpinst2 = 0; | |
491 | #endif | |
492 | ||
fc0b7a20 BD |
493 | /* ensure we have access to the vfp */ |
494 | vfp_enable(NULL); | |
495 | ||
6fa3eb70 | 496 | #ifndef CONFIG_VFP_OPT |
fc0b7a20 BD |
497 | /* and disable it to ensure the next usage restores the state */ |
498 | fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); | |
6fa3eb70 S |
499 | #else |
500 | /* restore VFP registers and state */ | |
501 | asm volatile ( | |
502 | "LDC p11, cr0, [%0],#32*4\n" | |
503 | //"VFPFMRX \tmp, MVFR0\n" | |
504 | "MRC p10, 7, %1, cr7, cr0, 0\n" | |
505 | "and %1, %1, %6\n" | |
506 | "cmp %1, #2\n" | |
507 | "ldceql p11, cr0, [%0],#32*4\n" | |
508 | "addne %0, %0, #32*4\n" | |
509 | "ldmia %0, {%2, %3, %4, %5}\n" | |
510 | //"VFPFMXR FPSCR, %3\n" | |
511 | "MCR p10, 7, %3, cr1, cr0, 0" | |
512 | : "+r"(vfpstate), "+r"(temp), "+r"(fpexc), "+r"(fpscr), "+r"(fpinst), "+r"(fpinst2) | |
513 | : "r" (MVFR0_A_SIMD_MASK) | |
514 | : "cc" | |
515 | ); | |
516 | #endif | |
517 | ||
fc0b7a20 BD |
518 | } |
519 | ||
746a9d19 CC |
520 | static int vfp_cpu_pm_notifier(struct notifier_block *self, unsigned long cmd, |
521 | void *v) | |
522 | { | |
523 | switch (cmd) { | |
524 | case CPU_PM_ENTER: | |
525 | vfp_pm_suspend(); | |
526 | break; | |
527 | case CPU_PM_ENTER_FAILED: | |
528 | case CPU_PM_EXIT: | |
529 | vfp_pm_resume(); | |
530 | break; | |
531 | } | |
532 | return NOTIFY_OK; | |
533 | } | |
534 | ||
535 | static struct notifier_block vfp_cpu_pm_notifier_block = { | |
536 | .notifier_call = vfp_cpu_pm_notifier, | |
fc0b7a20 BD |
537 | }; |
538 | ||
fc0b7a20 BD |
539 | static void vfp_pm_init(void) |
540 | { | |
746a9d19 | 541 | cpu_pm_register_notifier(&vfp_cpu_pm_notifier_block); |
fc0b7a20 BD |
542 | } |
543 | ||
fc0b7a20 BD |
544 | #else |
545 | static inline void vfp_pm_init(void) { } | |
746a9d19 | 546 | #endif /* CONFIG_CPU_PM */ |
fc0b7a20 | 547 | |
f8f2a852 RK |
548 | /* |
549 | * Ensure that the VFP state stored in 'thread->vfpstate' is up to date | |
550 | * with the hardware state. | |
551 | */ | |
ad187f95 | 552 | void vfp_sync_hwstate(struct thread_info *thread) |
3d1228ea CM |
553 | { |
554 | unsigned int cpu = get_cpu(); | |
3d1228ea | 555 | |
f8f2a852 | 556 | if (vfp_state_in_hw(cpu, thread)) { |
54cb3dbb | 557 | u32 fpexc = fmrx(FPEXC); |
3d1228ea | 558 | |
54cb3dbb RK |
559 | /* |
560 | * Save the last VFP state on this CPU. | |
561 | */ | |
562 | fmxr(FPEXC, fpexc | FPEXC_EN); | |
563 | vfp_save_state(&thread->vfpstate, fpexc | FPEXC_EN); | |
6fa3eb70 | 564 | #ifndef CONFIG_VFP_OPT |
ad187f95 | 565 | fmxr(FPEXC, fpexc); |
6fa3eb70 | 566 | #endif |
ad187f95 | 567 | } |
3d1228ea | 568 | |
ad187f95 RK |
569 | put_cpu(); |
570 | } | |
571 | ||
f8f2a852 | 572 | /* Ensure that the thread reloads the hardware VFP state on the next use. */ |
ad187f95 RK |
573 | void vfp_flush_hwstate(struct thread_info *thread) |
574 | { | |
575 | unsigned int cpu = get_cpu(); | |
3d1228ea | 576 | |
f8f2a852 | 577 | vfp_force_reload(cpu, thread); |
ad187f95 | 578 | |
3d1228ea CM |
579 | put_cpu(); |
580 | } | |
3d1228ea | 581 | |
2498814f WD |
582 | /* |
583 | * Save the current VFP state into the provided structures and prepare | |
584 | * for entry into a new function (signal handler). | |
585 | */ | |
586 | int vfp_preserve_user_clear_hwstate(struct user_vfp __user *ufp, | |
587 | struct user_vfp_exc __user *ufp_exc) | |
588 | { | |
589 | struct thread_info *thread = current_thread_info(); | |
590 | struct vfp_hard_struct *hwstate = &thread->vfpstate.hard; | |
591 | int err = 0; | |
592 | ||
593 | /* Ensure that the saved hwstate is up-to-date. */ | |
594 | vfp_sync_hwstate(thread); | |
595 | ||
596 | /* | |
597 | * Copy the floating point registers. There can be unused | |
598 | * registers see asm/hwcap.h for details. | |
599 | */ | |
600 | err |= __copy_to_user(&ufp->fpregs, &hwstate->fpregs, | |
601 | sizeof(hwstate->fpregs)); | |
602 | /* | |
603 | * Copy the status and control register. | |
604 | */ | |
605 | __put_user_error(hwstate->fpscr, &ufp->fpscr, err); | |
606 | ||
607 | /* | |
608 | * Copy the exception registers. | |
609 | */ | |
610 | __put_user_error(hwstate->fpexc, &ufp_exc->fpexc, err); | |
611 | __put_user_error(hwstate->fpinst, &ufp_exc->fpinst, err); | |
612 | __put_user_error(hwstate->fpinst2, &ufp_exc->fpinst2, err); | |
613 | ||
614 | if (err) | |
615 | return -EFAULT; | |
ff9a184c WD |
616 | |
617 | /* Ensure that VFP is disabled. */ | |
618 | vfp_flush_hwstate(thread); | |
619 | ||
620 | /* | |
621 | * As per the PCS, clear the length and stride bits for function | |
622 | * entry. | |
623 | */ | |
624 | hwstate->fpscr &= ~(FPSCR_LENGTH_MASK | FPSCR_STRIDE_MASK); | |
2498814f WD |
625 | return 0; |
626 | } | |
627 | ||
628 | /* Sanitise and restore the current VFP state from the provided structures. */ | |
629 | int vfp_restore_user_hwstate(struct user_vfp __user *ufp, | |
630 | struct user_vfp_exc __user *ufp_exc) | |
631 | { | |
632 | struct thread_info *thread = current_thread_info(); | |
633 | struct vfp_hard_struct *hwstate = &thread->vfpstate.hard; | |
634 | unsigned long fpexc; | |
635 | int err = 0; | |
636 | ||
56cb2484 WD |
637 | /* Disable VFP to avoid corrupting the new thread state. */ |
638 | vfp_flush_hwstate(thread); | |
2498814f WD |
639 | |
640 | /* | |
641 | * Copy the floating point registers. There can be unused | |
642 | * registers see asm/hwcap.h for details. | |
643 | */ | |
644 | err |= __copy_from_user(&hwstate->fpregs, &ufp->fpregs, | |
645 | sizeof(hwstate->fpregs)); | |
646 | /* | |
647 | * Copy the status and control register. | |
648 | */ | |
649 | __get_user_error(hwstate->fpscr, &ufp->fpscr, err); | |
650 | ||
651 | /* | |
652 | * Sanitise and restore the exception registers. | |
653 | */ | |
654 | __get_user_error(fpexc, &ufp_exc->fpexc, err); | |
655 | ||
656 | /* Ensure the VFP is enabled. */ | |
657 | fpexc |= FPEXC_EN; | |
658 | ||
659 | /* Ensure FPINST2 is invalid and the exception flag is cleared. */ | |
660 | fpexc &= ~(FPEXC_EX | FPEXC_FP2V); | |
661 | hwstate->fpexc = fpexc; | |
662 | ||
663 | __get_user_error(hwstate->fpinst, &ufp_exc->fpinst, err); | |
664 | __get_user_error(hwstate->fpinst2, &ufp_exc->fpinst2, err); | |
665 | ||
666 | return err ? -EFAULT : 0; | |
667 | } | |
668 | ||
90b44199 RK |
669 | /* |
670 | * VFP hardware can lose all context when a CPU goes offline. | |
74c25bee RK |
671 | * As we will be running in SMP mode with CPU hotplug, we will save the |
672 | * hardware state at every thread switch. We clear our held state when | |
673 | * a CPU has been killed, indicating that the VFP hardware doesn't contain | |
674 | * a threads VFP state. When a CPU starts up, we re-enable access to the | |
675 | * VFP hardware. | |
90b44199 RK |
676 | * |
677 | * Both CPU_DYING and CPU_STARTING are called on the CPU which | |
678 | * is being offlined/onlined. | |
679 | */ | |
680 | static int vfp_hotplug(struct notifier_block *b, unsigned long action, | |
681 | void *hcpu) | |
682 | { | |
683 | if (action == CPU_DYING || action == CPU_DYING_FROZEN) { | |
f8f2a852 | 684 | vfp_force_reload((long)hcpu, current_thread_info()); |
90b44199 RK |
685 | } else if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) |
686 | vfp_enable(NULL); | |
687 | return NOTIFY_OK; | |
688 | } | |
8e140362 | 689 | |
1da177e4 LT |
690 | /* |
691 | * VFP support code initialisation. | |
692 | */ | |
693 | static int __init vfp_init(void) | |
694 | { | |
695 | unsigned int vfpsid; | |
efe90d27 | 696 | unsigned int cpu_arch = cpu_architecture(); |
efe90d27 | 697 | |
c98929c0 | 698 | if (cpu_arch >= CPU_ARCH_ARMv6) |
998de4ac | 699 | on_each_cpu(vfp_enable, NULL, 1); |
1da177e4 LT |
700 | |
701 | /* | |
702 | * First check that there is a VFP that we can use. | |
703 | * The handler is already setup to just log calls, so | |
704 | * we just need to read the VFPSID register. | |
705 | */ | |
5d4cae5f | 706 | vfp_vector = vfp_testing_entry; |
b9338a78 | 707 | barrier(); |
1da177e4 | 708 | vfpsid = fmrx(FPSID); |
8e140362 | 709 | barrier(); |
5d4cae5f | 710 | vfp_vector = vfp_null_entry; |
1da177e4 | 711 | |
dc457078 | 712 | pr_info("VFP support v0.3: "); |
c98929c0 | 713 | if (VFP_arch) |
dc457078 | 714 | pr_cont("not present\n"); |
c98929c0 | 715 | else if (vfpsid & FPSID_NODOUBLE) { |
dc457078 | 716 | pr_cont("no double precision support\n"); |
1da177e4 | 717 | } else { |
90b44199 RK |
718 | hotcpu_notifier(vfp_hotplug, 0); |
719 | ||
1da177e4 | 720 | VFP_arch = (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT; /* Extract the architecture version */ |
dc457078 | 721 | pr_cont("implementor %02x architecture %d part %02x variant %x rev %x\n", |
1da177e4 LT |
722 | (vfpsid & FPSID_IMPLEMENTER_MASK) >> FPSID_IMPLEMENTER_BIT, |
723 | (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT, | |
724 | (vfpsid & FPSID_PART_MASK) >> FPSID_PART_BIT, | |
725 | (vfpsid & FPSID_VARIANT_MASK) >> FPSID_VARIANT_BIT, | |
726 | (vfpsid & FPSID_REV_MASK) >> FPSID_REV_BIT); | |
efe90d27 | 727 | |
1da177e4 | 728 | vfp_vector = vfp_support_entry; |
d6551e88 RK |
729 | |
730 | thread_register_notifier(&vfp_notifier_block); | |
fc0b7a20 | 731 | vfp_pm_init(); |
efe90d27 RK |
732 | |
733 | /* | |
734 | * We detected VFP, and the support code is | |
735 | * in place; report VFP support to userspace. | |
736 | */ | |
737 | elf_hwcap |= HWCAP_VFP; | |
7279dc3e | 738 | #ifdef CONFIG_VFPv3 |
325ffc36 | 739 | if (VFP_arch >= 2) { |
7279dc3e CM |
740 | elf_hwcap |= HWCAP_VFPv3; |
741 | ||
742 | /* | |
39141ddf PW |
743 | * Check for VFPv3 D16 and VFPv4 D16. CPUs in |
744 | * this configuration only have 16 x 64bit | |
745 | * registers. | |
7279dc3e CM |
746 | */ |
747 | if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK)) == 1) | |
39141ddf PW |
748 | elf_hwcap |= HWCAP_VFPv3D16; /* also v4-D16 */ |
749 | else | |
750 | elf_hwcap |= HWCAP_VFPD32; | |
7279dc3e CM |
751 | } |
752 | #endif | |
2bedbdf4 CM |
753 | /* |
754 | * Check for the presence of the Advanced SIMD | |
755 | * load/store instructions, integer and single | |
5aaf2544 TL |
756 | * precision floating point operations. Only check |
757 | * for NEON if the hardware has the MVFR registers. | |
2bedbdf4 | 758 | */ |
5aaf2544 | 759 | if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) { |
18b9dc13 | 760 | #ifdef CONFIG_NEON |
5aaf2544 TL |
761 | if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100) |
762 | elf_hwcap |= HWCAP_NEON; | |
2bedbdf4 | 763 | #endif |
3d9fb003 | 764 | #ifdef CONFIG_VFPv3 |
18b9dc13 WD |
765 | if ((fmrx(MVFR1) & 0xf0000000) == 0x10000000) |
766 | elf_hwcap |= HWCAP_VFPv4; | |
3d9fb003 | 767 | #endif |
18b9dc13 | 768 | } |
1da177e4 LT |
769 | } |
770 | return 0; | |
771 | } | |
772 | ||
773 | late_initcall(vfp_init); |