Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/vfp/vfpmodule.c | |
3 | * | |
4 | * Copyright (C) 2004 ARM Limited. | |
5 | * Written by Deep Blue Solutions Limited. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/module.h> | |
1da177e4 | 12 | #include <linux/types.h> |
90b44199 | 13 | #include <linux/cpu.h> |
1da177e4 | 14 | #include <linux/kernel.h> |
90b44199 | 15 | #include <linux/notifier.h> |
1da177e4 LT |
16 | #include <linux/signal.h> |
17 | #include <linux/sched.h> | |
90b44199 | 18 | #include <linux/smp.h> |
1da177e4 | 19 | #include <linux/init.h> |
d6551e88 | 20 | |
5aaf2544 | 21 | #include <asm/cputype.h> |
d6551e88 | 22 | #include <asm/thread_notify.h> |
1da177e4 LT |
23 | #include <asm/vfp.h> |
24 | ||
25 | #include "vfpinstr.h" | |
26 | #include "vfp.h" | |
27 | ||
28 | /* | |
29 | * Our undef handlers (in entry.S) | |
30 | */ | |
31 | void vfp_testing_entry(void); | |
32 | void vfp_support_entry(void); | |
5d4cae5f | 33 | void vfp_null_entry(void); |
1da177e4 | 34 | |
5d4cae5f | 35 | void (*vfp_vector)(void) = vfp_null_entry; |
af61bdf0 | 36 | |
f8f2a852 RK |
37 | /* |
38 | * Dual-use variable. | |
39 | * Used in startup: set to non-zero if VFP checks fail | |
40 | * After startup, holds VFP architecture | |
41 | */ | |
42 | unsigned int VFP_arch; | |
43 | ||
af61bdf0 RK |
44 | /* |
45 | * The pointer to the vfpstate structure of the thread which currently | |
46 | * owns the context held in the VFP hardware, or NULL if the hardware | |
47 | * context is invalid. | |
f8f2a852 RK |
48 | * |
49 | * For UP, this is sufficient to tell which thread owns the VFP context. | |
50 | * However, for SMP, we also need to check the CPU number stored in the | |
51 | * saved state too to catch migrations. | |
af61bdf0 RK |
52 | */ |
53 | union vfp_state *vfp_current_hw_state[NR_CPUS]; | |
1da177e4 LT |
54 | |
55 | /* | |
f8f2a852 RK |
56 | * Is 'thread's most up to date state stored in this CPUs hardware? |
57 | * Must be called from non-preemptible context. | |
1da177e4 | 58 | */ |
f8f2a852 RK |
59 | static bool vfp_state_in_hw(unsigned int cpu, struct thread_info *thread) |
60 | { | |
61 | #ifdef CONFIG_SMP | |
62 | if (thread->vfpstate.hard.cpu != cpu) | |
63 | return false; | |
64 | #endif | |
65 | return vfp_current_hw_state[cpu] == &thread->vfpstate; | |
66 | } | |
67 | ||
68 | /* | |
69 | * Force a reload of the VFP context from the thread structure. We do | |
70 | * this by ensuring that access to the VFP hardware is disabled, and | |
71 | * clear last_VFP_context. Must be called from non-preemptible context. | |
72 | */ | |
73 | static void vfp_force_reload(unsigned int cpu, struct thread_info *thread) | |
74 | { | |
75 | if (vfp_state_in_hw(cpu, thread)) { | |
76 | fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); | |
77 | vfp_current_hw_state[cpu] = NULL; | |
78 | } | |
79 | #ifdef CONFIG_SMP | |
80 | thread->vfpstate.hard.cpu = NR_CPUS; | |
81 | #endif | |
82 | } | |
1da177e4 | 83 | |
0d782dc4 RK |
84 | /* |
85 | * Per-thread VFP initialization. | |
86 | */ | |
87 | static void vfp_thread_flush(struct thread_info *thread) | |
88 | { | |
89 | union vfp_state *vfp = &thread->vfpstate; | |
90 | unsigned int cpu; | |
91 | ||
0d782dc4 RK |
92 | /* |
93 | * Disable VFP to ensure we initialize it first. We must ensure | |
19dad35f RK |
94 | * that the modification of vfp_current_hw_state[] and hardware |
95 | * disable are done for the same CPU and without preemption. | |
96 | * | |
97 | * Do this first to ensure that preemption won't overwrite our | |
98 | * state saving should access to the VFP be enabled at this point. | |
0d782dc4 RK |
99 | */ |
100 | cpu = get_cpu(); | |
af61bdf0 RK |
101 | if (vfp_current_hw_state[cpu] == vfp) |
102 | vfp_current_hw_state[cpu] = NULL; | |
0d782dc4 RK |
103 | fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); |
104 | put_cpu(); | |
19dad35f RK |
105 | |
106 | memset(vfp, 0, sizeof(union vfp_state)); | |
107 | ||
108 | vfp->hard.fpexc = FPEXC_EN; | |
109 | vfp->hard.fpscr = FPSCR_ROUND_NEAREST; | |
110 | #ifdef CONFIG_SMP | |
111 | vfp->hard.cpu = NR_CPUS; | |
112 | #endif | |
0d782dc4 RK |
113 | } |
114 | ||
797245f5 | 115 | static void vfp_thread_exit(struct thread_info *thread) |
0d782dc4 RK |
116 | { |
117 | /* release case: Per-thread VFP cleanup. */ | |
118 | union vfp_state *vfp = &thread->vfpstate; | |
797245f5 | 119 | unsigned int cpu = get_cpu(); |
0d782dc4 | 120 | |
af61bdf0 RK |
121 | if (vfp_current_hw_state[cpu] == vfp) |
122 | vfp_current_hw_state[cpu] = NULL; | |
797245f5 | 123 | put_cpu(); |
0d782dc4 RK |
124 | } |
125 | ||
c98c0977 CM |
126 | static void vfp_thread_copy(struct thread_info *thread) |
127 | { | |
128 | struct thread_info *parent = current_thread_info(); | |
129 | ||
130 | vfp_sync_hwstate(parent); | |
131 | thread->vfpstate = parent->vfpstate; | |
f8f2a852 RK |
132 | #ifdef CONFIG_SMP |
133 | thread->vfpstate.hard.cpu = NR_CPUS; | |
134 | #endif | |
c98c0977 CM |
135 | } |
136 | ||
0d782dc4 RK |
137 | /* |
138 | * When this function is called with the following 'cmd's, the following | |
139 | * is true while this function is being run: | |
140 | * THREAD_NOFTIFY_SWTICH: | |
141 | * - the previously running thread will not be scheduled onto another CPU. | |
142 | * - the next thread to be run (v) will not be running on another CPU. | |
143 | * - thread->cpu is the local CPU number | |
144 | * - not preemptible as we're called in the middle of a thread switch | |
145 | * THREAD_NOTIFY_FLUSH: | |
146 | * - the thread (v) will be running on the local CPU, so | |
147 | * v === current_thread_info() | |
148 | * - thread->cpu is the local CPU number at the time it is accessed, | |
149 | * but may change at any time. | |
150 | * - we could be preempted if tree preempt rcu is enabled, so | |
151 | * it is unsafe to use thread->cpu. | |
797245f5 RK |
152 | * THREAD_NOTIFY_EXIT |
153 | * - the thread (v) will be running on the local CPU, so | |
154 | * v === current_thread_info() | |
155 | * - thread->cpu is the local CPU number at the time it is accessed, | |
156 | * but may change at any time. | |
157 | * - we could be preempted if tree preempt rcu is enabled, so | |
158 | * it is unsafe to use thread->cpu. | |
0d782dc4 | 159 | */ |
d6551e88 | 160 | static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v) |
1da177e4 | 161 | { |
d6551e88 | 162 | struct thread_info *thread = v; |
2e82669a CM |
163 | u32 fpexc; |
164 | #ifdef CONFIG_SMP | |
165 | unsigned int cpu; | |
166 | #endif | |
1da177e4 | 167 | |
2e82669a CM |
168 | switch (cmd) { |
169 | case THREAD_NOTIFY_SWITCH: | |
170 | fpexc = fmrx(FPEXC); | |
c6428464 CM |
171 | |
172 | #ifdef CONFIG_SMP | |
2e82669a | 173 | cpu = thread->cpu; |
0d782dc4 | 174 | |
c6428464 CM |
175 | /* |
176 | * On SMP, if VFP is enabled, save the old state in | |
177 | * case the thread migrates to a different CPU. The | |
178 | * restoring is done lazily. | |
179 | */ | |
f8f2a852 | 180 | if ((fpexc & FPEXC_EN) && vfp_current_hw_state[cpu]) |
af61bdf0 | 181 | vfp_save_state(vfp_current_hw_state[cpu], fpexc); |
c6428464 CM |
182 | #endif |
183 | ||
681a4991 RK |
184 | /* |
185 | * Always disable VFP so we can lazily save/restore the | |
186 | * old state. | |
187 | */ | |
228adef1 | 188 | fmxr(FPEXC, fpexc & ~FPEXC_EN); |
2e82669a | 189 | break; |
681a4991 | 190 | |
2e82669a | 191 | case THREAD_NOTIFY_FLUSH: |
0d782dc4 | 192 | vfp_thread_flush(thread); |
2e82669a CM |
193 | break; |
194 | ||
195 | case THREAD_NOTIFY_EXIT: | |
797245f5 | 196 | vfp_thread_exit(thread); |
c98c0977 CM |
197 | break; |
198 | ||
199 | case THREAD_NOTIFY_COPY: | |
200 | vfp_thread_copy(thread); | |
2e82669a CM |
201 | break; |
202 | } | |
681a4991 | 203 | |
d6551e88 | 204 | return NOTIFY_DONE; |
1da177e4 LT |
205 | } |
206 | ||
d6551e88 RK |
207 | static struct notifier_block vfp_notifier_block = { |
208 | .notifier_call = vfp_notifier, | |
209 | }; | |
210 | ||
1da177e4 LT |
211 | /* |
212 | * Raise a SIGFPE for the current process. | |
213 | * sicode describes the signal being raised. | |
214 | */ | |
2bbd7e9b | 215 | static void vfp_raise_sigfpe(unsigned int sicode, struct pt_regs *regs) |
1da177e4 LT |
216 | { |
217 | siginfo_t info; | |
218 | ||
219 | memset(&info, 0, sizeof(info)); | |
220 | ||
221 | info.si_signo = SIGFPE; | |
222 | info.si_code = sicode; | |
35d59fc5 | 223 | info.si_addr = (void __user *)(instruction_pointer(regs) - 4); |
1da177e4 LT |
224 | |
225 | /* | |
226 | * This is the same as NWFPE, because it's not clear what | |
227 | * this is used for | |
228 | */ | |
229 | current->thread.error_code = 0; | |
230 | current->thread.trap_no = 6; | |
231 | ||
da41119a | 232 | send_sig_info(SIGFPE, &info, current); |
1da177e4 LT |
233 | } |
234 | ||
c98929c0 | 235 | static void vfp_panic(char *reason, u32 inst) |
1da177e4 LT |
236 | { |
237 | int i; | |
238 | ||
239 | printk(KERN_ERR "VFP: Error: %s\n", reason); | |
240 | printk(KERN_ERR "VFP: EXC 0x%08x SCR 0x%08x INST 0x%08x\n", | |
c98929c0 | 241 | fmrx(FPEXC), fmrx(FPSCR), inst); |
1da177e4 LT |
242 | for (i = 0; i < 32; i += 2) |
243 | printk(KERN_ERR "VFP: s%2u: 0x%08x s%2u: 0x%08x\n", | |
244 | i, vfp_get_float(i), i+1, vfp_get_float(i+1)); | |
245 | } | |
246 | ||
247 | /* | |
248 | * Process bitmask of exception conditions. | |
249 | */ | |
250 | static void vfp_raise_exceptions(u32 exceptions, u32 inst, u32 fpscr, struct pt_regs *regs) | |
251 | { | |
252 | int si_code = 0; | |
253 | ||
254 | pr_debug("VFP: raising exceptions %08x\n", exceptions); | |
255 | ||
7c6f2514 | 256 | if (exceptions == VFP_EXCEPTION_ERROR) { |
c98929c0 | 257 | vfp_panic("unhandled bounce", inst); |
1da177e4 LT |
258 | vfp_raise_sigfpe(0, regs); |
259 | return; | |
260 | } | |
261 | ||
262 | /* | |
dbead405 | 263 | * If any of the status flags are set, update the FPSCR. |
1da177e4 LT |
264 | * Comparison instructions always return at least one of |
265 | * these flags set. | |
266 | */ | |
dbead405 CM |
267 | if (exceptions & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V)) |
268 | fpscr &= ~(FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V); | |
269 | ||
1da177e4 LT |
270 | fpscr |= exceptions; |
271 | ||
272 | fmxr(FPSCR, fpscr); | |
273 | ||
274 | #define RAISE(stat,en,sig) \ | |
275 | if (exceptions & stat && fpscr & en) \ | |
276 | si_code = sig; | |
277 | ||
278 | /* | |
279 | * These are arranged in priority order, least to highest. | |
280 | */ | |
e0f205d9 | 281 | RAISE(FPSCR_DZC, FPSCR_DZE, FPE_FLTDIV); |
1da177e4 LT |
282 | RAISE(FPSCR_IXC, FPSCR_IXE, FPE_FLTRES); |
283 | RAISE(FPSCR_UFC, FPSCR_UFE, FPE_FLTUND); | |
284 | RAISE(FPSCR_OFC, FPSCR_OFE, FPE_FLTOVF); | |
285 | RAISE(FPSCR_IOC, FPSCR_IOE, FPE_FLTINV); | |
286 | ||
287 | if (si_code) | |
288 | vfp_raise_sigfpe(si_code, regs); | |
289 | } | |
290 | ||
291 | /* | |
292 | * Emulate a VFP instruction. | |
293 | */ | |
294 | static u32 vfp_emulate_instruction(u32 inst, u32 fpscr, struct pt_regs *regs) | |
295 | { | |
7c6f2514 | 296 | u32 exceptions = VFP_EXCEPTION_ERROR; |
1da177e4 LT |
297 | |
298 | pr_debug("VFP: emulate: INST=0x%08x SCR=0x%08x\n", inst, fpscr); | |
299 | ||
300 | if (INST_CPRTDO(inst)) { | |
301 | if (!INST_CPRT(inst)) { | |
302 | /* | |
303 | * CPDO | |
304 | */ | |
305 | if (vfp_single(inst)) { | |
306 | exceptions = vfp_single_cpdo(inst, fpscr); | |
307 | } else { | |
308 | exceptions = vfp_double_cpdo(inst, fpscr); | |
309 | } | |
310 | } else { | |
311 | /* | |
312 | * A CPRT instruction can not appear in FPINST2, nor | |
313 | * can it cause an exception. Therefore, we do not | |
314 | * have to emulate it. | |
315 | */ | |
316 | } | |
317 | } else { | |
318 | /* | |
319 | * A CPDT instruction can not appear in FPINST2, nor can | |
320 | * it cause an exception. Therefore, we do not have to | |
321 | * emulate it. | |
322 | */ | |
323 | } | |
928bd1b4 | 324 | return exceptions & ~VFP_NAN_FLAG; |
1da177e4 LT |
325 | } |
326 | ||
327 | /* | |
328 | * Package up a bounce condition. | |
329 | */ | |
c98929c0 | 330 | void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs) |
1da177e4 | 331 | { |
c98929c0 | 332 | u32 fpscr, orig_fpscr, fpsid, exceptions; |
1da177e4 LT |
333 | |
334 | pr_debug("VFP: bounce: trigger %08x fpexc %08x\n", trigger, fpexc); | |
335 | ||
336 | /* | |
c98929c0 CM |
337 | * At this point, FPEXC can have the following configuration: |
338 | * | |
339 | * EX DEX IXE | |
340 | * 0 1 x - synchronous exception | |
341 | * 1 x 0 - asynchronous exception | |
342 | * 1 x 1 - sychronous on VFP subarch 1 and asynchronous on later | |
343 | * 0 0 1 - synchronous on VFP9 (non-standard subarch 1 | |
344 | * implementation), undefined otherwise | |
345 | * | |
346 | * Clear various bits and enable access to the VFP so we can | |
347 | * handle the bounce. | |
1da177e4 | 348 | */ |
c98929c0 | 349 | fmxr(FPEXC, fpexc & ~(FPEXC_EX|FPEXC_DEX|FPEXC_FP2V|FPEXC_VV|FPEXC_TRAP_MASK)); |
1da177e4 | 350 | |
c98929c0 | 351 | fpsid = fmrx(FPSID); |
1da177e4 LT |
352 | orig_fpscr = fpscr = fmrx(FPSCR); |
353 | ||
354 | /* | |
c98929c0 | 355 | * Check for the special VFP subarch 1 and FPSCR.IXE bit case |
1da177e4 | 356 | */ |
c98929c0 CM |
357 | if ((fpsid & FPSID_ARCH_MASK) == (1 << FPSID_ARCH_BIT) |
358 | && (fpscr & FPSCR_IXE)) { | |
359 | /* | |
360 | * Synchronous exception, emulate the trigger instruction | |
361 | */ | |
1da177e4 LT |
362 | goto emulate; |
363 | } | |
364 | ||
c98929c0 | 365 | if (fpexc & FPEXC_EX) { |
85d6943a | 366 | #ifndef CONFIG_CPU_FEROCEON |
c98929c0 CM |
367 | /* |
368 | * Asynchronous exception. The instruction is read from FPINST | |
369 | * and the interrupted instruction has to be restarted. | |
370 | */ | |
371 | trigger = fmrx(FPINST); | |
372 | regs->ARM_pc -= 4; | |
85d6943a | 373 | #endif |
c98929c0 CM |
374 | } else if (!(fpexc & FPEXC_DEX)) { |
375 | /* | |
376 | * Illegal combination of bits. It can be caused by an | |
377 | * unallocated VFP instruction but with FPSCR.IXE set and not | |
378 | * on VFP subarch 1. | |
379 | */ | |
380 | vfp_raise_exceptions(VFP_EXCEPTION_ERROR, trigger, fpscr, regs); | |
f2255be8 | 381 | goto exit; |
c98929c0 | 382 | } |
1da177e4 LT |
383 | |
384 | /* | |
c98929c0 CM |
385 | * Modify fpscr to indicate the number of iterations remaining. |
386 | * If FPEXC.EX is 0, FPEXC.DEX is 1 and the FPEXC.VV bit indicates | |
387 | * whether FPEXC.VECITR or FPSCR.LEN is used. | |
1da177e4 | 388 | */ |
c98929c0 | 389 | if (fpexc & (FPEXC_EX | FPEXC_VV)) { |
1da177e4 LT |
390 | u32 len; |
391 | ||
392 | len = fpexc + (1 << FPEXC_LENGTH_BIT); | |
393 | ||
394 | fpscr &= ~FPSCR_LENGTH_MASK; | |
395 | fpscr |= (len & FPEXC_LENGTH_MASK) << (FPSCR_LENGTH_BIT - FPEXC_LENGTH_BIT); | |
396 | } | |
397 | ||
398 | /* | |
399 | * Handle the first FP instruction. We used to take note of the | |
400 | * FPEXC bounce reason, but this appears to be unreliable. | |
401 | * Emulate the bounced instruction instead. | |
402 | */ | |
c98929c0 | 403 | exceptions = vfp_emulate_instruction(trigger, fpscr, regs); |
1da177e4 | 404 | if (exceptions) |
c98929c0 | 405 | vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs); |
1da177e4 LT |
406 | |
407 | /* | |
c98929c0 CM |
408 | * If there isn't a second FP instruction, exit now. Note that |
409 | * the FPEXC.FP2V bit is valid only if FPEXC.EX is 1. | |
1da177e4 | 410 | */ |
c98929c0 | 411 | if (fpexc ^ (FPEXC_EX | FPEXC_FP2V)) |
f2255be8 | 412 | goto exit; |
1da177e4 LT |
413 | |
414 | /* | |
415 | * The barrier() here prevents fpinst2 being read | |
416 | * before the condition above. | |
417 | */ | |
418 | barrier(); | |
419 | trigger = fmrx(FPINST2); | |
1da177e4 LT |
420 | |
421 | emulate: | |
c98929c0 | 422 | exceptions = vfp_emulate_instruction(trigger, orig_fpscr, regs); |
1da177e4 LT |
423 | if (exceptions) |
424 | vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs); | |
f2255be8 GD |
425 | exit: |
426 | preempt_enable(); | |
1da177e4 | 427 | } |
efe90d27 | 428 | |
8e140362 RK |
429 | static void vfp_enable(void *unused) |
430 | { | |
431 | u32 access = get_copro_access(); | |
432 | ||
433 | /* | |
434 | * Enable full access to VFP (cp10 and cp11) | |
435 | */ | |
436 | set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11)); | |
437 | } | |
438 | ||
fc0b7a20 | 439 | #ifdef CONFIG_PM |
328f5cc3 | 440 | #include <linux/syscore_ops.h> |
fc0b7a20 | 441 | |
328f5cc3 | 442 | static int vfp_pm_suspend(void) |
fc0b7a20 BD |
443 | { |
444 | struct thread_info *ti = current_thread_info(); | |
445 | u32 fpexc = fmrx(FPEXC); | |
446 | ||
447 | /* if vfp is on, then save state for resumption */ | |
448 | if (fpexc & FPEXC_EN) { | |
449 | printk(KERN_DEBUG "%s: saving vfp state\n", __func__); | |
450 | vfp_save_state(&ti->vfpstate, fpexc); | |
451 | ||
452 | /* disable, just in case */ | |
453 | fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); | |
454 | } | |
455 | ||
456 | /* clear any information we had about last context state */ | |
af61bdf0 | 457 | memset(vfp_current_hw_state, 0, sizeof(vfp_current_hw_state)); |
fc0b7a20 BD |
458 | |
459 | return 0; | |
460 | } | |
461 | ||
328f5cc3 | 462 | static void vfp_pm_resume(void) |
fc0b7a20 BD |
463 | { |
464 | /* ensure we have access to the vfp */ | |
465 | vfp_enable(NULL); | |
466 | ||
467 | /* and disable it to ensure the next usage restores the state */ | |
468 | fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); | |
fc0b7a20 BD |
469 | } |
470 | ||
328f5cc3 | 471 | static struct syscore_ops vfp_pm_syscore_ops = { |
fc0b7a20 BD |
472 | .suspend = vfp_pm_suspend, |
473 | .resume = vfp_pm_resume, | |
474 | }; | |
475 | ||
fc0b7a20 BD |
476 | static void vfp_pm_init(void) |
477 | { | |
328f5cc3 | 478 | register_syscore_ops(&vfp_pm_syscore_ops); |
fc0b7a20 BD |
479 | } |
480 | ||
fc0b7a20 BD |
481 | #else |
482 | static inline void vfp_pm_init(void) { } | |
483 | #endif /* CONFIG_PM */ | |
484 | ||
f8f2a852 RK |
485 | /* |
486 | * Ensure that the VFP state stored in 'thread->vfpstate' is up to date | |
487 | * with the hardware state. | |
488 | */ | |
ad187f95 | 489 | void vfp_sync_hwstate(struct thread_info *thread) |
3d1228ea CM |
490 | { |
491 | unsigned int cpu = get_cpu(); | |
3d1228ea | 492 | |
f8f2a852 | 493 | if (vfp_state_in_hw(cpu, thread)) { |
54cb3dbb | 494 | u32 fpexc = fmrx(FPEXC); |
3d1228ea | 495 | |
54cb3dbb RK |
496 | /* |
497 | * Save the last VFP state on this CPU. | |
498 | */ | |
499 | fmxr(FPEXC, fpexc | FPEXC_EN); | |
500 | vfp_save_state(&thread->vfpstate, fpexc | FPEXC_EN); | |
ad187f95 RK |
501 | fmxr(FPEXC, fpexc); |
502 | } | |
3d1228ea | 503 | |
ad187f95 RK |
504 | put_cpu(); |
505 | } | |
506 | ||
f8f2a852 | 507 | /* Ensure that the thread reloads the hardware VFP state on the next use. */ |
ad187f95 RK |
508 | void vfp_flush_hwstate(struct thread_info *thread) |
509 | { | |
510 | unsigned int cpu = get_cpu(); | |
3d1228ea | 511 | |
f8f2a852 | 512 | vfp_force_reload(cpu, thread); |
ad187f95 | 513 | |
3d1228ea CM |
514 | put_cpu(); |
515 | } | |
3d1228ea | 516 | |
90b44199 RK |
517 | /* |
518 | * VFP hardware can lose all context when a CPU goes offline. | |
74c25bee RK |
519 | * As we will be running in SMP mode with CPU hotplug, we will save the |
520 | * hardware state at every thread switch. We clear our held state when | |
521 | * a CPU has been killed, indicating that the VFP hardware doesn't contain | |
522 | * a threads VFP state. When a CPU starts up, we re-enable access to the | |
523 | * VFP hardware. | |
90b44199 RK |
524 | * |
525 | * Both CPU_DYING and CPU_STARTING are called on the CPU which | |
526 | * is being offlined/onlined. | |
527 | */ | |
528 | static int vfp_hotplug(struct notifier_block *b, unsigned long action, | |
529 | void *hcpu) | |
530 | { | |
531 | if (action == CPU_DYING || action == CPU_DYING_FROZEN) { | |
f8f2a852 | 532 | vfp_force_reload((long)hcpu, current_thread_info()); |
90b44199 RK |
533 | } else if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) |
534 | vfp_enable(NULL); | |
535 | return NOTIFY_OK; | |
536 | } | |
8e140362 | 537 | |
1da177e4 LT |
538 | /* |
539 | * VFP support code initialisation. | |
540 | */ | |
541 | static int __init vfp_init(void) | |
542 | { | |
543 | unsigned int vfpsid; | |
efe90d27 | 544 | unsigned int cpu_arch = cpu_architecture(); |
efe90d27 | 545 | |
c98929c0 CM |
546 | if (cpu_arch >= CPU_ARCH_ARMv6) |
547 | vfp_enable(NULL); | |
1da177e4 LT |
548 | |
549 | /* | |
550 | * First check that there is a VFP that we can use. | |
551 | * The handler is already setup to just log calls, so | |
552 | * we just need to read the VFPSID register. | |
553 | */ | |
5d4cae5f | 554 | vfp_vector = vfp_testing_entry; |
b9338a78 | 555 | barrier(); |
1da177e4 | 556 | vfpsid = fmrx(FPSID); |
8e140362 | 557 | barrier(); |
5d4cae5f | 558 | vfp_vector = vfp_null_entry; |
1da177e4 LT |
559 | |
560 | printk(KERN_INFO "VFP support v0.3: "); | |
c98929c0 | 561 | if (VFP_arch) |
1da177e4 | 562 | printk("not present\n"); |
c98929c0 | 563 | else if (vfpsid & FPSID_NODOUBLE) { |
1da177e4 LT |
564 | printk("no double precision support\n"); |
565 | } else { | |
90b44199 RK |
566 | hotcpu_notifier(vfp_hotplug, 0); |
567 | ||
8691e5a8 | 568 | smp_call_function(vfp_enable, NULL, 1); |
8e140362 | 569 | |
1da177e4 LT |
570 | VFP_arch = (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT; /* Extract the architecture version */ |
571 | printk("implementor %02x architecture %d part %02x variant %x rev %x\n", | |
572 | (vfpsid & FPSID_IMPLEMENTER_MASK) >> FPSID_IMPLEMENTER_BIT, | |
573 | (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT, | |
574 | (vfpsid & FPSID_PART_MASK) >> FPSID_PART_BIT, | |
575 | (vfpsid & FPSID_VARIANT_MASK) >> FPSID_VARIANT_BIT, | |
576 | (vfpsid & FPSID_REV_MASK) >> FPSID_REV_BIT); | |
efe90d27 | 577 | |
1da177e4 | 578 | vfp_vector = vfp_support_entry; |
d6551e88 RK |
579 | |
580 | thread_register_notifier(&vfp_notifier_block); | |
fc0b7a20 | 581 | vfp_pm_init(); |
efe90d27 RK |
582 | |
583 | /* | |
584 | * We detected VFP, and the support code is | |
585 | * in place; report VFP support to userspace. | |
586 | */ | |
587 | elf_hwcap |= HWCAP_VFP; | |
7279dc3e | 588 | #ifdef CONFIG_VFPv3 |
325ffc36 | 589 | if (VFP_arch >= 2) { |
7279dc3e CM |
590 | elf_hwcap |= HWCAP_VFPv3; |
591 | ||
592 | /* | |
593 | * Check for VFPv3 D16. CPUs in this configuration | |
594 | * only have 16 x 64bit registers. | |
595 | */ | |
596 | if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK)) == 1) | |
597 | elf_hwcap |= HWCAP_VFPv3D16; | |
598 | } | |
599 | #endif | |
2bedbdf4 CM |
600 | /* |
601 | * Check for the presence of the Advanced SIMD | |
602 | * load/store instructions, integer and single | |
5aaf2544 TL |
603 | * precision floating point operations. Only check |
604 | * for NEON if the hardware has the MVFR registers. | |
2bedbdf4 | 605 | */ |
5aaf2544 | 606 | if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) { |
18b9dc13 | 607 | #ifdef CONFIG_NEON |
5aaf2544 TL |
608 | if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100) |
609 | elf_hwcap |= HWCAP_NEON; | |
2bedbdf4 | 610 | #endif |
18b9dc13 WD |
611 | if ((fmrx(MVFR1) & 0xf0000000) == 0x10000000) |
612 | elf_hwcap |= HWCAP_VFPv4; | |
613 | } | |
1da177e4 LT |
614 | } |
615 | return 0; | |
616 | } | |
617 | ||
618 | late_initcall(vfp_init); |