Commit | Line | Data |
---|---|---|
bbe88886 CM |
1 | /* |
2 | * linux/arch/arm/mm/proc-v7.S | |
3 | * | |
4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This is the "shell" of the ARMv7 processor support. | |
11 | */ | |
991da17e | 12 | #include <linux/init.h> |
bbe88886 CM |
13 | #include <linux/linkage.h> |
14 | #include <asm/assembler.h> | |
15 | #include <asm/asm-offsets.h> | |
5ec9407d | 16 | #include <asm/hwcap.h> |
bbe88886 CM |
17 | #include <asm/pgtable-hwdef.h> |
18 | #include <asm/pgtable.h> | |
6fa3eb70 | 19 | #include <asm/vfpmacros.h> |
bbe88886 CM |
20 | |
21 | #include "proc-macros.S" | |
22 | ||
1b6ba46b CM |
23 | #ifdef CONFIG_ARM_LPAE |
24 | #include "proc-v7-3level.S" | |
25 | #else | |
8d2cd3a3 | 26 | #include "proc-v7-2level.S" |
1b6ba46b | 27 | #endif |
73b63efa | 28 | |
bbe88886 CM |
29 | ENTRY(cpu_v7_proc_init) |
30 | mov pc, lr | |
93ed3970 | 31 | ENDPROC(cpu_v7_proc_init) |
bbe88886 CM |
32 | |
33 | ENTRY(cpu_v7_proc_fin) | |
1f667c69 TL |
34 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register |
35 | bic r0, r0, #0x1000 @ ...i............ | |
36 | bic r0, r0, #0x0006 @ .............ca. | |
37 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | |
9ca03a21 | 38 | mov pc, lr |
93ed3970 | 39 | ENDPROC(cpu_v7_proc_fin) |
bbe88886 CM |
40 | |
41 | /* | |
42 | * cpu_v7_reset(loc) | |
43 | * | |
44 | * Perform a soft reset of the system. Put the CPU into the | |
45 | * same state as it would be if it had been reset, and branch | |
46 | * to what would be the reset vector. | |
47 | * | |
48 | * - loc - location to jump to for soft reset | |
f4daf06f WD |
49 | * |
50 | * This code must be executed using a flat identity mapping with | |
51 | * caches disabled. | |
bbe88886 CM |
52 | */ |
53 | .align 5 | |
1a4baafa | 54 | .pushsection .idmap.text, "ax" |
bbe88886 | 55 | ENTRY(cpu_v7_reset) |
f4daf06f WD |
56 | mrc p15, 0, r1, c1, c0, 0 @ ctrl register |
57 | bic r1, r1, #0x1 @ ...............m | |
0f81bb6b | 58 | THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions) |
f4daf06f WD |
59 | mcr p15, 0, r1, c1, c0, 0 @ disable MMU |
60 | isb | |
153cd8e8 | 61 | bx r0 |
93ed3970 | 62 | ENDPROC(cpu_v7_reset) |
1a4baafa | 63 | .popsection |
bbe88886 CM |
64 | |
65 | /* | |
66 | * cpu_v7_do_idle() | |
67 | * | |
68 | * Idle the processor (eg, wait for interrupt). | |
69 | * | |
70 | * IRQs are already disabled. | |
71 | */ | |
72 | ENTRY(cpu_v7_do_idle) | |
8553cb67 | 73 | dsb @ WFI may enter a low-power mode |
000b5025 | 74 | wfi |
bbe88886 | 75 | mov pc, lr |
93ed3970 | 76 | ENDPROC(cpu_v7_do_idle) |
bbe88886 CM |
77 | |
78 | ENTRY(cpu_v7_dcache_clean_area) | |
34063113 WD |
79 | ALT_SMP(W(nop)) @ MP extensions imply L1 PTW |
80 | ALT_UP_B(1f) | |
81 | mov pc, lr | |
82 | 1: dcache_line_size r2, r3 | |
6fa3eb70 S |
83 | #ifdef CONFIG_ARM_ERRATA_824069 |
84 | 2: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry | |
85 | #else | |
34063113 | 86 | 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
6fa3eb70 | 87 | #endif |
bbe88886 CM |
88 | add r0, r0, r2 |
89 | subs r1, r1, r2 | |
34063113 | 90 | bhi 2b |
bbe88886 | 91 | dsb |
bbe88886 | 92 | mov pc, lr |
93ed3970 | 93 | ENDPROC(cpu_v7_dcache_clean_area) |
bbe88886 | 94 | |
78a8f3c3 | 95 | string cpu_v7_name, "ARMv7 Processor" |
bbe88886 CM |
96 | .align |
97 | ||
6fa3eb70 S |
98 | #define A53_IMPLEMENTATION_DEFINED |
99 | ||
100 | #if !defined (A53_IMPLEMENTATION_DEFINED) | |
101 | #define A53_IMPL_SIZE (0) | |
102 | #else //#if !defined (A53_IMPLEMENTATION_DEFINED) | |
103 | #define A53_IMPL_SIZE (4) | |
104 | #endif //#if !defined (A53_IMPLEMENTATION_DEFINED) | |
105 | ||
f6b0fa02 RK |
106 | /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ |
107 | .globl cpu_v7_suspend_size | |
6fa3eb70 S |
108 | .equ cpu_v7_suspend_size, 4 * (11 + A53_IMPL_SIZE) |
109 | ||
15e0d9e3 | 110 | #ifdef CONFIG_ARM_CPU_SUSPEND |
f6b0fa02 | 111 | ENTRY(cpu_v7_do_suspend) |
6fa3eb70 | 112 | stmfd sp!, {r4 - r11, lr} |
f6b0fa02 | 113 | mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID |
6fa3eb70 S |
114 | @ mrc p15, 0, r4, c13, c0, 1 @ CONTEXTIDR should be 0, instead of restored. |
115 | mrc p15, 0, r5, c13, c0, 2 @ TPIDRURW | |
116 | mrc p15, 0, r6, c13, c0, 3 @ TPIDRURO | |
117 | mrc p15, 0, r7, c13, c0, 4 @ TPIDRPRW | |
118 | stmia r0!, {r4 - r7} | |
f6b0fa02 | 119 | mrc p15, 0, r6, c3, c0, 0 @ Domain ID |
6fa3eb70 S |
120 | #ifdef CONFIG_ARM_LPAE |
121 | mrrc p15, 1, r5, r7, c2 @ TTB 1 | |
122 | #else | |
de8e71ca | 123 | mrc p15, 0, r7, c2, c0, 1 @ TTB 1 |
6fa3eb70 | 124 | #endif |
1b6ba46b | 125 | mrc p15, 0, r11, c2, c0, 2 @ TTB control register |
de8e71ca RK |
126 | mrc p15, 0, r8, c1, c0, 0 @ Control register |
127 | mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register | |
128 | mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control | |
6fa3eb70 S |
129 | stmia r0!, {r5 - r11} |
130 | ||
131 | #if defined (A53_IMPLEMENTATION_DEFINED) | |
132 | @@ extention for a53's implementation defined register | |
133 | MRC p15, 0, r9, c0, c0, 0 @ MIDR | |
134 | movw r10, #0xfff0 | |
135 | movt r10, #0xff0f | |
136 | and r9, r10 | |
137 | movw r10, #0xD030 | |
138 | movt r10, #0x410F | |
139 | teq r9, r10 | |
140 | bne 1f | |
141 | MRRC p15, 0, r4, r5, c15 @ Read CPU Auxiliary Control Register | |
142 | MRRC p15, 1, r6, r7, c15 @ Read CPU Extended Control Register | |
143 | stmia r0!, {r4 - r7} | |
144 | #endif //#if defined (A53_IMPLEMENTATION_DEFINED) | |
145 | ||
146 | 1: ldmfd sp!, {r4 - r11, pc} | |
f6b0fa02 RK |
147 | ENDPROC(cpu_v7_do_suspend) |
148 | ||
6fa3eb70 | 149 | /*** R1 is argument and reserved as TTBR1 **/ |
f6b0fa02 RK |
150 | ENTRY(cpu_v7_do_resume) |
151 | mov ip, #0 | |
f6b0fa02 | 152 | mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache |
6fa3eb70 | 153 | ldmia r0!, {r4 - r7} |
f6b0fa02 | 154 | mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID |
6fa3eb70 S |
155 | @ mcr p15, 0, r4, c13, c0, 1 @ CONTEXTIDR |
156 | mcr p15, 0, r5, c13, c0, 2 @ TPIDRURW | |
157 | mcr p15, 0, r6, c13, c0, 3 @ TPIDRURO | |
158 | mcr p15, 0, r7, c13, c0, 4 @ TPIDRPRW | |
159 | ldmia r0!, {r5 - r11} | |
160 | mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs | |
f6b0fa02 | 161 | mcr p15, 0, r6, c3, c0, 0 @ Domain ID |
6fa3eb70 S |
162 | #ifdef CONFIG_ARM_LPAE |
163 | mcrr p15, 0, r1, ip, c2 @ TTB 0 | |
164 | mcrr p15, 1, r5, r7, c2 @ TTB 1 | |
165 | #else | |
de8e71ca RK |
166 | ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) |
167 | ALT_UP(orr r1, r1, #TTB_FLAGS_UP) | |
168 | mcr p15, 0, r1, c2, c0, 0 @ TTB 0 | |
169 | mcr p15, 0, r7, c2, c0, 1 @ TTB 1 | |
6fa3eb70 | 170 | #endif |
1b6ba46b | 171 | mcr p15, 0, r11, c2, c0, 2 @ TTB control register |
25904157 | 172 | mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register |
de8e71ca RK |
173 | teq r4, r9 @ Is it already set? |
174 | mcrne p15, 0, r9, c1, c0, 1 @ No, so write it | |
175 | mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control | |
6fa3eb70 S |
176 | /**!! R8 is reserved and keeping CTLR !! **/ |
177 | /**!! R8 is reserved and keeping CTLR !! **/ | |
178 | ||
179 | #if defined (A53_IMPLEMENTATION_DEFINED) | |
180 | @@ extention for a53's implementation defined register | |
181 | MRC p15, 0, r9, c0, c0, 0 @ MIDR | |
182 | movw r10, #0xfff0 | |
183 | movt r10, #0xff0f | |
184 | and r9, r10 | |
185 | movw r10, #0xD030 | |
186 | movt r10, #0x410F | |
187 | teq r9, r10 | |
188 | bne 1f | |
189 | ldmia r0!, {r4 - r7} | |
190 | /* MCRR p15, 0, r4, r5, c15 @ Write CPU Auxiliary Control Register */ | |
191 | MCRR p15, 1, r6, r7, c15 @ write CPU Extended Control Register | |
192 | 1: dsb | |
193 | #endif //#if defined (A53_IMPLEMENTATION_DEFINED) | |
194 | ||
f6b0fa02 RK |
195 | ldr r4, =PRRR @ PRRR |
196 | ldr r5, =NMRR @ NMRR | |
197 | mcr p15, 0, r4, c10, c2, 0 @ write PRRR | |
198 | mcr p15, 0, r5, c10, c2, 1 @ write NMRR | |
199 | isb | |
f35235a3 | 200 | dsb |
de8e71ca | 201 | mov r0, r8 @ control register |
f6b0fa02 RK |
202 | b cpu_resume_mmu |
203 | ENDPROC(cpu_v7_do_resume) | |
3e0a07f8 GC |
204 | #endif |
205 | ||
206 | #ifdef CONFIG_CPU_PJ4B | |
207 | globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm | |
208 | globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext | |
209 | globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init | |
210 | globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin | |
211 | globl_equ cpu_pj4b_reset, cpu_v7_reset | |
212 | #ifdef CONFIG_PJ4B_ERRATA_4742 | |
213 | ENTRY(cpu_pj4b_do_idle) | |
214 | dsb @ WFI may enter a low-power mode | |
215 | wfi | |
216 | dsb @barrier | |
217 | mov pc, lr | |
218 | ENDPROC(cpu_pj4b_do_idle) | |
219 | #else | |
220 | globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle | |
221 | #endif | |
222 | globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area | |
223 | globl_equ cpu_pj4b_do_suspend, cpu_v7_do_suspend | |
224 | globl_equ cpu_pj4b_do_resume, cpu_v7_do_resume | |
225 | globl_equ cpu_pj4b_suspend_size, cpu_v7_suspend_size | |
226 | ||
f6b0fa02 RK |
227 | #endif |
228 | ||
5085f3ff | 229 | __CPUINIT |
bbe88886 CM |
230 | |
231 | /* | |
232 | * __v7_setup | |
233 | * | |
234 | * Initialise TLB, Caches, and MMU state ready to switch the MMU | |
235 | * on. Return in r0 the new CP15 C1 control register setting. | |
236 | * | |
bbe88886 CM |
237 | * This should be able to cover all ARMv7 cores. |
238 | * | |
239 | * It is assumed that: | |
240 | * - cache type register is implemented | |
241 | */ | |
15eb169b | 242 | __v7_ca5mp_setup: |
14eff181 | 243 | __v7_ca9mp_setup: |
7665d9d2 WD |
244 | mov r10, #(1 << 0) @ TLB ops broadcasting |
245 | b 1f | |
b4244738 | 246 | __v7_ca7mp_setup: |
6fa3eb70 | 247 | __v7_ca12mp_setup: |
7665d9d2 | 248 | __v7_ca15mp_setup: |
6fa3eb70 | 249 | __v7_ca17mp_setup: |
7665d9d2 WD |
250 | mov r10, #0 |
251 | 1: | |
6fa3eb70 S |
252 | #ifdef CONFIG_VFP_OPT |
253 | @ enable CP10 / CP11 access right | |
254 | ldr r0, =(0xF << 20) | |
255 | mcr p15, 0, r0, c1, c0, 2 | |
256 | orr r0, r0, #FPEXC_EN @ user FPEXC has the enable bit set | |
257 | bic r0, r0, #FPEXC_EX @ make sure exceptions are disabled | |
258 | VFPFMXR FPEXC, r0 @ enable VFP, disable any pending | |
259 | @ exceptions, so we can get at the | |
260 | @ rest of it | |
261 | #endif | |
73b63efa | 262 | #ifdef CONFIG_SMP |
f00ec48f RK |
263 | ALT_SMP(mrc p15, 0, r0, c1, c0, 1) |
264 | ALT_UP(mov r0, #(1 << 6)) @ fake it for UP | |
1b3a02eb | 265 | tst r0, #(1 << 6) @ SMP/nAMP mode enabled? |
7665d9d2 WD |
266 | orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode |
267 | orreq r0, r0, r10 @ Enable CPU-specific SMP bits | |
268 | mcreq p15, 0, r0, c1, c0, 1 | |
73b63efa | 269 | #endif |
d106de38 | 270 | b __v7_setup |
de490193 | 271 | |
6fa3eb70 S |
272 | __v7_ca53mp_setup: |
273 | mov r10, #0 | |
274 | #ifdef CONFIG_VFP_OPT | |
275 | @ enable CP10 / CP11 access right | |
276 | ldr r0, =(0xF << 20) | |
277 | mcr p15, 0, r0, c1, c0, 2 | |
278 | orr r0, r0, #FPEXC_EN @ user FPEXC has the enable bit set | |
279 | bic r0, r0, #FPEXC_EX @ make sure exceptions are disabled | |
280 | VFPFMXR FPEXC, r0 @ enable VFP, disable any pending | |
281 | @ exceptions, so we can get at the | |
282 | @ rest of it | |
283 | #endif | |
284 | #ifdef CONFIG_SMP | |
285 | ALT_SMP(mrrc p15, 1, r0, r1, c15) | |
286 | ALT_UP(mov r0, #(1 << 6)) @ fake it for UP | |
287 | tst r0, #(1 << 6) @ SMP/nAMP mode enabled? | |
288 | orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode | |
289 | orreq r0, r0, r10 @ Enable CPU-specific SMP bits | |
290 | mcrreq p15, 1, r0, r1, c15 | |
291 | #endif | |
292 | b __v7_setup | |
293 | ||
de490193 GC |
294 | __v7_pj4b_setup: |
295 | #ifdef CONFIG_CPU_PJ4B | |
296 | ||
297 | /* Auxiliary Debug Modes Control 1 Register */ | |
298 | #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */ | |
299 | #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */ | |
de490193 GC |
300 | #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */ |
301 | ||
302 | /* Auxiliary Debug Modes Control 2 Register */ | |
303 | #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */ | |
304 | #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */ | |
305 | #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */ | |
306 | #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */ | |
307 | #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */ | |
308 | #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\ | |
309 | PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR) | |
310 | ||
311 | /* Auxiliary Functional Modes Control Register 0 */ | |
312 | #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */ | |
313 | #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */ | |
314 | #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */ | |
315 | ||
316 | /* Auxiliary Debug Modes Control 0 Register */ | |
317 | #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */ | |
318 | ||
319 | /* Auxiliary Debug Modes Control 1 Register */ | |
320 | mrc p15, 1, r0, c15, c1, 1 | |
321 | orr r0, r0, #PJ4B_CLEAN_LINE | |
de490193 GC |
322 | orr r0, r0, #PJ4B_INTER_PARITY |
323 | bic r0, r0, #PJ4B_STATIC_BP | |
324 | mcr p15, 1, r0, c15, c1, 1 | |
325 | ||
326 | /* Auxiliary Debug Modes Control 2 Register */ | |
327 | mrc p15, 1, r0, c15, c1, 2 | |
328 | bic r0, r0, #PJ4B_FAST_LDR | |
329 | orr r0, r0, #PJ4B_AUX_DBG_CTRL2 | |
330 | mcr p15, 1, r0, c15, c1, 2 | |
331 | ||
332 | /* Auxiliary Functional Modes Control Register 0 */ | |
333 | mrc p15, 1, r0, c15, c2, 0 | |
334 | #ifdef CONFIG_SMP | |
335 | orr r0, r0, #PJ4B_SMP_CFB | |
336 | #endif | |
337 | orr r0, r0, #PJ4B_L1_PAR_CHK | |
338 | orr r0, r0, #PJ4B_BROADCAST_CACHE | |
339 | mcr p15, 1, r0, c15, c2, 0 | |
340 | ||
341 | /* Auxiliary Debug Modes Control 0 Register */ | |
342 | mrc p15, 1, r0, c15, c1, 0 | |
343 | orr r0, r0, #PJ4B_WFI_WFE | |
344 | mcr p15, 1, r0, c15, c1, 0 | |
345 | ||
346 | #endif /* CONFIG_CPU_PJ4B */ | |
347 | ||
14eff181 | 348 | __v7_setup: |
bbe88886 CM |
349 | adr r12, __v7_setup_stack @ the local stack |
350 | stmia r12, {r0-r5, r7, r9, r11, lr} | |
6323fa22 | 351 | bl v7_flush_dcache_louis |
bbe88886 | 352 | ldmia r12, {r0-r5, r7, r9, r11, lr} |
1946d6ef RK |
353 | |
354 | mrc p15, 0, r0, c0, c0, 0 @ read main ID register | |
355 | and r10, r0, #0xff000000 @ ARM? | |
356 | teq r10, #0x41000000 | |
9f05027c | 357 | bne 3f |
1946d6ef RK |
358 | and r5, r0, #0x00f00000 @ variant |
359 | and r6, r0, #0x0000000f @ revision | |
6491848d WD |
360 | orr r6, r6, r5, lsr #20-4 @ combine variant and revision |
361 | ubfx r0, r0, #4, #12 @ primary part number | |
1946d6ef | 362 | |
6491848d WD |
363 | /* Cortex-A8 Errata */ |
364 | ldr r10, =0x00000c08 @ Cortex-A8 primary part number | |
365 | teq r0, r10 | |
366 | bne 2f | |
62e4d357 RH |
367 | #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM) |
368 | ||
1946d6ef RK |
369 | teq r5, #0x00100000 @ only present in r1p* |
370 | mrceq p15, 0, r10, c1, c0, 1 @ read aux control register | |
371 | orreq r10, r10, #(1 << 6) @ set IBE to 1 | |
372 | mcreq p15, 0, r10, c1, c0, 1 @ write aux control register | |
855c551f CM |
373 | #endif |
374 | #ifdef CONFIG_ARM_ERRATA_458693 | |
6491848d | 375 | teq r6, #0x20 @ only present in r2p0 |
1946d6ef RK |
376 | mrceq p15, 0, r10, c1, c0, 1 @ read aux control register |
377 | orreq r10, r10, #(1 << 5) @ set L1NEON to 1 | |
378 | orreq r10, r10, #(1 << 9) @ set PLDNOP to 1 | |
379 | mcreq p15, 0, r10, c1, c0, 1 @ write aux control register | |
0516e464 CM |
380 | #endif |
381 | #ifdef CONFIG_ARM_ERRATA_460075 | |
6491848d | 382 | teq r6, #0x20 @ only present in r2p0 |
1946d6ef RK |
383 | mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register |
384 | tsteq r10, #1 << 22 | |
385 | orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit | |
386 | mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register | |
7ce236fc | 387 | #endif |
9f05027c WD |
388 | b 3f |
389 | ||
390 | /* Cortex-A9 Errata */ | |
391 | 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number | |
392 | teq r0, r10 | |
393 | bne 3f | |
394 | #ifdef CONFIG_ARM_ERRATA_742230 | |
395 | cmp r6, #0x22 @ only present up to r2p2 | |
396 | mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register | |
397 | orrle r10, r10, #1 << 4 @ set bit #4 | |
398 | mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register | |
399 | #endif | |
a672e99b WD |
400 | #ifdef CONFIG_ARM_ERRATA_742231 |
401 | teq r6, #0x20 @ present in r2p0 | |
402 | teqne r6, #0x21 @ present in r2p1 | |
403 | teqne r6, #0x22 @ present in r2p2 | |
404 | mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register | |
405 | orreq r10, r10, #1 << 12 @ set bit #12 | |
406 | orreq r10, r10, #1 << 22 @ set bit #22 | |
407 | mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register | |
408 | #endif | |
475d92fc | 409 | #ifdef CONFIG_ARM_ERRATA_743622 |
efbc74ac | 410 | teq r5, #0x00200000 @ only present in r2p* |
475d92fc WD |
411 | mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register |
412 | orreq r10, r10, #1 << 6 @ set bit #6 | |
413 | mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register | |
414 | #endif | |
ba90c516 DM |
415 | #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP) |
416 | ALT_SMP(cmp r6, #0x30) @ present prior to r3p0 | |
417 | ALT_UP_B(1f) | |
9a27c27c WD |
418 | mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register |
419 | orrlt r10, r10, #1 << 11 @ set bit #11 | |
420 | mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register | |
ba90c516 | 421 | 1: |
9a27c27c | 422 | #endif |
1946d6ef | 423 | |
9f05027c | 424 | 3: mov r10, #0 |
bbe88886 | 425 | mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate |
2eb8c82b | 426 | #ifdef CONFIG_MMU |
bbe88886 | 427 | mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs |
6fa3eb70 S |
428 | #ifdef CONFIG_ARM_ERRATA_831171 |
429 | mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs | |
430 | #endif | |
8d2cd3a3 | 431 | v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup |
f6b0fa02 RK |
432 | ldr r5, =PRRR @ PRRR |
433 | ldr r6, =NMRR @ NMRR | |
3f69c0c1 RK |
434 | mcr p15, 0, r5, c10, c2, 0 @ write PRRR |
435 | mcr p15, 0, r6, c10, c2, 1 @ write NMRR | |
078c0454 | 436 | #endif |
1266f2d3 | 437 | dsb @ Complete invalidations |
078c0454 JA |
438 | #ifndef CONFIG_ARM_THUMBEE |
439 | mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE | |
440 | and r0, r0, #(0xf << 12) @ ThumbEE enabled field | |
441 | teq r0, #(1 << 12) @ check if ThumbEE is present | |
442 | bne 1f | |
443 | mov r5, #0 | |
444 | mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0 | |
445 | mrc p14, 6, r0, c0, c0, 0 @ load TEECR | |
446 | orr r0, r0, #1 @ set the 1st bit in order to | |
447 | mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access | |
448 | 1: | |
bdaaaec3 | 449 | #endif |
2eb8c82b CM |
450 | adr r5, v7_crval |
451 | ldmia r5, {r5, r6} | |
26584853 CM |
452 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
453 | orr r6, r6, #1 << 25 @ big-endian page tables | |
64d2dc38 LL |
454 | #endif |
455 | #ifdef CONFIG_SWP_EMULATE | |
456 | orr r5, r5, #(1 << 10) @ set SW bit in "clear" | |
457 | bic r6, r6, #(1 << 10) @ clear it in "mmuset" | |
26584853 | 458 | #endif |
2eb8c82b CM |
459 | mrc p15, 0, r0, c1, c0, 0 @ read control register |
460 | bic r0, r0, r5 @ clear bits them | |
461 | orr r0, r0, r6 @ set them | |
347c8b70 | 462 | THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions |
bbe88886 | 463 | mov pc, lr @ return to head.S:__ret |
93ed3970 | 464 | ENDPROC(__v7_setup) |
bbe88886 | 465 | |
8d2cd3a3 | 466 | .align 2 |
bbe88886 CM |
467 | __v7_setup_stack: |
468 | .space 4 * 11 @ 11 registers | |
469 | ||
5085f3ff RK |
470 | __INITDATA |
471 | ||
78a8f3c3 DM |
472 | @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) |
473 | define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 | |
3e0a07f8 GC |
474 | #ifdef CONFIG_CPU_PJ4B |
475 | define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 | |
476 | #endif | |
bbe88886 | 477 | |
5085f3ff RK |
478 | .section ".rodata" |
479 | ||
78a8f3c3 DM |
480 | string cpu_arch_name, "armv7" |
481 | string cpu_elf_name, "v7" | |
bbe88886 CM |
482 | .align |
483 | ||
484 | .section ".proc.info.init", #alloc, #execinstr | |
485 | ||
dc939cd8 PM |
486 | /* |
487 | * Standard v7 proc info content | |
488 | */ | |
3e0a07f8 | 489 | .macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions |
dc939cd8 | 490 | ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ |
1b6ba46b | 491 | PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags) |
dc939cd8 | 492 | ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ |
1b6ba46b CM |
493 | PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags) |
494 | .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \ | |
495 | PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags | |
dc939cd8 | 496 | W(b) \initfunc |
14eff181 DW |
497 | .long cpu_arch_name |
498 | .long cpu_elf_name | |
dc939cd8 PM |
499 | .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \ |
500 | HWCAP_EDSP | HWCAP_TLS | \hwcaps | |
14eff181 | 501 | .long cpu_v7_name |
3e0a07f8 | 502 | .long \proc_fns |
14eff181 DW |
503 | .long v7wbi_tlb_fns |
504 | .long v6_user_fns | |
505 | .long v7_cache_fns | |
dc939cd8 PM |
506 | .endm |
507 | ||
1b6ba46b | 508 | #ifndef CONFIG_ARM_LPAE |
15eb169b PM |
509 | /* |
510 | * ARM Ltd. Cortex A5 processor. | |
511 | */ | |
512 | .type __v7_ca5mp_proc_info, #object | |
513 | __v7_ca5mp_proc_info: | |
514 | .long 0x410fc050 | |
515 | .long 0xff0ffff0 | |
516 | __v7_proc __v7_ca5mp_setup | |
517 | .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info | |
518 | ||
dc939cd8 PM |
519 | /* |
520 | * ARM Ltd. Cortex A9 processor. | |
521 | */ | |
522 | .type __v7_ca9mp_proc_info, #object | |
523 | __v7_ca9mp_proc_info: | |
524 | .long 0x410fc090 | |
525 | .long 0xff0ffff0 | |
526 | __v7_proc __v7_ca9mp_setup | |
14eff181 | 527 | .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info |
de490193 | 528 | |
b361d61d GC |
529 | #endif /* CONFIG_ARM_LPAE */ |
530 | ||
de490193 GC |
531 | /* |
532 | * Marvell PJ4B processor. | |
533 | */ | |
3e0a07f8 | 534 | #ifdef CONFIG_CPU_PJ4B |
de490193 GC |
535 | .type __v7_pj4b_proc_info, #object |
536 | __v7_pj4b_proc_info: | |
049be070 GC |
537 | .long 0x560f5800 |
538 | .long 0xff0fff00 | |
3e0a07f8 | 539 | __v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions |
de490193 | 540 | .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info |
3e0a07f8 | 541 | #endif |
14eff181 | 542 | |
868dbf90 WD |
543 | /* |
544 | * ARM Ltd. Cortex A7 processor. | |
545 | */ | |
546 | .type __v7_ca7mp_proc_info, #object | |
547 | __v7_ca7mp_proc_info: | |
548 | .long 0x410fc070 | |
549 | .long 0xff0ffff0 | |
8164f7af | 550 | __v7_proc __v7_ca7mp_setup |
868dbf90 WD |
551 | .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info |
552 | ||
6fa3eb70 S |
553 | /* |
554 | * ARM Ltd. Cortex A12 processor. | |
555 | */ | |
556 | .type __v7_ca12mp_proc_info, #object | |
557 | __v7_ca12mp_proc_info: | |
558 | .long 0x410fc0d0 | |
559 | .long 0xff0ffff0 | |
560 | __v7_proc __v7_ca12mp_setup | |
561 | .size __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info | |
562 | ||
563 | ||
7665d9d2 WD |
564 | /* |
565 | * ARM Ltd. Cortex A15 processor. | |
566 | */ | |
567 | .type __v7_ca15mp_proc_info, #object | |
568 | __v7_ca15mp_proc_info: | |
569 | .long 0x410fc0f0 | |
570 | .long 0xff0ffff0 | |
8164f7af | 571 | __v7_proc __v7_ca15mp_setup |
7665d9d2 WD |
572 | .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info |
573 | ||
6fa3eb70 S |
574 | /* |
575 | * ARM Ltd. Cortex A17 processor. | |
576 | */ | |
577 | .type __v7_ca17mp_proc_info, #object | |
578 | __v7_ca17mp_proc_info: | |
579 | .long 0x410fc0e0 | |
580 | .long 0xff0ffff0 | |
581 | __v7_proc __v7_ca17mp_setup | |
582 | .size __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info | |
583 | ||
584 | .type __v7_ca53mp_proc_info, #object | |
585 | __v7_ca53mp_proc_info: | |
586 | .long 0x410FD030 | |
587 | .long 0xff0ffff0 | |
588 | __v7_proc __v7_ca53mp_setup | |
589 | .size __v7_ca53mp_proc_info, . - __v7_ca53mp_proc_info | |
590 | ||
120ecfaf SM |
591 | /* |
592 | * Qualcomm Inc. Krait processors. | |
593 | */ | |
594 | .type __krait_proc_info, #object | |
595 | __krait_proc_info: | |
596 | .long 0x510f0400 @ Required ID value | |
597 | .long 0xff0ffc00 @ Mask for ID | |
598 | /* | |
599 | * Some Krait processors don't indicate support for SDIV and UDIV | |
600 | * instructions in the ARM instruction set, even though they actually | |
601 | * do support them. | |
602 | */ | |
603 | __v7_proc __v7_setup, hwcaps = HWCAP_IDIV | |
604 | .size __krait_proc_info, . - __krait_proc_info | |
605 | ||
bbe88886 CM |
606 | /* |
607 | * Match any ARMv7 processor core. | |
608 | */ | |
609 | .type __v7_proc_info, #object | |
610 | __v7_proc_info: | |
611 | .long 0x000f0000 @ Required ID value | |
612 | .long 0x000f0000 @ Mask for ID | |
dc939cd8 | 613 | __v7_proc __v7_setup |
bbe88886 | 614 | .size __v7_proc_info, . - __v7_proc_info |