[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mm / proc-sa110.S

/*
 *  linux/arch/arm/mm/proc-sa110.S
 *
 *  Copyright (C) 1997-2002 Russell King
 *  hacked for non-paged-MM by Hyok S. Choi, 2003.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  MMU functions for SA110
 *
 *  These are the low level assembler for performing cache and TLB
 *  functions on the StrongARM-110.
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/procinfo.h>
#include <asm/hardware.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/ptrace.h>

/*
 * the cache line size of the I and D cache
 */
#define DCACHELINESIZE	32

	.text

/*
 * cpu_sa110_proc_init()
 */
ENTRY(cpu_sa110_proc_init)
	mov	r0, #0
	mcr	p15, 0, r0, c15, c1, 2		@ Enable clock switching
	mov	pc, lr

/*
 * cpu_sa110_proc_fin()
 */
ENTRY(cpu_sa110_proc_fin)
	stmfd	sp!, {lr}
	mov	ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
	msr	cpsr_c, ip
	bl	v4wb_flush_kern_cache_all	@ clean caches
1:	mov	r0, #0
	mcr	p15, 0, r0, c15, c2, 2		@ Disable clock switching
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x000e			@ ............wca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	ldmfd	sp!, {pc}

/*
 * cpu_sa110_reset(loc)
 *
 * Perform a soft reset of the system.  Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_sa110_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x000f			@ ............wcam
	bic	ip, ip, #0x1100			@ ...i...s........
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	mov	pc, r0

/*
 * cpu_sa110_do_idle(type)
 *
 * Cause the processor to idle
 *
 * type: call type:
 *   0 = slow idle
 *   1 = fast idle
 *   2 = switch to slow processor clock
 *   3 = switch to fast processor clock
 */
	.align	5

ENTRY(cpu_sa110_do_idle)
	mcr	p15, 0, ip, c15, c2, 2		@ disable clock switching
	ldr	r1, =UNCACHEABLE_ADDR		@ load from uncacheable loc
	ldr	r1, [r1, #0]			@ force switch to MCLK
	mov	r0, r0				@ safety
	mov	r0, r0				@ safety
	mov	r0, r0				@ safety
	mcr	p15, 0, r0, c15, c8, 2		@ Wait for interrupt, cache aligned
	mov	r0, r0				@ safety
	mov	r0, r0				@ safety
	mov	r0, r0				@ safety
	mcr	p15, 0, r0, c15, c1, 2		@ enable clock switching
	mov	pc, lr

/* ================================= CACHE ================================ */

/*
 * cpu_sa110_dcache_clean_area(addr,sz)
 *
 * Clean the specified entry of any caches such that the MMU
 * translation fetches will obtain correct data.
 *
 * addr: cache-unaligned virtual address
 */
	.align	5
ENTRY(cpu_sa110_dcache_clean_area)
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #DCACHELINESIZE
	subs	r1, r1, #DCACHELINESIZE
	bhi	1b
	mov	pc, lr

/* =============================== PageTable ============================== */

/*
 * cpu_sa110_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
ENTRY(cpu_sa110_switch_mm)
#ifdef CONFIG_MMU
	str	lr, [sp, #-4]!
	bl	v4wb_flush_kern_cache_all	@ clears IP
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
	ldr	pc, [sp], #4
#else
	mov	pc, lr
#endif

/*
 * cpu_sa110_set_pte(ptep, pte)
 *
 * Set a PTE and flush it out
 */
	.align	5
ENTRY(cpu_sa110_set_pte)
#ifdef CONFIG_MMU
	str	r1, [r0], #-2048		@ linux version

	eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY

	bic	r2, r1, #PTE_SMALL_AP_MASK
	bic	r2, r2, #PTE_TYPE_MASK
	orr	r2, r2, #PTE_TYPE_SMALL

	tst	r1, #L_PTE_USER			@ User?
	orrne	r2, r2, #PTE_SMALL_AP_URO_SRW

	tst	r1, #L_PTE_WRITE | L_PTE_DIRTY	@ Write and Dirty?
	orreq	r2, r2, #PTE_SMALL_AP_UNO_SRW

	tst	r1, #L_PTE_PRESENT | L_PTE_YOUNG	@ Present and Young?
	movne	r2, #0

	str	r2, [r0]			@ hardware version
	mov	r0, r0
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
#endif
	mov	pc, lr

	__INIT

	.type	__sa110_setup, #function
__sa110_setup:
	mov	r10, #0
	mcr	p15, 0, r10, c7, c7		@ invalidate I,D caches on v4
	mcr	p15, 0, r10, c7, c10, 4		@ drain write buffer on v4
#ifdef CONFIG_MMU
	mcr	p15, 0, r10, c8, c7		@ invalidate I,D TLBs on v4
#endif
	mrc	p15, 0, r0, c1, c0		@ get control register v4
	ldr	r5, sa110_cr1_clear
	bic	r0, r0, r5
	ldr	r5, sa110_cr1_set
	orr	r0, r0, r5
	mov	pc, lr
	.size	__sa110_setup, . - __sa110_setup

	/*
	 *  R
	 * .RVI ZFRS BLDP WCAM
	 * ..01 0001 ..11 1101
	 * 
	 */
	.type	sa110_cr1_clear, #object
	.type	sa110_cr1_set, #object
sa110_cr1_clear:
	.word	0x3f3f
sa110_cr1_set:
	.word	0x113d

	__INITDATA

/*
 * Purpose : Function pointers used to access above functions - all calls
 *	     come through these
 */

	.type	sa110_processor_functions, #object
ENTRY(sa110_processor_functions)
	.word	v4_early_abort
	.word	cpu_sa110_proc_init
	.word	cpu_sa110_proc_fin
	.word	cpu_sa110_reset
	.word	cpu_sa110_do_idle
	.word	cpu_sa110_dcache_clean_area
	.word	cpu_sa110_switch_mm
	.word	cpu_sa110_set_pte
	.size	sa110_processor_functions, . - sa110_processor_functions

	.section ".rodata"

	.type	cpu_arch_name, #object
cpu_arch_name:
	.asciz	"armv4"
	.size	cpu_arch_name, . - cpu_arch_name

	.type	cpu_elf_name, #object
cpu_elf_name:
	.asciz	"v4"
	.size	cpu_elf_name, . - cpu_elf_name

	.type	cpu_sa110_name, #object
cpu_sa110_name:
	.asciz	"StrongARM-110"
	.size	cpu_sa110_name, . - cpu_sa110_name

	.align

	.section ".proc.info.init", #alloc, #execinstr

	.type	__sa110_proc_info,#object
__sa110_proc_info:
	.long	0x4401a100
	.long	0xfffffff0
	.long   PMD_TYPE_SECT | \
		PMD_SECT_BUFFERABLE | \
		PMD_SECT_CACHEABLE | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long   PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__sa110_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
	.long	cpu_sa110_name
	.long	sa110_processor_functions
	.long	v4wb_tlb_fns
	.long	v4wb_user_fns
	.long	v4wb_cache_fns
	.size	__sa110_proc_info, . - __sa110_proc_info
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/proc-sa110.S
	3	*
	4	* Copyright (C) 1997-2002 Russell King
d090ddda	5	* hacked for non-paged-MM by Hyok S. Choi, 2003.
1da177e4 LT	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* MMU functions for SA110
	12	*
	13	* These are the low level assembler for performing cache and TLB
	14	* functions on the StrongARM-110.
	15	*/
	16	#include <linux/linkage.h>
	17	#include <linux/init.h>
	18	#include <asm/assembler.h>
e6ae744d	19	#include <asm/asm-offsets.h>
1da177e4 LT	20	#include <asm/procinfo.h>
1da177e4 LT	21	#include <asm/hardware.h>
74945c86	22	#include <asm/pgtable-hwdef.h>
1da177e4 LT	23	#include <asm/pgtable.h>
	24	#include <asm/ptrace.h>
	25
	26	/*
	27	* the cache line size of the I and D cache
	28	*/
	29	#define DCACHELINESIZE 32
95f3df6b	30
1da177e4 LT	31	.text
	32
	33	/*
	34	* cpu_sa110_proc_init()
	35	*/
	36	ENTRY(cpu_sa110_proc_init)
	37	mov r0, #0
	38	mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
	39	mov pc, lr
	40
	41	/*
	42	* cpu_sa110_proc_fin()
	43	*/
	44	ENTRY(cpu_sa110_proc_fin)
	45	stmfd sp!, {lr}
	46	mov ip, #PSR_F_BIT \| PSR_I_BIT \| SVC_MODE
	47	msr cpsr_c, ip
	48	bl v4wb_flush_kern_cache_all @ clean caches
	49	1: mov r0, #0
	50	mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
	51	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	52	bic r0, r0, #0x1000 @ ...i............
	53	bic r0, r0, #0x000e @ ............wca.
	54	mcr p15, 0, r0, c1, c0, 0 @ disable caches
	55	ldmfd sp!, {pc}
	56
	57	/*
	58	* cpu_sa110_reset(loc)
	59	*
	60	* Perform a soft reset of the system. Put the CPU into the
	61	* same state as it would be if it had been reset, and branch
	62	* to what would be the reset vector.
	63	*
	64	* loc: location to jump to for soft reset
	65	*/
	66	.align 5
	67	ENTRY(cpu_sa110_reset)
	68	mov ip, #0
	69	mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
	70	mcr p15, 0, ip, c7, c10, 4 @ drain WB
d090ddda	71	#ifdef CONFIG_MMU
1da177e4	72	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	73	#endif
1da177e4 LT	74	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	75	bic ip, ip, #0x000f @ ............wcam
	76	bic ip, ip, #0x1100 @ ...i...s........
	77	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
	78	mov pc, r0
	79
	80	/*
	81	* cpu_sa110_do_idle(type)
	82	*
	83	* Cause the processor to idle
	84	*
	85	* type: call type:
	86	* 0 = slow idle
	87	* 1 = fast idle
	88	* 2 = switch to slow processor clock
	89	* 3 = switch to fast processor clock
	90	*/
	91	.align 5
	92
	93	ENTRY(cpu_sa110_do_idle)
	94	mcr p15, 0, ip, c15, c2, 2 @ disable clock switching
	95	ldr r1, =UNCACHEABLE_ADDR @ load from uncacheable loc
	96	ldr r1, [r1, #0] @ force switch to MCLK
	97	mov r0, r0 @ safety
	98	mov r0, r0 @ safety
	99	mov r0, r0 @ safety
	100	mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
	101	mov r0, r0 @ safety
	102	mov r0, r0 @ safety
	103	mov r0, r0 @ safety
	104	mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
	105	mov pc, lr
	106
	107	/* ================================= CACHE ================================ */
	108
	109	/*
	110	* cpu_sa110_dcache_clean_area(addr,sz)
	111	*
	112	* Clean the specified entry of any caches such that the MMU
	113	* translation fetches will obtain correct data.
	114	*
	115	* addr: cache-unaligned virtual address
	116	*/
	117	.align 5
	118	ENTRY(cpu_sa110_dcache_clean_area)
	119	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	120	add r0, r0, #DCACHELINESIZE
	121	subs r1, r1, #DCACHELINESIZE
	122	bhi 1b
	123	mov pc, lr
	124
	125	/* =============================== PageTable ============================== */
	126
	127	/*
	128	* cpu_sa110_switch_mm(pgd)
	129	*
	130	* Set the translation base pointer to be as described by pgd.
	131	*
	132	* pgd: new page tables
	133	*/
	134	.align 5
	135	ENTRY(cpu_sa110_switch_mm)
d090ddda	136	#ifdef CONFIG_MMU
95f3df6b RK	137	str lr, [sp, #-4]!
95f3df6b RK	138	bl v4wb_flush_kern_cache_all @ clears IP
1da177e4	139	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
95f3df6b RK	140	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
95f3df6b RK	141	ldr pc, [sp], #4
d090ddda HC	142	#else
	143	mov pc, lr
	144	#endif
1da177e4 LT	145
	146	/*
	147	* cpu_sa110_set_pte(ptep, pte)
	148	*
	149	* Set a PTE and flush it out
	150	*/
	151	.align 5
	152	ENTRY(cpu_sa110_set_pte)
d090ddda	153	#ifdef CONFIG_MMU
1da177e4 LT	154	str r1, [r0], #-2048 @ linux version
	155
	156	eor r1, r1, #L_PTE_PRESENT \| L_PTE_YOUNG \| L_PTE_WRITE \| L_PTE_DIRTY
	157
	158	bic r2, r1, #PTE_SMALL_AP_MASK
	159	bic r2, r2, #PTE_TYPE_MASK
	160	orr r2, r2, #PTE_TYPE_SMALL
	161
	162	tst r1, #L_PTE_USER @ User?
	163	orrne r2, r2, #PTE_SMALL_AP_URO_SRW
	164
	165	tst r1, #L_PTE_WRITE \| L_PTE_DIRTY @ Write and Dirty?
	166	orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
	167
	168	tst r1, #L_PTE_PRESENT \| L_PTE_YOUNG @ Present and Young?
	169	movne r2, #0
	170
	171	str r2, [r0] @ hardware version
	172	mov r0, r0
	173	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	174	mcr p15, 0, r0, c7, c10, 4 @ drain WB
d090ddda	175	#endif
1da177e4 LT	176	mov pc, lr
	177
	178	__INIT
	179
	180	.type __sa110_setup, #function
	181	__sa110_setup:
	182	mov r10, #0
	183	mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
	184	mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4
d090ddda	185	#ifdef CONFIG_MMU
1da177e4	186	mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
d090ddda	187	#endif
1da177e4 LT	188	mrc p15, 0, r0, c1, c0 @ get control register v4
	189	ldr r5, sa110_cr1_clear
	190	bic r0, r0, r5
	191	ldr r5, sa110_cr1_set
	192	orr r0, r0, r5
	193	mov pc, lr
	194	.size __sa110_setup, . - __sa110_setup
	195
	196	/*
	197	* R
	198	* .RVI ZFRS BLDP WCAM
	199	* ..01 0001 ..11 1101
	200	*
	201	*/
	202	.type sa110_cr1_clear, #object
	203	.type sa110_cr1_set, #object
	204	sa110_cr1_clear:
	205	.word 0x3f3f
	206	sa110_cr1_set:
	207	.word 0x113d
	208
	209	__INITDATA
	210
	211	/*
	212	* Purpose : Function pointers used to access above functions - all calls
	213	* come through these
	214	*/
	215
	216	.type sa110_processor_functions, #object
	217	ENTRY(sa110_processor_functions)
	218	.word v4_early_abort
	219	.word cpu_sa110_proc_init
	220	.word cpu_sa110_proc_fin
	221	.word cpu_sa110_reset
	222	.word cpu_sa110_do_idle
	223	.word cpu_sa110_dcache_clean_area
	224	.word cpu_sa110_switch_mm
	225	.word cpu_sa110_set_pte
	226	.size sa110_processor_functions, . - sa110_processor_functions
	227
	228	.section ".rodata"
	229
	230	.type cpu_arch_name, #object
	231	cpu_arch_name:
	232	.asciz "armv4"
	233	.size cpu_arch_name, . - cpu_arch_name
	234
	235	.type cpu_elf_name, #object
	236	cpu_elf_name:
	237	.asciz "v4"
	238	.size cpu_elf_name, . - cpu_elf_name
	239
	240	.type cpu_sa110_name, #object
	241	cpu_sa110_name:
	242	.asciz "StrongARM-110"
	243	.size cpu_sa110_name, . - cpu_sa110_name
	244
	245	.align
	246
02b7dd12	247	.section ".proc.info.init", #alloc, #execinstr
1da177e4 LT	248
	249	.type __sa110_proc_info,#object
	250	__sa110_proc_info:
	251	.long 0x4401a100
	252	.long 0xfffffff0
	253	.long PMD_TYPE_SECT \| \
	254	PMD_SECT_BUFFERABLE \| \
	255	PMD_SECT_CACHEABLE \| \
	256	PMD_SECT_AP_WRITE \| \
	257	PMD_SECT_AP_READ
8799ee9f RK	258	.long PMD_TYPE_SECT \| \
	259	PMD_SECT_AP_WRITE \| \
	260	PMD_SECT_AP_READ
1da177e4 LT	261	b __sa110_setup
	262	.long cpu_arch_name
	263	.long cpu_elf_name
	264	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_26BIT \| HWCAP_FAST_MULT
	265	.long cpu_sa110_name
	266	.long sa110_processor_functions
	267	.long v4wb_tlb_fns
	268	.long v4wb_user_fns
	269	.long v4wb_cache_fns
	270	.size __sa110_proc_info, . - __sa110_proc_info