[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mm / cache-v6.S

/*
 *  linux/arch/arm/mm/cache-v6.S
 *
 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This is the "shell" of the ARMv6 processor support.
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>

#include "proc-macros.S"

#define HARVARD_CACHE
#define CACHE_LINE_SIZE		32
#define D_CACHE_LINE_SIZE	32
#define BTB_FLUSH_SIZE		8

/*
 *	v6_flush_cache_all()
 *
 *	Flush the entire cache.
 *
 *	It is assumed that:
 */
ENTRY(v6_flush_kern_cache_all)
	mov	r0, #0
#ifdef HARVARD_CACHE
	mcr	p15, 0, r0, c7, c14, 0		@ D cache clean+invalidate
	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
#else
	mcr	p15, 0, r0, c7, c15, 0		@ Cache clean+invalidate
#endif
	mov	pc, lr

/*
 *	v6_flush_cache_all()
 *
 *	Flush all TLB entries in a particular address space
 *
 *	- mm    - mm_struct describing address space
 */
ENTRY(v6_flush_user_cache_all)
	/*FALLTHROUGH*/

/*
 *	v6_flush_cache_range(start, end, flags)
 *
 *	Flush a range of TLB entries in the specified address space.
 *
 *	- start - start address (may not be aligned)
 *	- end   - end address (exclusive, may not be aligned)
 *	- flags	- vm_area_struct flags describing address space
 *
 *	It is assumed that:
 *	- we have a VIPT cache.
 */
ENTRY(v6_flush_user_cache_range)
	mov	pc, lr

/*
 *	v6_coherent_kern_range(start,end)
 *
 *	Ensure that the I and D caches are coherent within specified
 *	region.  This is typically used when code has been written to
 *	a memory region, and will be executed.
 *
 *	- start   - virtual start address of region
 *	- end     - virtual end address of region
 *
 *	It is assumed that:
 *	- the Icache does not read data from the write buffer
 */
ENTRY(v6_coherent_kern_range)
	/* FALLTHROUGH */

/*
 *	v6_coherent_user_range(start,end)
 *
 *	Ensure that the I and D caches are coherent within specified
 *	region.  This is typically used when code has been written to
 *	a memory region, and will be executed.
 *
 *	- start   - virtual start address of region
 *	- end     - virtual end address of region
 *
 *	It is assumed that:
 *	- the Icache does not read data from the write buffer
 */
ENTRY(v6_coherent_user_range)
	bic	r0, r0, #CACHE_LINE_SIZE - 1
1:
#ifdef HARVARD_CACHE
	mcr	p15, 0, r0, c7, c10, 1		@ clean D line
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I line
#endif
	mcr	p15, 0, r0, c7, c5, 7		@ invalidate BTB entry
	add	r0, r0, #BTB_FLUSH_SIZE
	mcr	p15, 0, r0, c7, c5, 7		@ invalidate BTB entry
	add	r0, r0, #BTB_FLUSH_SIZE
	mcr	p15, 0, r0, c7, c5, 7		@ invalidate BTB entry
	add	r0, r0, #BTB_FLUSH_SIZE
	mcr	p15, 0, r0, c7, c5, 7		@ invalidate BTB entry
	add	r0, r0, #BTB_FLUSH_SIZE
	cmp	r0, r1
	blo	1b
#ifdef HARVARD_CACHE
	mov	r0, #0
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer
#endif
	mov	pc, lr

/*
 *	v6_flush_kern_dcache_page(kaddr)
 *
 *	Ensure that the data held in the page kaddr is written back
 *	to the page in question.
 *
 *	- kaddr   - kernel address (guaranteed to be page aligned)
 */
ENTRY(v6_flush_kern_dcache_page)
	add	r1, r0, #PAGE_SZ
1:
#ifdef HARVARD_CACHE
	mcr	p15, 0, r0, c7, c14, 1		@ clean & invalidate D line
#else
	mcr	p15, 0, r0, c7, c15, 1		@ clean & invalidate unified line
#endif	
	add	r0, r0, #D_CACHE_LINE_SIZE
	cmp	r0, r1
	blo	1b
#ifdef HARVARD_CACHE
	mov	r0, #0
	mcr	p15, 0, r0, c7, c10, 4
#endif
	mov	pc, lr


/*
 *	v6_dma_inv_range(start,end)
 *
 *	Invalidate the data cache within the specified region; we will
 *	be performing a DMA operation in this region and we want to
 *	purge old data in the cache.
 *
 *	- start   - virtual start address of region
 *	- end     - virtual end address of region
 */
ENTRY(v6_dma_inv_range)
	tst	r0, #D_CACHE_LINE_SIZE - 1
	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
#ifdef HARVARD_CACHE
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D line
#else
	mcrne	p15, 0, r0, c7, c11, 1		@ clean unified line
#endif
	tst	r1, #D_CACHE_LINE_SIZE - 1
	bic	r1, r1, #D_CACHE_LINE_SIZE - 1
#ifdef HARVARD_CACHE
	mcrne	p15, 0, r1, c7, c14, 1		@ clean & invalidate D line
#else
	mcrne	p15, 0, r1, c7, c15, 1		@ clean & invalidate unified line
#endif
1:
#ifdef HARVARD_CACHE
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D line
#else
	mcr	p15, 0, r0, c7, c7, 1		@ invalidate unified line
#endif
	add	r0, r0, #D_CACHE_LINE_SIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer
	mov	pc, lr

/*
 *	v6_dma_clean_range(start,end)
 *	- start   - virtual start address of region
 *	- end     - virtual end address of region
 */
ENTRY(v6_dma_clean_range)
	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
1:
#ifdef HARVARD_CACHE
	mcr	p15, 0, r0, c7, c10, 1		@ clean D line
#else
	mcr	p15, 0, r0, c7, c11, 1		@ clean unified line
#endif
	add	r0, r0, #D_CACHE_LINE_SIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer
	mov	pc, lr

/*
 *	v6_dma_flush_range(start,end)
 *	- start   - virtual start address of region
 *	- end     - virtual end address of region
 */
ENTRY(v6_dma_flush_range)
	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
1:
#ifdef HARVARD_CACHE
	mcr	p15, 0, r0, c7, c14, 1		@ clean & invalidate D line
#else
	mcr	p15, 0, r0, c7, c15, 1		@ clean & invalidate line
#endif
	add	r0, r0, #D_CACHE_LINE_SIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer
	mov	pc, lr

	__INITDATA

	.type	v6_cache_fns, #object
ENTRY(v6_cache_fns)
	.long	v6_flush_kern_cache_all
	.long	v6_flush_user_cache_all
	.long	v6_flush_user_cache_range
	.long	v6_coherent_kern_range
	.long	v6_coherent_user_range
	.long	v6_flush_kern_dcache_page
	.long	v6_dma_inv_range
	.long	v6_dma_clean_range
	.long	v6_dma_flush_range
	.size	v6_cache_fns, . - v6_cache_fns
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/cache-v6.S
	3	*
	4	* Copyright (C) 2001 Deep Blue Solutions Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This is the "shell" of the ARMv6 processor support.
	11	*/
	12	#include <linux/linkage.h>
	13	#include <linux/init.h>
	14	#include <asm/assembler.h>
	15
	16	#include "proc-macros.S"
	17
	18	#define HARVARD_CACHE
	19	#define CACHE_LINE_SIZE 32
	20	#define D_CACHE_LINE_SIZE 32
217874fe	21	#define BTB_FLUSH_SIZE 8
1da177e4 LT	22
	23	/*
	24	* v6_flush_cache_all()
	25	*
	26	* Flush the entire cache.
	27	*
	28	* It is assumed that:
	29	*/
	30	ENTRY(v6_flush_kern_cache_all)
	31	mov r0, #0
	32	#ifdef HARVARD_CACHE
	33	mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
	34	mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
	35	#else
	36	mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
	37	#endif
	38	mov pc, lr
	39
	40	/*
	41	* v6_flush_cache_all()
	42	*
	43	* Flush all TLB entries in a particular address space
	44	*
	45	* - mm - mm_struct describing address space
	46	*/
	47	ENTRY(v6_flush_user_cache_all)
	48	/FALLTHROUGH/
	49
	50	/*
	51	* v6_flush_cache_range(start, end, flags)
	52	*
	53	* Flush a range of TLB entries in the specified address space.
	54	*
	55	* - start - start address (may not be aligned)
	56	* - end - end address (exclusive, may not be aligned)
	57	* - flags - vm_area_struct flags describing address space
	58	*
	59	* It is assumed that:
	60	* - we have a VIPT cache.
	61	*/
	62	ENTRY(v6_flush_user_cache_range)
	63	mov pc, lr
	64
	65	/*
	66	* v6_coherent_kern_range(start,end)
	67	*
	68	* Ensure that the I and D caches are coherent within specified
	69	* region. This is typically used when code has been written to
	70	* a memory region, and will be executed.
	71	*
	72	* - start - virtual start address of region
	73	* - end - virtual end address of region
	74	*
	75	* It is assumed that:
	76	* - the Icache does not read data from the write buffer
	77	*/
	78	ENTRY(v6_coherent_kern_range)
	79	/* FALLTHROUGH */
	80
	81	/*
	82	* v6_coherent_user_range(start,end)
	83	*
	84	* Ensure that the I and D caches are coherent within specified
	85	* region. This is typically used when code has been written to
86	* a memory region, and will be executed.
87	*
88	* - start - virtual start address of region
89	* - end - virtual end address of region
90	*
91	* It is assumed that:
92	* - the Icache does not read data from the write buffer
93	*/
94	ENTRY(v6_coherent_user_range)
95	bic r0, r0, #CACHE_LINE_SIZE - 1
96	1:
97	#ifdef HARVARD_CACHE
98	mcr p15, 0, r0, c7, c10, 1 @ clean D line
99	mcr p15, 0, r0, c7, c5, 1 @ invalidate I line
100	#endif
101	mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
217874fe GF	102	add r0, r0, #BTB_FLUSH_SIZE
	103	mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
	104	add r0, r0, #BTB_FLUSH_SIZE
	105	mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
	106	add r0, r0, #BTB_FLUSH_SIZE
	107	mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
	108	add r0, r0, #BTB_FLUSH_SIZE
1da177e4 LT	109	cmp r0, r1
	110	blo 1b
	111	#ifdef HARVARD_CACHE
	112	mov r0, #0
	113	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
	114	#endif
	115	mov pc, lr
	116
	117	/*
	118	* v6_flush_kern_dcache_page(kaddr)
	119	*
	120	* Ensure that the data held in the page kaddr is written back
	121	* to the page in question.
	122	*
	123	* - kaddr - kernel address (guaranteed to be page aligned)
	124	*/
	125	ENTRY(v6_flush_kern_dcache_page)
	126	add r1, r0, #PAGE_SZ
	127	1:
	128	#ifdef HARVARD_CACHE
	129	mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
	130	#else
	131	mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate unified line
	132	#endif
	133	add r0, r0, #D_CACHE_LINE_SIZE
	134	cmp r0, r1
	135	blo 1b
	136	#ifdef HARVARD_CACHE
	137	mov r0, #0
	138	mcr p15, 0, r0, c7, c10, 4
	139	#endif
	140	mov pc, lr
	141
	142
	143	/*
	144	* v6_dma_inv_range(start,end)
	145	*
	146	* Invalidate the data cache within the specified region; we will
	147	* be performing a DMA operation in this region and we want to
	148	* purge old data in the cache.
	149	*
	150	* - start - virtual start address of region
	151	* - end - virtual end address of region
	152	*/
	153	ENTRY(v6_dma_inv_range)
	154	tst r0, #D_CACHE_LINE_SIZE - 1
	155	bic r0, r0, #D_CACHE_LINE_SIZE - 1
	156	#ifdef HARVARD_CACHE
	157	mcrne p15, 0, r0, c7, c10, 1 @ clean D line
	158	#else
	159	mcrne p15, 0, r0, c7, c11, 1 @ clean unified line
	160	#endif
	161	tst r1, #D_CACHE_LINE_SIZE - 1
	162	bic r1, r1, #D_CACHE_LINE_SIZE - 1
	163	#ifdef HARVARD_CACHE
	164	mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D line
	165	#else
	166	mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line
	167	#endif
	168	1:
	169	#ifdef HARVARD_CACHE
	170	mcr p15, 0, r0, c7, c6, 1 @ invalidate D line
	171	#else
	172	mcr p15, 0, r0, c7, c7, 1 @ invalidate unified line
173	#endif
174	add r0, r0, #D_CACHE_LINE_SIZE
175	cmp r0, r1
176	blo 1b
177	mov r0, #0
178	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
179	mov pc, lr
180
181	/*
182	* v6_dma_clean_range(start,end)
183	* - start - virtual start address of region
184	* - end - virtual end address of region
185	*/
186	ENTRY(v6_dma_clean_range)
187	bic r0, r0, #D_CACHE_LINE_SIZE - 1
188	1:
189	#ifdef HARVARD_CACHE
190	mcr p15, 0, r0, c7, c10, 1 @ clean D line
191	#else
192	mcr p15, 0, r0, c7, c11, 1 @ clean unified line
193	#endif
194	add r0, r0, #D_CACHE_LINE_SIZE
195	cmp r0, r1
196	blo 1b
197	mov r0, #0
198	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
199	mov pc, lr
200
201	/*
202	* v6_dma_flush_range(start,end)
203	* - start - virtual start address of region
204	* - end - virtual end address of region
205	*/
206	ENTRY(v6_dma_flush_range)
207	bic r0, r0, #D_CACHE_LINE_SIZE - 1
208	1:
209	#ifdef HARVARD_CACHE
210	mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
211	#else
212	mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate line
213	#endif
214	add r0, r0, #D_CACHE_LINE_SIZE
215	cmp r0, r1
216	blo 1b
217	mov r0, #0
218	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
219	mov pc, lr
220
221	__INITDATA
222
223	.type v6_cache_fns, #object
224	ENTRY(v6_cache_fns)
225	.long v6_flush_kern_cache_all
226	.long v6_flush_user_cache_all
227	.long v6_flush_user_cache_range
228	.long v6_coherent_kern_range
229	.long v6_coherent_user_range
230	.long v6_flush_kern_dcache_page
231	.long v6_dma_inv_range
232	.long v6_dma_clean_range
233	.long v6_dma_flush_range
234	.size v6_cache_fns, . - v6_cache_fns