[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-ux500 / cpu-db8500.c

/*
 * Copyright (C) 2008-2009 ST-Ericsson SA
 *
 * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2, as
 * published by the Free Software Foundation.
 *
 */
#include <linux/types.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/mfd/abx500/ab8500.h>
#include <linux/mfd/dbx500-prcmu.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/regulator/machine.h>
#include <linux/platform_data/pinctrl-nomadik.h>
#include <linux/random.h>

#include <asm/pmu.h>
#include <asm/mach/map.h>
#include <asm/mach/arch.h>

#include "setup.h"
#include "devices.h"
#include "irqs.h"

#include "devices-db8500.h"
#include "ste-dma40-db8500.h"
#include "db8500-regs.h"
#include "board-mop500.h"
#include "id.h"

/* minimum static i/o mapping required to boot U8500 platforms */
static struct map_desc u8500_uart_io_desc[] __initdata = {
	__IO_DEV_DESC(U8500_UART0_BASE, SZ_4K),
	__IO_DEV_DESC(U8500_UART2_BASE, SZ_4K),
};
/*  U8500 and U9540 common io_desc */
static struct map_desc u8500_common_io_desc[] __initdata = {
	/* SCU base also covers GIC CPU BASE and TWD with its 4K page */
	__IO_DEV_DESC(U8500_SCU_BASE, SZ_4K),
	__IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K),
	__IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K),
	__IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
	__IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K),

	__IO_DEV_DESC(U8500_CLKRST1_BASE, SZ_4K),
	__IO_DEV_DESC(U8500_CLKRST2_BASE, SZ_4K),
	__IO_DEV_DESC(U8500_CLKRST3_BASE, SZ_4K),
	__IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K),
	__IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K),

	__IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K),
	__IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
	__IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
	__IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
};

/* U8500 IO map specific description */
static struct map_desc u8500_io_desc[] __initdata = {
	__IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K),
	__IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),

};

/* U9540 IO map specific description */
static struct map_desc u9540_io_desc[] __initdata = {
	__IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K + SZ_8K),
	__IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K + SZ_8K),
};

void __init u8500_map_io(void)
{
	/*
	 * Map the UARTs early so that the DEBUG_LL stuff continues to work.
	 */
	iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc));

	ux500_map_io();

	iotable_init(u8500_common_io_desc, ARRAY_SIZE(u8500_common_io_desc));

	if (cpu_is_ux540_family())
		iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc));
	else
		iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
}

static struct resource db8500_pmu_resources[] = {
	[0] = {
		.start		= IRQ_DB8500_PMU,
		.end		= IRQ_DB8500_PMU,
		.flags		= IORESOURCE_IRQ,
	},
};

/*
 * The PMU IRQ lines of two cores are wired together into a single interrupt.
 * Bounce the interrupt to the other core if it's not ours.
 */
static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler)
{
	irqreturn_t ret = handler(irq, dev);
	int other = !smp_processor_id();

	if (ret == IRQ_NONE && cpu_online(other))
		irq_set_affinity(irq, cpumask_of(other));

	/*
	 * We should be able to get away with the amount of IRQ_NONEs we give,
	 * while still having the spurious IRQ detection code kick in if the
	 * interrupt really starts hitting spuriously.
	 */
	return ret;
}

struct arm_pmu_platdata db8500_pmu_platdata = {
	.handle_irq		= db8500_pmu_handler,
};

static struct platform_device db8500_pmu_device = {
	.name			= "arm-pmu",
	.id			= -1,
	.num_resources		= ARRAY_SIZE(db8500_pmu_resources),
	.resource		= db8500_pmu_resources,
	.dev.platform_data	= &db8500_pmu_platdata,
};

static struct platform_device *platform_devs[] __initdata = {
	&u8500_dma40_device,
	&db8500_pmu_device,
};

static resource_size_t __initdata db8500_gpio_base[] = {
	U8500_GPIOBANK0_BASE,
	U8500_GPIOBANK1_BASE,
	U8500_GPIOBANK2_BASE,
	U8500_GPIOBANK3_BASE,
	U8500_GPIOBANK4_BASE,
	U8500_GPIOBANK5_BASE,
	U8500_GPIOBANK6_BASE,
	U8500_GPIOBANK7_BASE,
	U8500_GPIOBANK8_BASE,
};

static void __init db8500_add_gpios(struct device *parent)
{
	struct nmk_gpio_platform_data pdata = {
		.supports_sleepmode = true,
	};

	dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base),
			 IRQ_DB8500_GPIO0, &pdata);
	dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE);
}

static int usb_db8500_rx_dma_cfg[] = {
	DB8500_DMA_DEV38_USB_OTG_IEP_1_9,
	DB8500_DMA_DEV37_USB_OTG_IEP_2_10,
	DB8500_DMA_DEV36_USB_OTG_IEP_3_11,
	DB8500_DMA_DEV19_USB_OTG_IEP_4_12,
	DB8500_DMA_DEV18_USB_OTG_IEP_5_13,
	DB8500_DMA_DEV17_USB_OTG_IEP_6_14,
	DB8500_DMA_DEV16_USB_OTG_IEP_7_15,
	DB8500_DMA_DEV39_USB_OTG_IEP_8
};

static int usb_db8500_tx_dma_cfg[] = {
	DB8500_DMA_DEV38_USB_OTG_OEP_1_9,
	DB8500_DMA_DEV37_USB_OTG_OEP_2_10,
	DB8500_DMA_DEV36_USB_OTG_OEP_3_11,
	DB8500_DMA_DEV19_USB_OTG_OEP_4_12,
	DB8500_DMA_DEV18_USB_OTG_OEP_5_13,
	DB8500_DMA_DEV17_USB_OTG_OEP_6_14,
	DB8500_DMA_DEV16_USB_OTG_OEP_7_15,
	DB8500_DMA_DEV39_USB_OTG_OEP_8
};

static const char *db8500_read_soc_id(void)
{
	void __iomem *uid = __io_address(U8500_BB_UID_BASE);

	/* Throw these device-specific numbers into the entropy pool */
	add_device_randomness(uid, 0x14);
	return kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x",
			 readl((u32 *)uid+0),
			 readl((u32 *)uid+1), readl((u32 *)uid+2),
			 readl((u32 *)uid+3), readl((u32 *)uid+4));
}

static struct device * __init db8500_soc_device_init(void)
{
	const char *soc_id = db8500_read_soc_id();

	return ux500_soc_device_init(soc_id);
}

/*
 * This function is called from the board init
 */
struct device * __init u8500_init_devices(void)
{
	struct device *parent;
	int i;

	parent = db8500_soc_device_init();

	db8500_add_rtc(parent);
	db8500_add_gpios(parent);
	db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);

	for (i = 0; i < ARRAY_SIZE(platform_devs); i++)
		platform_devs[i]->dev.parent = parent;

	platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));

	return parent;
}

#ifdef CONFIG_MACH_UX500_DT

/* TODO: Once all pieces are DT:ed, remove completely. */
static struct device * __init u8500_of_init_devices(void)
{
	struct device *parent = db8500_soc_device_init();

	db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);

	u8500_dma40_device.dev.parent = parent;

	/*
	 * Devices to be DT:ed:
	 *   u8500_dma40_device  = todo
	 *   db8500_pmu_device   = done
	 *   db8500_prcmu_device = done
	 */
	platform_device_register(&u8500_dma40_device);

	return parent;
}

static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
	/* Requires call-back bindings. */
	OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
	/* Requires DMA bindings. */
	OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
	OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
	OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
	OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
	OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  &mop500_sdi0_data),
	OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  &mop500_sdi1_data),
	OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2",  &mop500_sdi2_data),
	OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4",  &mop500_sdi4_data),
	/* Requires clock name bindings. */
	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL),
	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL),
	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL),
	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL),
	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL),
	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL),
	OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL),
	OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL),
	OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL),
	OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
	OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
	OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
	OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
			&db8500_prcmu_pdata),
	OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL),
	/* Requires device name bindings. */
	OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
		"pinctrl-db8500", NULL),
	/* Requires clock name and DMA bindings. */
	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
		"ux500-msp-i2s.0", &msp0_platform_data),
	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
		"ux500-msp-i2s.1", &msp1_platform_data),
	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000,
		"ux500-msp-i2s.2", &msp2_platform_data),
	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
		"ux500-msp-i2s.3", &msp3_platform_data),
	{},
};

static const struct of_device_id u8500_local_bus_nodes[] = {
	/* only create devices below soc node */
	{ .compatible = "stericsson,db8500", },
	{ .compatible = "stericsson,db8500-prcmu", },
	{ .compatible = "simple-bus"},
	{ },
};

static void __init u8500_init_machine(void)
{
	struct device *parent = NULL;

	/* Pinmaps must be in place before devices register */
	if (of_machine_is_compatible("st-ericsson,mop500"))
		mop500_pinmaps_init();
	else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
		snowball_pinmaps_init();
		mop500_snowball_ethernet_clock_enable();
	} else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
		hrefv60_pinmaps_init();
	else if (of_machine_is_compatible("st-ericsson,ccu9540")) {}
		/* TODO: Add pinmaps for ccu9540 board. */

	/* TODO: Export SoC, USB, cpu-freq and DMA40 */
	parent = u8500_of_init_devices();

	/* automatically probe child nodes of db8500 device */
	of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent);
}

static const char * stericsson_dt_platform_compat[] = {
	"st-ericsson,u8500",
	"st-ericsson,u8540",
	"st-ericsson,u9500",
	"st-ericsson,u9540",
	NULL,
};

DT_MACHINE_START(U8500_DT, "ST-Ericsson Ux5x0 platform (Device Tree Support)")
	.smp            = smp_ops(ux500_smp_ops),
	.map_io		= u8500_map_io,
	.init_irq	= ux500_init_irq,
	/* we re-use nomadik timer here */
	.init_time	= ux500_timer_init,
	.init_machine	= u8500_init_machine,
	.init_late	= NULL,
	.dt_compat      = stericsson_dt_platform_compat,
MACHINE_END

#endif
Commit	Line	Data
aa44ef4d	1	/*
c15def1c	2	* Copyright (C) 2008-2009 ST-Ericsson SA
aa44ef4d SK	3	*
	4	* Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2, as
	8	* published by the Free Software Foundation.
	9	*
	10	*/
	11	#include <linux/types.h>
	12	#include <linux/init.h>
	13	#include <linux/device.h>
	14	#include <linux/amba/bus.h>
aa90eb9d	15	#include <linux/interrupt.h>
aa44ef4d SK	16	#include <linux/irq.h>
aa44ef4d SK	17	#include <linux/platform_device.h>
cc2c1334	18	#include <linux/io.h>
3a8e39c9	19	#include <linux/mfd/abx500/ab8500.h>
661c6af0	20	#include <linux/mfd/dbx500-prcmu.h>
fa86a764 LJ	21	#include <linux/of.h>
	22	#include <linux/of_platform.h>
	23	#include <linux/regulator/machine.h>
7cb15e10	24	#include <linux/platform_data/pinctrl-nomadik.h>
4040d10a	25	#include <linux/random.h>
aa44ef4d	26
5caecb44	27	#include <asm/pmu.h>
aa44ef4d	28	#include <asm/mach/map.h>
fa86a764	29	#include <asm/mach/arch.h>
b8edf848	30
e657bcf6 AB	31	#include "setup.h"
e657bcf6 AB	32	#include "devices.h"
eba52748	33	#include "irqs.h"
94bdc0e2	34
fbf1eadf	35	#include "devices-db8500.h"
6f3f3c3f	36	#include "ste-dma40-db8500.h"
174e7796	37	#include "db8500-regs.h"
fa86a764	38	#include "board-mop500.h"
7a4f2609	39	#include "id.h"
fbf1eadf	40
aa44ef4d	41	/* minimum static i/o mapping required to boot U8500 platforms */
abf12d71	42	static struct map_desc u8500_uart_io_desc[] __initdata = {
92389ca8 RV	43	__IO_DEV_DESC(U8500_UART0_BASE, SZ_4K),
92389ca8 RV	44	__IO_DEV_DESC(U8500_UART2_BASE, SZ_4K),
abf12d71	45	};
bc71c096 LW	46	/* U8500 and U9540 common io_desc */
bc71c096 LW	47	static struct map_desc u8500_common_io_desc[] __initdata = {
215e83d9 LW	48	/* SCU base also covers GIC CPU BASE and TWD with its 4K page */
215e83d9 LW	49	__IO_DEV_DESC(U8500_SCU_BASE, SZ_4K),
92389ca8 RV	50	__IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K),
92389ca8 RV	51	__IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K),
92389ca8	52	__IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
92389ca8 RV	53	__IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K),
	54
	55	__IO_DEV_DESC(U8500_CLKRST1_BASE, SZ_4K),
	56	__IO_DEV_DESC(U8500_CLKRST2_BASE, SZ_4K),
	57	__IO_DEV_DESC(U8500_CLKRST3_BASE, SZ_4K),
	58	__IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K),
	59	__IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K),
	60
c9c09572	61	__IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K),
94bdc0e2 RV	62	__IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
	63	__IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
	64	__IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
ee9581d7 MJ	65	};
	66
	67	/* U8500 IO map specific description */
	68	static struct map_desc u8500_io_desc[] __initdata = {
	69	__IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K),
fcbd458e	70	__IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
ee9581d7 MJ	71
	72	};
	73
	74	/* U9540 IO map specific description */
	75	static struct map_desc u9540_io_desc[] __initdata = {
	76	__IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K + SZ_8K),
	77	__IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K + SZ_8K),
75a36ee0 RV	78	};
75a36ee0 RV	79
abf12d71	80	void __init u8500_map_io(void)
f946738c	81	{
abf12d71 RV	82	/*
	83	* Map the UARTs early so that the DEBUG_LL stuff continues to work.
	84	*/
	85	iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc));
f946738c	86
abf12d71	87	ux500_map_io();
f946738c	88
bc71c096	89	iotable_init(u8500_common_io_desc, ARRAY_SIZE(u8500_common_io_desc));
75a36ee0	90
e1bbb55d	91	if (cpu_is_ux540_family())
ee9581d7 MJ	92	iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc));
	93	else
	94	iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
aa44ef4d SK	95	}
aa44ef4d SK	96
aa90eb9d RV	97	static struct resource db8500_pmu_resources[] = {
	98	[0] = {
	99	.start = IRQ_DB8500_PMU,
	100	.end = IRQ_DB8500_PMU,
	101	.flags = IORESOURCE_IRQ,
	102	},
	103	};
	104
	105	/*
	106	* The PMU IRQ lines of two cores are wired together into a single interrupt.
	107	* Bounce the interrupt to the other core if it's not ours.
	108	*/
	109	static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler)
	110	{
	111	irqreturn_t ret = handler(irq, dev);
	112	int other = !smp_processor_id();
	113
	114	if (ret == IRQ_NONE && cpu_online(other))
	115	irq_set_affinity(irq, cpumask_of(other));
	116
	117	/*
	118	* We should be able to get away with the amount of IRQ_NONEs we give,
	119	* while still having the spurious IRQ detection code kick in if the
	120	* interrupt really starts hitting spuriously.
	121	*/
	122	return ret;
	123	}
	124
3a8e39c9	125	struct arm_pmu_platdata db8500_pmu_platdata = {
aa90eb9d RV	126	.handle_irq = db8500_pmu_handler,
	127	};
	128
	129	static struct platform_device db8500_pmu_device = {
	130	.name = "arm-pmu",
df3d17e0	131	.id = -1,
aa90eb9d RV	132	.num_resources = ARRAY_SIZE(db8500_pmu_resources),
	133	.resource = db8500_pmu_resources,
	134	.dev.platform_data = &db8500_pmu_platdata,
	135	};
	136
	137	static struct platform_device *platform_devs[] __initdata = {
	138	&u8500_dma40_device,
	139	&db8500_pmu_device,
	140	};
	141
01afdd13 RV	142	static resource_size_t __initdata db8500_gpio_base[] = {
	143	U8500_GPIOBANK0_BASE,
	144	U8500_GPIOBANK1_BASE,
	145	U8500_GPIOBANK2_BASE,
	146	U8500_GPIOBANK3_BASE,
	147	U8500_GPIOBANK4_BASE,
	148	U8500_GPIOBANK5_BASE,
	149	U8500_GPIOBANK6_BASE,
	150	U8500_GPIOBANK7_BASE,
	151	U8500_GPIOBANK8_BASE,
	152	};
	153
18403424	154	static void __init db8500_add_gpios(struct device *parent)
01afdd13 RV	155	{
01afdd13 RV	156	struct nmk_gpio_platform_data pdata = {
c15def1c	157	.supports_sleepmode = true,
01afdd13 RV	158	};
01afdd13 RV	159
18403424	160	dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base),
01afdd13	161	IRQ_DB8500_GPIO0, &pdata);
f4828336	162	dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE);
01afdd13 RV	163	}
01afdd13 RV	164
6f3f3c3f MYK	165	static int usb_db8500_rx_dma_cfg[] = {
	166	DB8500_DMA_DEV38_USB_OTG_IEP_1_9,
	167	DB8500_DMA_DEV37_USB_OTG_IEP_2_10,
	168	DB8500_DMA_DEV36_USB_OTG_IEP_3_11,
	169	DB8500_DMA_DEV19_USB_OTG_IEP_4_12,
	170	DB8500_DMA_DEV18_USB_OTG_IEP_5_13,
	171	DB8500_DMA_DEV17_USB_OTG_IEP_6_14,
	172	DB8500_DMA_DEV16_USB_OTG_IEP_7_15,
	173	DB8500_DMA_DEV39_USB_OTG_IEP_8
	174	};
	175
	176	static int usb_db8500_tx_dma_cfg[] = {
	177	DB8500_DMA_DEV38_USB_OTG_OEP_1_9,
	178	DB8500_DMA_DEV37_USB_OTG_OEP_2_10,
	179	DB8500_DMA_DEV36_USB_OTG_OEP_3_11,
	180	DB8500_DMA_DEV19_USB_OTG_OEP_4_12,
	181	DB8500_DMA_DEV18_USB_OTG_OEP_5_13,
	182	DB8500_DMA_DEV17_USB_OTG_OEP_6_14,
	183	DB8500_DMA_DEV16_USB_OTG_OEP_7_15,
	184	DB8500_DMA_DEV39_USB_OTG_OEP_8
	185	};
	186
eda413c2 LJ	187	static const char *db8500_read_soc_id(void)
	188	{
	189	void __iomem *uid = __io_address(U8500_BB_UID_BASE);
	190
4040d10a LW	191	/* Throw these device-specific numbers into the entropy pool */
4040d10a LW	192	add_device_randomness(uid, 0x14);
eda413c2	193	return kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x",
33c8abce	194	readl((u32 *)uid+0),
eda413c2 LJ	195	readl((u32 )uid+1), readl((u32 )uid+2),
	196	readl((u32 )uid+3), readl((u32 )uid+4));
	197	}
	198
	199	static struct device * __init db8500_soc_device_init(void)
	200	{
	201	const char *soc_id = db8500_read_soc_id();
	202
	203	return ux500_soc_device_init(soc_id);
	204	}
	205
aa44ef4d SK	206	/*
	207	* This function is called from the board init
	208	*/
3210c053	209	struct device * __init u8500_init_devices(void)
aa44ef4d	210	{
eda413c2	211	struct device *parent;
b024a0c8	212	int i;
eda413c2 LJ	213
	214	parent = db8500_soc_device_init();
	215
	216	db8500_add_rtc(parent);
	217	db8500_add_gpios(parent);
	218	db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
fbf1eadf	219
f65c1982 LJ	220	for (i = 0; i < ARRAY_SIZE(platform_devs); i++)
	221	platform_devs[i]->dev.parent = parent;
	222
	223	platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
	224
	225	return parent;
	226	}
	227
fa86a764 LJ	228	#ifdef CONFIG_MACH_UX500_DT
fa86a764 LJ	229
f65c1982	230	/* TODO: Once all pieces are DT:ed, remove completely. */
fa86a764	231	static struct device * __init u8500_of_init_devices(void)
f65c1982	232	{
fa86a764	233	struct device *parent = db8500_soc_device_init();
f65c1982	234
f65c1982 LJ	235	db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
f65c1982 LJ	236
38cd8c5d	237	u8500_dma40_device.dev.parent = parent;
b024a0c8	238
08d05026 LJ	239	/*
	240	* Devices to be DT:ed:
	241	* u8500_dma40_device = todo
da384870	242	* db8500_pmu_device = done
dee42ebe	243	* db8500_prcmu_device = done
08d05026	244	*/
38cd8c5d	245	platform_device_register(&u8500_dma40_device);
aa44ef4d	246
eda413c2	247	return parent;
aa44ef4d	248	}
fa86a764 LJ	249
	250	static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
	251	/* Requires call-back bindings. */
	252	OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
cece5c40	253	/* Requires DMA bindings. */
fa86a764 LJ	254	OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
	255	OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
	256	OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
fa86a764 LJ	257	OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat),
	258	OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data),
	259	OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data),
	260	OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", &mop500_sdi2_data),
	261	OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data),
	262	/* Requires clock name bindings. */
	263	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
	264	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
	265	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL),
	266	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL),
	267	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL),
	268	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL),
	269	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL),
	270	OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL),
	271	OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL),
	272	OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL),
	273	OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL),
	274	OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
	275	OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
	276	OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
05ec260e LW	277	OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
05ec260e LW	278	&db8500_prcmu_pdata),
7d2b64f9	279	OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL),
fa86a764	280	/* Requires device name bindings. */
e32af889	281	OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
9fcb4cc2	282	"pinctrl-db8500", NULL),
fa86a764 LJ	283	/* Requires clock name and DMA bindings. */
	284	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
	285	"ux500-msp-i2s.0", &msp0_platform_data),
	286	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
	287	"ux500-msp-i2s.1", &msp1_platform_data),
	288	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000,
	289	"ux500-msp-i2s.2", &msp2_platform_data),
	290	OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
	291	"ux500-msp-i2s.3", &msp3_platform_data),
	292	{},
	293	};
	294
	295	static const struct of_device_id u8500_local_bus_nodes[] = {
	296	/* only create devices below soc node */
	297	{ .compatible = "stericsson,db8500", },
	298	{ .compatible = "stericsson,db8500-prcmu", },
	299	{ .compatible = "simple-bus"},
	300	{ },
	301	};
	302
	303	static void __init u8500_init_machine(void)
	304	{
	305	struct device *parent = NULL;
	306
	307	/* Pinmaps must be in place before devices register */
	308	if (of_machine_is_compatible("st-ericsson,mop500"))
	309	mop500_pinmaps_init();
265c3c0a	310	else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
fa86a764	311	snowball_pinmaps_init();
265c3c0a LJ	312	mop500_snowball_ethernet_clock_enable();
265c3c0a LJ	313	} else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
fa86a764	314	hrefv60_pinmaps_init();
58e5b9e3 LJ	315	else if (of_machine_is_compatible("st-ericsson,ccu9540")) {}
58e5b9e3 LJ	316	/* TODO: Add pinmaps for ccu9540 board. */
fa86a764 LJ	317
	318	/* TODO: Export SoC, USB, cpu-freq and DMA40 */
	319	parent = u8500_of_init_devices();
	320
	321	/* automatically probe child nodes of db8500 device */
	322	of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent);
fa86a764 LJ	323	}
fa86a764 LJ	324
79b40753 LJ	325	static const char * stericsson_dt_platform_compat[] = {
	326	"st-ericsson,u8500",
	327	"st-ericsson,u8540",
	328	"st-ericsson,u9500",
	329	"st-ericsson,u9540",
fa86a764 LJ	330	NULL,
	331	};
	332
46c1bf81	333	DT_MACHINE_START(U8500_DT, "ST-Ericsson Ux5x0 platform (Device Tree Support)")
f44c5fd1	334	.smp = smp_ops(ux500_smp_ops),
fa86a764 LJ	335	.map_io = u8500_map_io,
	336	.init_irq = ux500_init_irq,
	337	/* we re-use nomadik timer here */
6bb27d73	338	.init_time = ux500_timer_init,
fa86a764	339	.init_machine = u8500_init_machine,
74a1c9ab	340	.init_late = NULL,
79b40753	341	.dt_compat = stericsson_dt_platform_compat,
fa86a764 LJ	342	MACHINE_END
	343
	344	#endif